Lines Matching refs:CTLZ
402 setOperationAction(ISD::CTLZ, MVT::i32,
407 setOperationAction({ISD::CTLZ, ISD::CTLZ_ZERO_UNDEF}, MVT::i32, Custom);
410 setOperationAction(ISD::CTLZ, XLenVT, Expand);
412 setOperationAction(ISD::CTLZ, MVT::i32, Expand);
915 setOperationAction({ISD::CTLZ, ISD::CTTZ, ISD::CTPOP}, VT, Expand);
924 setOperationAction({ISD::CTLZ, ISD::CTLZ_ZERO_UNDEF,
1271 setOperationAction({ISD::BITREVERSE, ISD::CTLZ, ISD::CTLZ_ZERO_UNDEF,
1280 {ISD::CTLZ, ISD::CTLZ_ZERO_UNDEF, ISD::CTTZ_ZERO_UNDEF}, VT,
5510 // EltSize. Hence, we can do min(Res, EltSize) for CTLZ.
5511 if (Op.getOpcode() == ISD::CTLZ)
5972 OP_CASE(CTLZ)
6027 VP_CASE(CTLZ) // VP_CTLZ
7065 case ISD::CTLZ:
12425 case ISD::CTLZ:
15921 // This represents either CTTZ or CTLZ instruction.
15949 CountZeroes.getOpcode() != ISD::CTLZ &&
15964 CountZeroes = DAG.getNode(ISD::CTLZ, SDLoc(CountZeroes),