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Searched refs:CSR_READ_1 (Results 1 – 25 of 28) sorted by relevance

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/freebsd/sys/dev/ste/
H A Dif_ste.c195 CSR_WRITE_1(sc, reg, CSR_READ_1(sc, reg) | (x))
198 CSR_WRITE_1(sc, reg, CSR_READ_1(sc, reg) & ~(x))
211 val = CSR_READ_1(sc, STE_PHYCTL); in ste_mii_bitbang_read()
429 rxcfg = CSR_READ_1(sc, STE_RX_MODE); in ste_rxfilter()
453 CSR_READ_1(sc, STE_RX_MODE); in ste_rxfilter()
814 CSR_READ_1(sc, STE_STAT_RX_BCAST); in ste_stats_clear()
815 CSR_READ_1(sc, STE_STAT_RX_MCAST); in ste_stats_clear()
816 CSR_READ_1(sc, STE_STAT_RX_LOST); in ste_stats_clear()
821 CSR_READ_1(sc, STE_STAT_TX_BCAST); in ste_stats_clear()
822 CSR_READ_1(sc, STE_STAT_TX_MCAST); in ste_stats_clear()
[all …]
H A Dif_stereg.h492 #define CSR_READ_1(sc, reg) \ macro
/freebsd/sys/dev/re/
H A Dif_re.c359 CSR_READ_1(sc, RL_EECMD) | x)
363 CSR_READ_1(sc, RL_EECMD) & ~x)
413 if (CSR_READ_1(sc, RL_EECMD) & RL_EE_DATAOUT) in re_eeprom_getword()
458 rval = CSR_READ_1(sc, RL_GMEDIASTAT); in re_gmii_readreg()
556 rval = CSR_READ_1(sc, RL_MEDIASTAT); in re_miibus_readreg()
741 if (!(CSR_READ_1(sc, RL_COMMAND) & RL_CMD_RESET)) in re_reset()
1324 cfg = CSR_READ_1(sc, RL_CFG2); in re_attach()
1361 cfg = CSR_READ_1(sc, RL_CFG2); in re_attach()
1559 cfg = CSR_READ_1(sc, sc->rl_cfg1); in re_attach()
1562 cfg = CSR_READ_1(sc, sc->rl_cfg5); in re_attach()
[all …]
/freebsd/sys/dev/vge/
H A Dif_vge.c258 if (CSR_READ_1(sc, VGE_EECMD) & VGE_EECMD_EDONE) in vge_eeprom_getword()
299 dest[i] = CSR_READ_1(sc, VGE_PAR0 + i); in vge_read_eeprom()
312 if (CSR_READ_1(sc, VGE_MIISTS) & VGE_MIISTS_IIDL) in vge_miipoll_stop()
332 if (CSR_READ_1(sc, VGE_MIISTS) & VGE_MIISTS_IIDL) in vge_miipoll_start()
349 if ((CSR_READ_1(sc, VGE_MIISTS) & VGE_MIISTS_IIDL) == 0) in vge_miipoll_start()
377 if ((CSR_READ_1(sc, VGE_MIICMD) & VGE_MIICMD_RCMD) == 0) in vge_miibus_readreg()
413 if ((CSR_READ_1(sc, VGE_MIICMD) & VGE_MIICMD_WCMD) == 0) in vge_miibus_writereg()
482 if ((CSR_READ_1(sc, VGE_CAMCTL) & VGE_CAMCTL_WRITE) == 0) in vge_cam_set()
520 cfg = CSR_READ_1(sc, VGE_RXCFG); in vge_setvlan()
573 rxcfg = CSR_READ_1(sc, VGE_RXCTL); in vge_rxfilter()
[all …]
H A Dif_vgevar.h228 #define CSR_READ_1(sc, reg) \ macro
232 CSR_WRITE_1(sc, reg, CSR_READ_1(sc, reg) | (x))
239 CSR_WRITE_1(sc, reg, CSR_READ_1(sc, reg) & ~(x))
/freebsd/sys/dev/vr/
H A Dif_vr.c253 if ((CSR_READ_1(sc, VR_MIICMD) & VR_MIICMD_READ_ENB) == 0) in vr_miibus_readreg()
277 if ((CSR_READ_1(sc, VR_MIICMD) & VR_MIICMD_WRITE_ENB) == 0) in vr_miibus_writereg()
322 cr0 = CSR_READ_1(sc, VR_CR0); in vr_miibus_statchg()
323 cr1 = CSR_READ_1(sc, VR_CR1); in vr_miibus_statchg()
347 fc = CSR_READ_1(sc, VR_FLOWCR1); in vr_miibus_statchg()
360 fc = CSR_READ_1(sc, VR_MISC_CR0); in vr_miibus_statchg()
418 if ((CSR_READ_1(sc, VR_CAMCTL) & VR_CAMCTL_WRITE) == 0) in vr_cam_data()
482 rxfilt = CSR_READ_1(sc, VR_RXCFG); in vr_set_filter()
544 if (!(CSR_READ_1(sc, VR_CR1) & VR_CR1_RESET)) in vr_reset()
723 if ((CSR_READ_1(sc, VR_EECSR) & VR_EECSR_LOAD) == 0) in vr_attach()
[all …]
H A Dif_vrreg.h754 #define CSR_READ_1(sc, reg) bus_read_1(sc->vr_res, reg) macro
756 #define VR_SETBIT(sc, reg, x) CSR_WRITE_1(sc, reg, CSR_READ_1(sc, reg) | (x))
757 #define VR_CLRBIT(sc, reg, x) CSR_WRITE_1(sc, reg, CSR_READ_1(sc, reg) & ~(x))
/freebsd/sys/dev/rl/
H A Dif_rl.c265 CSR_READ_1(sc, RL_EECMD) | x)
269 CSR_READ_1(sc, RL_EECMD) & ~x)
323 if (CSR_READ_1(sc, RL_EECMD) & RL_EE_DATAOUT) in rl_eeprom_getword()
365 val = CSR_READ_1(sc, RL_MII); in rl_mii_bitbang_read()
422 return (CSR_READ_1(sc, RL_MEDIASTAT)); in rl_miibus_readreg()
572 if (!(CSR_READ_1(sc, RL_COMMAND) & RL_CMD_RESET)) in rl_reset()
776 eaddr[i] = CSR_READ_1(sc, RL_IDR0 + i); in rl_attach()
1134 while((CSR_READ_1(sc, RL_COMMAND) & RL_CMD_EMPTY_RXBUF) == 0) { in rl_rxeof()
1919 if ((CSR_READ_1(sc, RL_COMMAND) & in rl_stop()
2056 v = CSR_READ_1(sc, sc->rl_cfg1); in rl_setwol()
[all …]
H A Dif_rlreg.h958 #define CSR_READ_1(sc, reg) \ macro
965 CSR_WRITE_1(sc, offset, CSR_READ_1(sc, offset) | (val))
968 CSR_WRITE_1(sc, offset, CSR_READ_1(sc, offset) & ~(val))
/freebsd/sys/dev/ipw/
H A Dif_ipwreg.h326 #define CSR_READ_1(sc, reg) \ macro
353 CSR_READ_1((sc), IPW_CSR_INDIRECT_DATA))
/freebsd/sys/dev/fxp/
H A Dif_fxp.c334 while (CSR_READ_1(sc, FXP_CSR_SCB_COMMAND) && --i) in fxp_scb_wait()
337 flowctl.b[0] = CSR_READ_1(sc, FXP_CSR_FC_THRESH); in fxp_scb_wait()
338 flowctl.b[1] = CSR_READ_1(sc, FXP_CSR_FC_STATUS); in fxp_scb_wait()
340 CSR_READ_1(sc, FXP_CSR_SCB_COMMAND), in fxp_scb_wait()
341 CSR_READ_1(sc, FXP_CSR_SCB_STATACK), in fxp_scb_wait()
342 CSR_READ_1(sc, FXP_CSR_SCB_RUSCUS), flowctl.w); in fxp_scb_wait()
910 CSR_WRITE_1(sc, FXP_CSR_PMDR, CSR_READ_1(sc, FXP_CSR_PMDR)); in fxp_attach()
1106 CSR_READ_1(sc, FXP_CSR_PMDR)); in fxp_resume()
1681 tmp = CSR_READ_1(sc, FXP_CSR_SCB_STATACK); in fxp_poll()
1720 while ((statack = CSR_READ_1(sc, FXP_CSR_SCB_STATACK)) != 0) { in fxp_intr()
[all …]
H A Dif_fxpvar.h244 #define CSR_READ_1(sc, reg) bus_read_1(sc->fxp_res[0], reg) macro
/freebsd/sys/dev/xl/
H A Dif_xl.c453 macctl = CSR_READ_1(sc, XL_W3_MAC_CTRL); in xl_miibus_statchg()
625 rxfilt = CSR_READ_1(sc, XL_W5_RX_FILTER); in xl_rxfilter_90x()
685 rxfilt = CSR_READ_1(sc, XL_W5_RX_FILTER); in xl_rxfilter_90xB()
814 (CSR_READ_1(sc, XL_W3_MAC_CTRL) & ~XL_MACCTRL_DUPLEX)); in xl_setmode()
2077 while ((txstat = CSR_READ_1(sc, XL_TX_STATUS))) { in xl_txeoc()
2300 *p++ = CSR_READ_1(sc, XL_W6_CARRIER_LOST + i); in xl_stats_update()
2316 CSR_READ_1(sc, XL_W4_BADSSD); in xl_stats_update()
2815 macctl = CSR_READ_1(sc, XL_W3_MAC_CTRL); in xl_init_locked()
2941 if (CSR_READ_1(sc, XL_W3_MAC_CTRL) & XL_MACCTRL_DUPLEX) in xl_ifmedia_sts()
2950 if (CSR_READ_1(sc, XL_W3_MAC_CTRL) & XL_MACCTRL_DUPLEX) in xl_ifmedia_sts()
H A Dif_xlreg.h663 #define CSR_READ_1(sc, reg) \ macro
/freebsd/sys/dev/msk/
H A Dif_msk.c1206 sc->msk_ramsize = CSR_READ_1(sc, B2_E_0) * 4; in mskc_setup_rambuffer()
1660 eaddr[i] = CSR_READ_1(sc, B2_MAC_1 + (port * 8) + i); in msk_attach()
1774 sc->msk_hw_id = CSR_READ_1(sc, B2_CHIP_ID); in mskc_attach()
1775 sc->msk_hw_rev = (CSR_READ_1(sc, B2_MAC_CFG) >> 4) & 0x0f; in mskc_attach()
1813 sc->msk_pmd = CSR_READ_1(sc, B2_PMD_TYP); in mskc_attach()
1816 if ((CSR_READ_1(sc, B2_Y2_HW_RES) & CFG_DUAL_MAC_MSK) == in mskc_attach()
1818 if (!(CSR_READ_1(sc, B2_Y2_CLK_GATE) & Y2_STATUS_LNK2_INAC)) in mskc_attach()
3384 status = CSR_READ_1(sc, MR_ADDR(sc_if->msk_port, GMAC_IRQ_SRC)); in msk_intr_gmac()
3812 CSR_READ_1(sc, MR_ADDR(sc_if->msk_port, GMAC_IRQ_SRC)); in msk_init_locked()
4067 CSR_READ_1(sc, RB_ADDR(sc_if->msk_rxq, RB_CTRL)); in msk_set_rambuffer()
[all …]
H A Dif_mskreg.h2135 #define CSR_READ_1(sc, reg) \ macro
2157 CSR_READ_1((sc_if)->msk_softc, (reg))
/freebsd/sys/dev/stge/
H A Dif_stge.c255 val = CSR_READ_1(sc, STGE_PhyCtrl); in stge_mii_bitbang_read()
294 error = CSR_READ_1(sc, STGE_PhyCtrl); in stge_miibus_readreg()
585 sc->sc_PhyCtrl = CSR_READ_1(sc, STGE_PhyCtrl) & in stge_attach()
979 v = CSR_READ_1(sc, STGE_WakeEvent); in stge_setwol()
1025 v = CSR_READ_1(sc, STGE_WakeEvent); in stge_resume()
1947 v = CSR_READ_1(sc, STGE_PhySet); in stge_reset()
H A Dif_stgereg.h100 #define CSR_READ_1(_sc, reg) \ macro
/freebsd/sys/dev/my/
H A Dif_myreg.h399 #define CSR_READ_1(sc, reg) \ macro
H A Dif_my.c853 eaddr[i] = CSR_READ_1(sc, MY_PAR0 + i); in my_attach()
/freebsd/sys/dev/lge/
H A Dif_lge.c642 if (CSR_READ_1(sc, LGE_RXCMDFREE_8BIT) == 0) in lge_list_rx_init()
962 txdone = CSR_READ_1(sc, LGE_TXDMADONE_8BIT); in lge_txeof()
1161 if (CSR_READ_1(sc, LGE_TXCMDFREE_8BIT) == 0) in lge_start_locked()
H A Dif_lgereg.h547 #define CSR_READ_1(sc, reg) \ macro
/freebsd/sys/dev/iwi/
H A Dif_iwireg.h572 #define CSR_READ_1(sc, reg) \ macro
/freebsd/sys/dev/sk/
H A Dif_skreg.h1285 #define CSR_READ_1(sc, reg) \ macro
H A Dif_sk.c389 return(CSR_READ_1(sc, SK_WIN_BASE + SK_REG(reg))); in sk_win_read_1()
391 return(CSR_READ_1(sc, reg)); in sk_win_read_1()

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