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Searched refs:CPUID (Results 1 – 25 of 28) sorted by relevance

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/freebsd/crypto/openssl/doc/man3/
H A DOPENSSL_ia32cap.pod21 successive executions of the CPUID instruction, after which any OPENSSL_ia32cap
27 Further CPUID information can be found in the Intel(R) Architecture
34 resulting from the following execution of CPUID.(EAX=01H).EDX and
35 CPUID.(EAX=01H).ECX:
82 resulting from the following execution of CPUID.(EAX=07H,ECX=0H).EBX and
83 CPUID.(EAX=07H,ECX=0H).ECX:
119 resulting from the following execution of CPUID.(EAX=07H,ECX=0H).EDX and
120 CPUID.(EAX=07H,ECX=1H).EAX:
141 resulting from the following execution of CPUID.(EAX=07H,ECX=1H).EDX and
142 CPUID.(EAX=07H,ECX=1H).EBX:
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/freebsd/contrib/llvm-project/llvm/include/llvm/MC/
H A DMCInstrAnalysis.h139 unsigned CPUID) const { in isZeroIdiom() argument
164 unsigned CPUID) const { in isDependencyBreaking() argument
165 return isZeroIdiom(MI, Mask, CPUID); in isDependencyBreaking()
175 unsigned CPUID) const { in isOptimizableRegisterMove() argument
H A DMCSubtargetInfo.h226 unsigned CPUID) const { in resolveVariantSchedClass() argument
/freebsd/contrib/llvm-project/llvm/lib/MC/
H A DMCSchedule.cpp80 unsigned CPUID = getProcessorID(); in computeInstrLatency() local
84 STI.resolveVariantSchedClass(SchedClass, &Inst, &MCII, CPUID); in computeInstrLatency()
134 unsigned CPUID = getProcessorID(); in getReciprocalThroughput() local
136 SchedClass = STI.resolveVariantSchedClass(SchedClass, &Inst, &MCII, CPUID); in getReciprocalThroughput()
/freebsd/lib/libpmc/pmu-events/
H A DREADME108 CPUID,Version,Dir/path/name,Type
124 CPUID:
125 CPUID is an arch-specific char string, that can be used
131 CPUID == 'GenuineIntel-6-2E' (on x86).
132 CPUID == '004b0100' (PVR value in Powerpc)
/freebsd/crypto/openssl/crypto/
H A Dbuild.info66 # CPUID support. We need to add that explicitly in every shared library and
67 # provider module that uses it. ctype.c is included here because the CPUID
76 # We only need to include the CPUID stuff in the legacy provider when it's a
85 # Implementations are now spread across several libraries, so the CPUID define
/freebsd/contrib/llvm-project/llvm/tools/llvm-mca/Views/
H A DInstructionInfoView.cpp204 unsigned CPUID = SM.getProcessorID(); in collectData() local
209 STI.resolveVariantSchedClass(SchedClassID, &Inst, &MCII, CPUID); in collectData()
/freebsd/sys/amd64/amd64/
H A Dapic_vector.S236 movl PCPU(CPUID), %eax
/freebsd/sys/i386/i386/
H A Dswtch.S56 movl PCPU(CPUID), %esi
146 movl PCPU(CPUID),%esi
H A Dapic_vector.S326 movl PCPU(CPUID), %eax
/freebsd/contrib/llvm-project/llvm/include/llvm/BinaryFormat/
H A DMinidump.h167 support::ulittle32_t CPUID; member
/freebsd/contrib/llvm-project/llvm/lib/MCA/
H A DInstrBuilder.cpp546 unsigned CPUID = SM.getProcessorID(); in getVariantSchedClassID() local
549 STI.resolveVariantSchedClass(SchedClassID, &MCI, &MCII, CPUID); in getVariantSchedClassID()
/freebsd/contrib/llvm-project/openmp/runtime/src/
H A Dz_Windows_NT-586_asm.asm90 cpuid ; Query the CPUID for the current processor
650 cpuid ; Query the CPUID for the current processor
/freebsd/contrib/llvm-project/llvm/lib/ObjectYAML/
H A DMinidumpYAML.cpp168 mapRequiredHex(IO, "CPUID", Info.CPUID); in mapping()
/freebsd/contrib/llvm-project/clang/lib/CodeGen/TargetBuiltins/
H A DRISCV.cpp1056 Value *CPUID = Builder.CreateAlignedLoad(StructTy->getTypeAtIndex(Index), in EmitRISCVCpuIs() local
1058 return CPUID; in EmitRISCVCpuIs()
/freebsd/sys/x86/conf/
H A DNOTES621 # CPU control pseudo-device. Provides access to MSRs, CPUID info and
/freebsd/contrib/llvm-project/llvm/lib/Target/X86/
H A DX86ScheduleAtom.td880 def : InstRW<[AtomWrite01_121], (instrs CPUID)>;
H A DX86InstrSystem.td516 def CPUID : I<0xA2, RawFrm, (outs), (ins), "cpuid", []>, TB;
H A DX86SchedSkylakeClient.td1386 def: InstRW<[SKLWriteResGroup184], (instrs CPUID, RDTSC)>;
H A DX86SchedBroadwell.td1325 def: InstRW<[BWWriteResGroup159], (instrs CPUID)>;
H A DX86SchedHaswell.td1562 def: InstRW<[HWWriteResGroup149], (instrs CPUID, RDTSC)>;
H A DX86SchedLunarlakeP.td1166 def : InstRW<[LNLPWriteResGroupX34], (instrs CPUID)>;
H A DX86SchedSkylakeServer.td2067 def: InstRW<[SKXWriteResGroup207], (instrs CPUID, RDTSC)>;
H A DX86SchedAlderlakeP.td781 def : InstRW<[ADLPWriteResGroup34], (instrs CPUID)>;
H A DX86SchedIceLake.td2097 def: InstRW<[ICXWriteResGroup207], (instrs CPUID, RDTSC)>;

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