1# 2# NOTES -- Lines that can be cut/pasted into kernel and hints configs. 3# 4# This file contains machine dependent kernel configuration notes. For 5# machine independent notes, look in /sys/conf/NOTES. For notes shared 6# with amd64, look in /sys/x86/conf/NOTES. 7# 8# 9 10 11##################################################################### 12# SMP OPTIONS: 13# 14# The apic device enables the use of the I/O APIC for interrupt delivery. 15# The apic device can be used in both UP and SMP kernels, but is required 16# for SMP kernels. Thus, the apic device is not strictly an SMP option, 17# but it is a prerequisite for SMP. 18# 19# Notes: 20# 21# HTT CPUs should only be used if they are enabled in the BIOS. For 22# the ACPI case, ACPI only correctly tells us about any HTT CPUs if 23# they are enabled. However, most HTT systems do not list HTT CPUs 24# in the MP Table if they are enabled, thus we guess at the HTT CPUs 25# for the MP Table case. However, we shouldn't try to guess and use 26# these CPUs if HTT is disabled. Thus, HTT guessing is only enabled 27# for the MP Table if the user explicitly asks for it via the 28# MPTABLE_FORCE_HTT option. Do NOT use this option if you have HTT 29# disabled in your BIOS. 30 31# Mandatory: 32device apic # I/O apic 33 34# Optional: 35options MPTABLE_FORCE_HTT # Enable HTT CPUs with the MP Table 36 37 38##################################################################### 39# CPU OPTIONS 40 41# 42# You must specify at least one CPU (the one you intend to run on); 43# deleting the specification for CPUs you don't need to use may make 44# parts of the system run faster. 45# 46cpu I486_CPU 47cpu I586_CPU # aka Pentium(tm) 48cpu I686_CPU # aka Pentium Pro(tm) 49 50# 51# Options for CPU features. 52# 53# CPU_ATHLON_SSE_HACK tries to enable SSE instructions when the BIOS has 54# forgotten to enable them. 55# 56# CPU_BLUELIGHTNING_3X enables triple-clock mode on IBM Blue Lightning 57# CPU if CPU supports it. The default is double-clock mode on 58# BlueLightning CPU box. 59# 60# CPU_BLUELIGHTNING_FPU_OP_CACHE enables FPU operand cache on IBM 61# BlueLightning CPU. It works only with Cyrix FPU, and this option 62# should not be used with Intel FPU. 63# 64# CPU_BTB_EN enables branch target buffer on Cyrix 5x86 (NOTE 1). 65# 66# CPU_CYRIX_NO_LOCK enables weak locking for the entire address space 67# of Cyrix 6x86 and 6x86MX CPUs by setting the NO_LOCK bit of CCR1. 68# Otherwise, the NO_LOCK bit of CCR1 is cleared. (NOTE 3) 69# 70# CPU_DIRECT_MAPPED_CACHE sets L1 cache of Cyrix 486DLC CPU in direct 71# mapped mode. Default is 2-way set associative mode. 72# 73# CPU_DISABLE_5X86_LSSER disables load store serialize (i.e., enables 74# reorder). This option should not be used if you use memory mapped 75# I/O device(s). 76# 77# CPU_ELAN enables support for AMDs ElanSC520 CPU. 78# CPU_ELAN_PPS enables precision timestamp code. 79# CPU_ELAN_XTAL sets the clock crystal frequency in Hz. 80# 81# CPU_ENABLE_LONGRUN enables support for Transmeta Crusoe LongRun 82# technology which allows to restrict power consumption of the CPU by 83# using group of hw.crusoe.* sysctls. 84# 85# CPU_FASTER_5X86_FPU enables faster FPU exception handler. 86# 87# CPU_GEODE is for the SC1100 Geode embedded processor. This option 88# is necessary because the i8254 timecounter is toast. 89# 90# CPU_I486_ON_386 enables CPU cache on i486 based CPU upgrade products 91# for i386 machines. 92# 93# CPU_IORT defines I/O clock delay time (NOTE 1). Default values of 94# I/O clock delay time on Cyrix 5x86 and 6x86 are 0 and 7,respectively 95# (no clock delay). 96# 97# CPU_L2_LATENCY specifies the L2 cache latency value. This option is used 98# only when CPU_PPRO2CELERON is defined and Mendocino Celeron is detected. 99# The default value is 5. 100# 101# CPU_LOOP_EN prevents flushing the prefetch buffer if the destination 102# of a jump is already present in the prefetch buffer on Cyrix 5x86(NOTE 103# 1). 104# 105# CPU_PPRO2CELERON enables L2 cache of Mendocino Celeron CPUs. This option 106# is useful when you use Socket 8 to Socket 370 converter, because most Pentium 107# Pro BIOSs do not enable L2 cache of Mendocino Celeron CPUs. 108# 109# CPU_RSTK_EN enables return stack on Cyrix 5x86 (NOTE 1). 110# 111# CPU_SOEKRIS enables support www.soekris.com hardware. 112# 113# CPU_SUSP_HLT enables suspend on HALT. If this option is set, CPU 114# enters suspend mode following execution of HALT instruction. 115# 116# CPU_UPGRADE_HW_CACHE eliminates unneeded cache flush instruction(s). 117# 118# CPU_WT_ALLOC enables write allocation on Cyrix 6x86/6x86MX and AMD 119# K5/K6/K6-2 CPUs. 120# 121# CYRIX_CACHE_WORKS enables CPU cache on Cyrix 486 CPUs with cache 122# flush at hold state. 123# 124# CYRIX_CACHE_REALLY_WORKS enables (1) CPU cache on Cyrix 486 CPUs 125# without cache flush at hold state, and (2) write-back CPU cache on 126# Cyrix 6x86 whose revision < 2.7 (NOTE 2). 127# 128# NO_F00F_HACK disables the hack that prevents Pentiums (and ONLY 129# Pentiums) from locking up when a LOCK CMPXCHG8B instruction is 130# executed. This option is only needed if I586_CPU is also defined, 131# and should be included for any non-Pentium CPU that defines it. 132# 133# NO_MEMORY_HOLE is an optimisation for systems with AMD K6 processors 134# which indicates that the 15-16MB range is *definitely* not being 135# occupied by an ISA memory hole. 136# 137# NOTE 1: The options, CPU_BTB_EN, CPU_LOOP_EN, CPU_IORT, 138# CPU_LOOP_EN and CPU_RSTK_EN should not be used because of CPU bugs. 139# These options may crash your system. 140# 141# NOTE 2: If CYRIX_CACHE_REALLY_WORKS is not set, CPU cache is enabled 142# in write-through mode when revision < 2.7. If revision of Cyrix 143# 6x86 >= 2.7, CPU cache is always enabled in write-back mode. 144# 145# NOTE 3: This option may cause failures for software that requires 146# locked cycles in order to operate correctly. 147# 148options CPU_ATHLON_SSE_HACK 149options CPU_BLUELIGHTNING_3X 150options CPU_BLUELIGHTNING_FPU_OP_CACHE 151options CPU_BTB_EN 152options CPU_DIRECT_MAPPED_CACHE 153options CPU_DISABLE_5X86_LSSER 154options CPU_ELAN 155options CPU_ELAN_PPS 156options CPU_ELAN_XTAL=32768000 157options CPU_ENABLE_LONGRUN 158options CPU_FASTER_5X86_FPU 159options CPU_GEODE 160options CPU_I486_ON_386 161options CPU_IORT 162options CPU_L2_LATENCY=5 163options CPU_LOOP_EN 164options CPU_PPRO2CELERON 165options CPU_RSTK_EN 166options CPU_SOEKRIS 167options CPU_SUSP_HLT 168options CPU_UPGRADE_HW_CACHE 169options CPU_WT_ALLOC 170options CYRIX_CACHE_WORKS 171options CYRIX_CACHE_REALLY_WORKS 172#options NO_F00F_HACK 173 174# Debug options 175options NPX_DEBUG # enable npx debugging 176 177# 178# Hints for the non-optional Numeric Processing eXtension driver. 179envvar hint.npx.0.flags="0x0" 180envvar hint.npx.0.irq="13" 181 182# 183# `flags' for npx0: 184# 0x01 don't use the npx registers to optimize bcopy. 185# 0x02 don't use the npx registers to optimize bzero. 186# 0x04 don't use the npx registers to optimize copyin or copyout. 187# The npx registers are normally used to optimize copying and zeroing when 188# all of the following conditions are satisfied: 189# I586_CPU is an option 190# the cpu is an i586 (perhaps not a Pentium) 191# the probe for npx0 succeeds 192# INT 16 exception handling works. 193# Then copying and zeroing using the npx registers is normally 30-100% faster. 194# The flags can be used to control cases where it doesn't work or is slower. 195# Setting them at boot time using hints works right (the optimizations 196# are not used until later in the bootstrap when npx0 is attached). 197# Flag 0x08 automatically disables the i586 optimized routines. 198# 199 200 201##################################################################### 202# HARDWARE DEVICE CONFIGURATION 203 204# 205# Optional devices: 206# 207 208# 3Dfx Voodoo Graphics, Voodoo II /dev/3dfx CDEV support. This will create 209# the /dev/3dfx0 device to work with glide implementations. This should get 210# linked to /dev/3dfx and /dev/voodoo. Note that this is not the same as 211# the tdfx DRI module from XFree86 and is completely unrelated. 212# 213# To enable Linuxulator support, one must also load linux.ko and tdfx_linux.ko. 214 215device tdfx # Enable 3Dfx Voodoo support 216 217# 218# RAID adapters 219# 220device pst 221 222# 223# Adaptec by PMC RAID controllers, Series 6/7/8 and upcoming families 224device aacraid # Container interface, CAM required 225 226# 227# Network interfaces: 228# 229 230# sbni: Granch SBNI12-xx ISA and PCI adapters 231# vmx: VMware VMXNET3 Ethernet (BSD open source) 232# wpi: Intel 3945ABG Wireless LAN controller 233# Requires the wpi firmware module 234 235# Order for ISA/EISA devices is important here 236 237envvar hint.cs.0.at="isa" 238envvar hint.cs.0.port="0x300" 239envvar hint.ed.0.at="isa" 240envvar hint.ed.0.port="0x280" 241envvar hint.ed.0.irq="5" 242envvar hint.ed.0.maddr="0xd8000" 243device sbni 244envvar hint.sbni.0.at="isa" 245envvar hint.sbni.0.port="0x210" 246envvar hint.sbni.0.irq="0xefdead" 247envvar hint.sbni.0.flags="0" 248 249##################################################################### 250 251# 252# Miscellaneous hardware: 253# 254# smapi: System Management Application Program Interface driver 255 256device smapi 257 258# 259# Laptop/Notebook options: 260# 261# See also: 262# apm under `Miscellaneous hardware' 263# above. 264 265# For older notebooks that signal a powerfail condition (external 266# power supply dropped, or battery state low) by issuing an NMI: 267 268options POWERFAIL_NMI # make it beep instead of panicing 269 270# 271# I2C Bus 272# 273# Requires 'device iicbus'. 274# 275# Supported interfaces: 276# glxiic: AMD Geode LX CS5536 System Management Bus 277# pcf: Philips PCF8584 ISA-bus controller 278# 279device glxiic # AMD Geode LX CS5536 System Management Bus 280device pcf 281envvar hint.pcf.0.at="isa" 282envvar hint.pcf.0.port="0x320" 283envvar hint.pcf.0.irq="5" 284 285# 286# glxsb is a driver for the Security Block in AMD Geode LX processors. 287# Requires 'device crypto'. 288# 289device glxsb # AMD Geode LX Security Block 290 291##################################################################### 292# ABI Emulation 293 294# Enable (32-bit) a.out binary support 295options COMPAT_AOUT 296 297##################################################################### 298# VM OPTIONS 299 300# 301# Set the number of PV entries per process. Increasing this can 302# stop panics related to heavy use of shared memory. However, that can 303# (combined with large amounts of physical memory) cause panics at 304# boot time due the kernel running out of VM space. 305# 306# If you're tweaking this, you might also want to increase the sysctls 307# "vm.v_free_min", "vm.v_free_reserved", and "vm.v_free_target". 308# 309# The value below is the one more than the default. 310# 311options PMAP_SHPGPERPROC=201 312 313# 314# Number of initial kernel page table pages used for early bootstrap. 315# This number should include enough pages to map the kernel, any 316# modules or other data loaded with the kernel by the loader, and data 317# structures allocated before the VM system is initialized such as the 318# vm_page_t array. Each page table page maps 4MB (2MB with PAE). 319# 320options NKPT=31 321 322# KSTACK_PAGES is the number of memory pages to assign to the kernel 323# stack of each thread. 324 325options KSTACK_PAGES=5 326 327# Enable detailed accounting by the PV entry allocator. 328 329options PV_STATS 330 331##################################################################### 332# Items broken on i386 that are generally available elsewhere 333 334# Device uses bus_read_8 and friends, so can't work. Remove it from lint. 335nodevice bnxt 336