Searched refs:CLK_TOP_UNIVPLL1_D4 (Results 1 – 12 of 12) sorted by relevance
30 #define CLK_TOP_UNIVPLL1_D4 23 macro
44 #define CLK_TOP_UNIVPLL1_D4 33 macro
51 #define CLK_TOP_UNIVPLL1_D4 41 macro
45 #define CLK_TOP_UNIVPLL1_D4 33 macro
69 #define CLK_TOP_UNIVPLL1_D4 59 macro
72 #define CLK_TOP_UNIVPLL1_D4 61 macro
74 #define CLK_TOP_UNIVPLL1_D4 64 macro
59 #define CLK_TOP_UNIVPLL1_D4 24 macro
34 #define CLK_TOP_UNIVPLL1_D4 24 macro
58 #define CLK_TOP_UNIVPLL1_D4 27 macro
37 #define CLK_TOP_UNIVPLL1_D4 27 macro
19 - <&topckgen CLK_TOP_UNIVPLL1_D4>: specify parent clock 156MHZ.