Searched refs:CHELSIO_T5 (Results 1 – 18 of 18) sorted by relevance
38 #define CHELSIO_T5 0x5 macro60 T5_A0 = CHELSIO_CHIP_CODE(CHELSIO_T5, 0),61 T5_A1 = CHELSIO_CHIP_CODE(CHELSIO_T5, 1),77 return (CHELSIO_CHIP_VERSION(chip) == CHELSIO_T5); in is_t5()
74 return dev->chip_version == CHELSIO_T5; in dev_is_t5()
149 case CHELSIO_T5: in c4iw_alloc_context()
142 if (chip_id(adapter) <= CHELSIO_T5) in t4vf_get_sge_params()174 if (chip_id(adapter) <= CHELSIO_T5) { in t4vf_get_sge_params()
167 if (chip_id(adap) <= CHELSIO_T5) in t4_hw_pci_read_cfg4()800 case CHELSIO_T5: in t4_get_regs_len()2662 case CHELSIO_T5: in t4_get_regs()4435 if (chip_id(adap) <= CHELSIO_T5) { in sge_intr_handler()4446 if (chip_id(adap) >= CHELSIO_T5) in sge_intr_handler()4864 if (chip_id(adap) <= CHELSIO_T5) { in le_intr_handler()5240 if (chip_id(adap) >= CHELSIO_T5) { in mac_intr_handler()5426 if (chip_id(adap) <= CHELSIO_T5) in t4_intr_enable()5859 if ((chip_id(adap) > CHELSIO_T5) && in t4_write_rss_key()5925 if (chip_id(adapter) <= CHELSIO_T5) { in t4_read_rss_vf_config()[all …]
418 #define CHELSIO_T5 0x5 macro532 return adap->params.chipid == CHELSIO_T5; in is_t5()
328 case CHELSIO_T5: in t4_connect()365 case CHELSIO_T5: in t4_connect()
1303 else if (chip_id(sc) == CHELSIO_T5 && in init_conn_params()
335 htobe16(V_FW_IQ_CMD_FL0FBMIN(chip_id(sc) <= CHELSIO_T5 ? in alloc_nm_rxq_hwq()337 V_FW_IQ_CMD_FL0FBMAX(chip_id(sc) <= CHELSIO_T5 ? in alloc_nm_rxq_hwq()365 nm_rxq->fl_db_threshold = chip_id(sc) <= CHELSIO_T5 ? 8 : 4; in alloc_nm_rxq_hwq()377 if (chip_id(sc) >= CHELSIO_T5 && cong_drop != -1) { in alloc_nm_rxq_hwq()435 htobe32(V_FW_EQ_ETH_CMD_FBMIN(chip_id(sc) <= CHELSIO_T5 ? in alloc_nm_txq_hwq()
128 if (chip_id(sc) <= CHELSIO_T5) { in t4_write_sme()
215 if (G_CHIPID(pl_rev) <= CHELSIO_T5) in t4iov_attach()
1513 MPASS(chip_id(sc) >= CHELSIO_T5 && chip_id(sc) <= CHELSIO_T6); in mk_act_open_req6()1516 if (chip_id(sc) == CHELSIO_T5) { in mk_act_open_req6()1557 MPASS(chip_id(sc) >= CHELSIO_T5 && chip_id(sc) <= CHELSIO_T6); in mk_act_open_req()1560 if (chip_id(sc) == CHELSIO_T5) { in mk_act_open_req()
1297 sc->pf = chip_id(sc) <= CHELSIO_T5 ? G_SOURCEPF(j) : G_T6_SOURCEPF(j); in t4_attach()3884 if (chip_id(sc) >= CHELSIO_T5) { in t4_map_bar_2()4683 .chip = CHELSIO_T5,7786 chip_id(sc) <= CHELSIO_T5 ? sysctl_mps_tcam : sysctl_mps_tcam_t6, in t4_sysctls()7833 if (chip_id(sc) >= CHELSIO_T5) { in t4_sysctls()8987 chip_id(sc) < CHELSIO_T5) in sysctl_reset_sensor()10057 if (chip_id(sc) <= CHELSIO_T5) in sysctl_meminfo()10176 if (chip_id(sc) > CHELSIO_T5) in sysctl_meminfo()10192 if (chip_id(sc) > CHELSIO_T5) in sysctl_meminfo()10231 MPASS(chip_id(sc) <= CHELSIO_T5); in sysctl_mps_tcam()[all …]
641 pad_shift = chip_id(sc) > CHELSIO_T5 ? X_T6_INGPADBOUNDARY_SHIFT : in setup_pad_and_pack_boundaries()3599 htobe16(V_FW_IQ_CMD_FL0FBMIN(chip_id(sc) <= CHELSIO_T5 ? in alloc_iq_fl_hwq()3601 V_FW_IQ_CMD_FL0FBMAX(chip_id(sc) <= CHELSIO_T5 ? in alloc_iq_fl_hwq()3669 if (chip_id(sc) >= CHELSIO_T5 && !(sc->flags & IS_VF) && in alloc_iq_fl_hwq()3906 if (chip_id(sc) < CHELSIO_T5) in t4_sge_set_conm_context()4268 htobe32(V_FW_EQ_CTRL_CMD_FBMIN(chip_id(sc) <= CHELSIO_T5 ? in ctrl_eq_alloc()4314 htobe32(V_FW_EQ_ETH_CMD_FBMIN(chip_id(sc) <= CHELSIO_T5 ? in eth_eq_alloc()4358 htobe32(V_FW_EQ_OFLD_CMD_FBMIN(chip_id(sc) <= CHELSIO_T5 ? in ofld_eq_alloc()5338 if (chip_id(sc) <= CHELSIO_T5) in csum_to_ctrl()
947 if (chip_id(padap) <= CHELSIO_T5) { in fill_meminfo()1052 if (chip_id(padap) > CHELSIO_T5) in fill_meminfo()1069 if (chip_id(padap) > CHELSIO_T5) in fill_meminfo()3397 if (chip_id(padap) <= CHELSIO_T5) { in collect_tid()3801 if (chip_id(padap) > CHELSIO_T5) in collect_le_tcam()
130 if (chip_id(sc) == CHELSIO_T5) { in read_pdu_limits()
1193 if (icc->sc->tt.iso && chip_id(icc->sc) >= CHELSIO_T5 && in icl_cxgbei_conn_handoff()
270 V_FW_RI_RES_WR_FBMIN(chip_id(sc) <= CHELSIO_T5 ? in create_qp()293 V_FW_RI_RES_WR_FBMIN(chip_id(sc) <= CHELSIO_T5 ? in create_qp()