12dae2a74SNavdeep Parhar /*-
2*4d846d26SWarner Losh * SPDX-License-Identifier: BSD-2-Clause
32dae2a74SNavdeep Parhar *
42dae2a74SNavdeep Parhar * Copyright (c) 2018 Chelsio Communications, Inc.
52dae2a74SNavdeep Parhar * All rights reserved.
62dae2a74SNavdeep Parhar *
72dae2a74SNavdeep Parhar * Redistribution and use in source and binary forms, with or without
82dae2a74SNavdeep Parhar * modification, are permitted provided that the following conditions
92dae2a74SNavdeep Parhar * are met:
102dae2a74SNavdeep Parhar * 1. Redistributions of source code must retain the above copyright
112dae2a74SNavdeep Parhar * notice, this list of conditions and the following disclaimer.
122dae2a74SNavdeep Parhar * 2. Redistributions in binary form must reproduce the above copyright
132dae2a74SNavdeep Parhar * notice, this list of conditions and the following disclaimer in the
142dae2a74SNavdeep Parhar * documentation and/or other materials provided with the distribution.
152dae2a74SNavdeep Parhar *
162dae2a74SNavdeep Parhar * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
172dae2a74SNavdeep Parhar * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
182dae2a74SNavdeep Parhar * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
192dae2a74SNavdeep Parhar * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
202dae2a74SNavdeep Parhar * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
212dae2a74SNavdeep Parhar * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
222dae2a74SNavdeep Parhar * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
232dae2a74SNavdeep Parhar * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
242dae2a74SNavdeep Parhar * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
252dae2a74SNavdeep Parhar * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
262dae2a74SNavdeep Parhar * SUCH DAMAGE.
272dae2a74SNavdeep Parhar */
282dae2a74SNavdeep Parhar #include <sys/cdefs.h>
292dae2a74SNavdeep Parhar #include "opt_inet.h"
302dae2a74SNavdeep Parhar #include "opt_inet6.h"
312dae2a74SNavdeep Parhar
322dae2a74SNavdeep Parhar #include <sys/param.h>
332dae2a74SNavdeep Parhar #include <sys/eventhandler.h>
342dae2a74SNavdeep Parhar #include <sys/systm.h>
352dae2a74SNavdeep Parhar #include <sys/kernel.h>
362dae2a74SNavdeep Parhar #include <sys/module.h>
372dae2a74SNavdeep Parhar #include <sys/bus.h>
382dae2a74SNavdeep Parhar #include <sys/lock.h>
392dae2a74SNavdeep Parhar #include <sys/mutex.h>
402dae2a74SNavdeep Parhar #include <sys/rwlock.h>
412dae2a74SNavdeep Parhar #include <sys/socket.h>
422dae2a74SNavdeep Parhar #include <sys/sbuf.h>
432dae2a74SNavdeep Parhar #include <netinet/in.h>
442dae2a74SNavdeep Parhar
452dae2a74SNavdeep Parhar #include "common/common.h"
462dae2a74SNavdeep Parhar #include "common/t4_msg.h"
472dae2a74SNavdeep Parhar #include "t4_smt.h"
482dae2a74SNavdeep Parhar
492dae2a74SNavdeep Parhar /*
502dae2a74SNavdeep Parhar * Module locking notes: There is a RW lock protecting the SMAC table as a
512dae2a74SNavdeep Parhar * whole plus a spinlock per SMT entry. Entry lookups and allocations happen
522dae2a74SNavdeep Parhar * under the protection of the table lock, individual entry changes happen
532dae2a74SNavdeep Parhar * while holding that entry's spinlock. The table lock nests outside the
542dae2a74SNavdeep Parhar * entry locks. Allocations of new entries take the table lock as writers so
552dae2a74SNavdeep Parhar * no other lookups can happen while allocating new entries. Entry updates
562dae2a74SNavdeep Parhar * take the table lock as readers so multiple entries can be updated in
572dae2a74SNavdeep Parhar * parallel. An SMT entry can be dropped by decrementing its reference count
582dae2a74SNavdeep Parhar * and therefore can happen in parallel with entry allocation but no entry
592dae2a74SNavdeep Parhar * can change state or increment its ref count during allocation as both of
602dae2a74SNavdeep Parhar * these perform lookups.
612dae2a74SNavdeep Parhar *
622dae2a74SNavdeep Parhar * Note: We do not take references to ifnets in this module because both
632dae2a74SNavdeep Parhar * the TOE and the sockets already hold references to the interfaces and the
642dae2a74SNavdeep Parhar * lifetime of an SMT entry is fully contained in the lifetime of the TOE.
652dae2a74SNavdeep Parhar */
662dae2a74SNavdeep Parhar
672dae2a74SNavdeep Parhar /*
682dae2a74SNavdeep Parhar * Allocate a free SMT entry. Must be called with smt_data.lock held.
692dae2a74SNavdeep Parhar */
702dae2a74SNavdeep Parhar struct smt_entry *
t4_find_or_alloc_sme(struct smt_data * s,uint8_t * smac)712dae2a74SNavdeep Parhar t4_find_or_alloc_sme(struct smt_data *s, uint8_t *smac)
722dae2a74SNavdeep Parhar {
732dae2a74SNavdeep Parhar struct smt_entry *end, *e;
742dae2a74SNavdeep Parhar struct smt_entry *first_free = NULL;
752dae2a74SNavdeep Parhar
762dae2a74SNavdeep Parhar rw_assert(&s->lock, RA_WLOCKED);
772dae2a74SNavdeep Parhar for (e = &s->smtab[0], end = &s->smtab[s->smt_size]; e != end; ++e) {
782dae2a74SNavdeep Parhar if (atomic_load_acq_int(&e->refcnt) == 0) {
792dae2a74SNavdeep Parhar if (!first_free)
802dae2a74SNavdeep Parhar first_free = e;
812dae2a74SNavdeep Parhar } else {
822dae2a74SNavdeep Parhar if (e->state == SMT_STATE_SWITCHING) {
832dae2a74SNavdeep Parhar /*
842dae2a74SNavdeep Parhar * This entry is actually in use. See if we can
852dae2a74SNavdeep Parhar * re-use it?
862dae2a74SNavdeep Parhar */
872dae2a74SNavdeep Parhar if (memcmp(e->smac, smac, ETHER_ADDR_LEN) == 0)
882dae2a74SNavdeep Parhar goto found_reuse;
892dae2a74SNavdeep Parhar }
902dae2a74SNavdeep Parhar }
912dae2a74SNavdeep Parhar }
922dae2a74SNavdeep Parhar if (first_free) {
932dae2a74SNavdeep Parhar e = first_free;
942dae2a74SNavdeep Parhar goto found;
952dae2a74SNavdeep Parhar }
962dae2a74SNavdeep Parhar return NULL;
972dae2a74SNavdeep Parhar
982dae2a74SNavdeep Parhar found:
992dae2a74SNavdeep Parhar e->state = SMT_STATE_UNUSED;
1002dae2a74SNavdeep Parhar found_reuse:
1012dae2a74SNavdeep Parhar atomic_add_int(&e->refcnt, 1);
1022dae2a74SNavdeep Parhar return e;
1032dae2a74SNavdeep Parhar }
1042dae2a74SNavdeep Parhar
1052dae2a74SNavdeep Parhar /*
1062dae2a74SNavdeep Parhar * Write an SMT entry. Must be called with the entry locked.
1072dae2a74SNavdeep Parhar */
1082dae2a74SNavdeep Parhar int
t4_write_sme(struct smt_entry * e)1092dae2a74SNavdeep Parhar t4_write_sme(struct smt_entry *e)
1102dae2a74SNavdeep Parhar {
1112dae2a74SNavdeep Parhar struct smt_data *s;
1122dae2a74SNavdeep Parhar struct sge_wrq *wrq;
1132dae2a74SNavdeep Parhar struct adapter *sc;
1142dae2a74SNavdeep Parhar struct wrq_cookie cookie;
1152dae2a74SNavdeep Parhar struct cpl_smt_write_req *req;
1162dae2a74SNavdeep Parhar struct cpl_t6_smt_write_req *t6req;
1172dae2a74SNavdeep Parhar u8 row;
1182dae2a74SNavdeep Parhar
1192dae2a74SNavdeep Parhar mtx_assert(&e->lock, MA_OWNED);
1202dae2a74SNavdeep Parhar
1212dae2a74SNavdeep Parhar MPASS(e->wrq != NULL);
1222dae2a74SNavdeep Parhar wrq = e->wrq;
1232dae2a74SNavdeep Parhar sc = wrq->adapter;
1242dae2a74SNavdeep Parhar MPASS(wrq->adapter != NULL);
1252dae2a74SNavdeep Parhar s = sc->smt;
1262dae2a74SNavdeep Parhar
1272dae2a74SNavdeep Parhar
1282dae2a74SNavdeep Parhar if (chip_id(sc) <= CHELSIO_T5) {
1292dae2a74SNavdeep Parhar /* Source MAC Table (SMT) contains 256 SMAC entries
1302dae2a74SNavdeep Parhar * organized in 128 rows of 2 entries each.
1312dae2a74SNavdeep Parhar */
1322dae2a74SNavdeep Parhar req = start_wrq_wr(wrq, howmany(sizeof(*req), 16), &cookie);
1332dae2a74SNavdeep Parhar if (req == NULL)
1342dae2a74SNavdeep Parhar return (ENOMEM);
1352dae2a74SNavdeep Parhar INIT_TP_WR(req, 0);
1362dae2a74SNavdeep Parhar /* Each row contains an SMAC pair.
1372dae2a74SNavdeep Parhar * LSB selects the SMAC entry within a row
1382dae2a74SNavdeep Parhar */
1392dae2a74SNavdeep Parhar row = (e->idx >> 1);
1402dae2a74SNavdeep Parhar if (e->idx & 1) {
1412dae2a74SNavdeep Parhar req->pfvf1 = 0x0;
1422dae2a74SNavdeep Parhar memcpy(req->src_mac1, e->smac, ETHER_ADDR_LEN);
1432dae2a74SNavdeep Parhar /* fill pfvf0/src_mac0 with entry
1442dae2a74SNavdeep Parhar * at prev index from smt-tab.
1452dae2a74SNavdeep Parhar */
1462dae2a74SNavdeep Parhar req->pfvf0 = 0x0;
1472dae2a74SNavdeep Parhar memcpy(req->src_mac0, s->smtab[e->idx - 1].smac,
1482dae2a74SNavdeep Parhar ETHER_ADDR_LEN);
1492dae2a74SNavdeep Parhar } else {
1502dae2a74SNavdeep Parhar req->pfvf0 = 0x0;
1512dae2a74SNavdeep Parhar memcpy(req->src_mac0, e->smac, ETHER_ADDR_LEN);
1522dae2a74SNavdeep Parhar /* fill pfvf1/src_mac1 with entry
1532dae2a74SNavdeep Parhar * at next index from smt-tab
1542dae2a74SNavdeep Parhar */
1552dae2a74SNavdeep Parhar req->pfvf1 = 0x0;
1562dae2a74SNavdeep Parhar memcpy(req->src_mac1, s->smtab[e->idx + 1].smac,
1572dae2a74SNavdeep Parhar ETHER_ADDR_LEN);
1582dae2a74SNavdeep Parhar }
1592dae2a74SNavdeep Parhar } else {
1602dae2a74SNavdeep Parhar /* Source MAC Table (SMT) contains 256 SMAC entries */
1612dae2a74SNavdeep Parhar t6req = start_wrq_wr(wrq, howmany(sizeof(*t6req), 16), &cookie);
1622dae2a74SNavdeep Parhar if (t6req == NULL)
1632dae2a74SNavdeep Parhar return (ENOMEM);
1642dae2a74SNavdeep Parhar INIT_TP_WR(t6req, 0);
1652dae2a74SNavdeep Parhar req = (struct cpl_smt_write_req *)t6req;
1662dae2a74SNavdeep Parhar
1672dae2a74SNavdeep Parhar /* fill pfvf0/src_mac0 from smt-tab */
1682dae2a74SNavdeep Parhar req->pfvf0 = 0x0;
1692dae2a74SNavdeep Parhar memcpy(req->src_mac0, s->smtab[e->idx].smac, ETHER_ADDR_LEN);
1702dae2a74SNavdeep Parhar row = e->idx;
1712dae2a74SNavdeep Parhar }
1722dae2a74SNavdeep Parhar OPCODE_TID(req) = htonl(MK_OPCODE_TID(CPL_SMT_WRITE_REQ, e->idx |
1732dae2a74SNavdeep Parhar V_TID_QID(e->iqid)));
1742dae2a74SNavdeep Parhar req->params = htonl(V_SMTW_NORPL(0) |
1752dae2a74SNavdeep Parhar V_SMTW_IDX(row) |
1762dae2a74SNavdeep Parhar V_SMTW_OVLAN_IDX(0));
1772dae2a74SNavdeep Parhar
1782dae2a74SNavdeep Parhar commit_wrq_wr(wrq, req, &cookie);
1792dae2a74SNavdeep Parhar
1802dae2a74SNavdeep Parhar return (0);
1812dae2a74SNavdeep Parhar }
1822dae2a74SNavdeep Parhar
1832dae2a74SNavdeep Parhar /*
1842dae2a74SNavdeep Parhar * Allocate an SMT entry for use by a switching rule.
1852dae2a74SNavdeep Parhar */
1862dae2a74SNavdeep Parhar struct smt_entry *
t4_smt_alloc_switching(struct smt_data * s,uint8_t * smac)1872dae2a74SNavdeep Parhar t4_smt_alloc_switching(struct smt_data *s, uint8_t *smac)
1882dae2a74SNavdeep Parhar {
1892dae2a74SNavdeep Parhar struct smt_entry *e;
1902dae2a74SNavdeep Parhar
1912dae2a74SNavdeep Parhar MPASS(s != NULL);
1922dae2a74SNavdeep Parhar rw_wlock(&s->lock);
1932dae2a74SNavdeep Parhar e = t4_find_or_alloc_sme(s, smac);
1942dae2a74SNavdeep Parhar rw_wunlock(&s->lock);
1952dae2a74SNavdeep Parhar return e;
1962dae2a74SNavdeep Parhar }
1972dae2a74SNavdeep Parhar
1982dae2a74SNavdeep Parhar /*
1992dae2a74SNavdeep Parhar * Sets/updates the contents of a switching SMT entry that has been allocated
2002dae2a74SNavdeep Parhar * with an earlier call to @t4_smt_alloc_switching.
2012dae2a74SNavdeep Parhar */
2022dae2a74SNavdeep Parhar int
t4_smt_set_switching(struct adapter * sc,struct smt_entry * e,uint16_t pfvf,uint8_t * smac)2032dae2a74SNavdeep Parhar t4_smt_set_switching(struct adapter *sc, struct smt_entry *e, uint16_t pfvf,
2042dae2a74SNavdeep Parhar uint8_t *smac)
2052dae2a74SNavdeep Parhar {
2062dae2a74SNavdeep Parhar int rc = 0;
2072dae2a74SNavdeep Parhar
2082dae2a74SNavdeep Parhar if (atomic_load_acq_int(&e->refcnt) == 1) {
2092dae2a74SNavdeep Parhar /* Setup the entry for the first time */
2102dae2a74SNavdeep Parhar mtx_lock(&e->lock);
21137310a98SNavdeep Parhar e->wrq = &sc->sge.ctrlq[0];
2122dae2a74SNavdeep Parhar e->iqid = sc->sge.fwq.abs_id;
2132dae2a74SNavdeep Parhar e->pfvf = pfvf;
2142dae2a74SNavdeep Parhar e->state = SMT_STATE_SWITCHING;
2152dae2a74SNavdeep Parhar memcpy(e->smac, smac, ETHER_ADDR_LEN);
2162dae2a74SNavdeep Parhar rc = t4_write_sme(e);
2172dae2a74SNavdeep Parhar mtx_unlock(&e->lock);
2182dae2a74SNavdeep Parhar }
2192dae2a74SNavdeep Parhar
2202dae2a74SNavdeep Parhar return (rc);
2212dae2a74SNavdeep Parhar }
2222dae2a74SNavdeep Parhar
2232dae2a74SNavdeep Parhar int
t4_init_smt(struct adapter * sc,int flags)2242dae2a74SNavdeep Parhar t4_init_smt(struct adapter *sc, int flags)
2252dae2a74SNavdeep Parhar {
2262dae2a74SNavdeep Parhar int i, smt_size;
2272dae2a74SNavdeep Parhar struct smt_data *s;
2282dae2a74SNavdeep Parhar
2292dae2a74SNavdeep Parhar smt_size = SMT_SIZE;
2302dae2a74SNavdeep Parhar s = malloc(sizeof(*s) + smt_size * sizeof (struct smt_entry), M_CXGBE,
2312dae2a74SNavdeep Parhar M_ZERO | flags);
2322dae2a74SNavdeep Parhar if (!s)
2332dae2a74SNavdeep Parhar return (ENOMEM);
2342dae2a74SNavdeep Parhar
2352dae2a74SNavdeep Parhar s->smt_size = smt_size;
2362dae2a74SNavdeep Parhar rw_init(&s->lock, "SMT");
2372dae2a74SNavdeep Parhar
2382dae2a74SNavdeep Parhar for (i = 0; i < smt_size; i++) {
2392dae2a74SNavdeep Parhar struct smt_entry *e = &s->smtab[i];
2402dae2a74SNavdeep Parhar
2412dae2a74SNavdeep Parhar e->idx = i;
2422dae2a74SNavdeep Parhar e->state = SMT_STATE_UNUSED;
2432dae2a74SNavdeep Parhar mtx_init(&e->lock, "SMT_E", NULL, MTX_DEF);
2442dae2a74SNavdeep Parhar atomic_store_rel_int(&e->refcnt, 0);
2452dae2a74SNavdeep Parhar }
2462dae2a74SNavdeep Parhar
2472dae2a74SNavdeep Parhar sc->smt = s;
2482dae2a74SNavdeep Parhar
2492dae2a74SNavdeep Parhar return (0);
2502dae2a74SNavdeep Parhar }
2512dae2a74SNavdeep Parhar
2522dae2a74SNavdeep Parhar int
t4_free_smt(struct smt_data * s)2532dae2a74SNavdeep Parhar t4_free_smt(struct smt_data *s)
2542dae2a74SNavdeep Parhar {
2552dae2a74SNavdeep Parhar int i;
2562dae2a74SNavdeep Parhar
2572dae2a74SNavdeep Parhar for (i = 0; i < s->smt_size; i++)
2582dae2a74SNavdeep Parhar mtx_destroy(&s->smtab[i].lock);
2592dae2a74SNavdeep Parhar rw_destroy(&s->lock);
2602dae2a74SNavdeep Parhar free(s, M_CXGBE);
2612dae2a74SNavdeep Parhar
2622dae2a74SNavdeep Parhar return (0);
2632dae2a74SNavdeep Parhar }
2642dae2a74SNavdeep Parhar
2652dae2a74SNavdeep Parhar int
do_smt_write_rpl(struct sge_iq * iq,const struct rss_header * rss,struct mbuf * m)2662dae2a74SNavdeep Parhar do_smt_write_rpl(struct sge_iq *iq, const struct rss_header *rss,
2672dae2a74SNavdeep Parhar struct mbuf *m)
2682dae2a74SNavdeep Parhar {
2692dae2a74SNavdeep Parhar struct adapter *sc = iq->adapter;
2702dae2a74SNavdeep Parhar const struct cpl_smt_write_rpl *rpl = (const void *)(rss + 1);
2712dae2a74SNavdeep Parhar unsigned int tid = GET_TID(rpl);
2722dae2a74SNavdeep Parhar unsigned int smtidx = G_TID_TID(tid);
2732dae2a74SNavdeep Parhar
2742dae2a74SNavdeep Parhar if (__predict_false(rpl->status != CPL_ERR_NONE)) {
2752dae2a74SNavdeep Parhar struct smt_entry *e = &sc->smt->smtab[smtidx];
2762dae2a74SNavdeep Parhar log(LOG_ERR,
2772dae2a74SNavdeep Parhar "Unexpected SMT_WRITE_RPL (%u) for entry at hw_idx %u\n",
2782dae2a74SNavdeep Parhar rpl->status, smtidx);
2792dae2a74SNavdeep Parhar mtx_lock(&e->lock);
2802dae2a74SNavdeep Parhar e->state = SMT_STATE_ERROR;
2812dae2a74SNavdeep Parhar mtx_unlock(&e->lock);
2822dae2a74SNavdeep Parhar return (EINVAL);
2832dae2a74SNavdeep Parhar }
2842dae2a74SNavdeep Parhar
2852dae2a74SNavdeep Parhar return (0);
2862dae2a74SNavdeep Parhar }
2872dae2a74SNavdeep Parhar
2882dae2a74SNavdeep Parhar static char
smt_state(const struct smt_entry * e)2892dae2a74SNavdeep Parhar smt_state(const struct smt_entry *e)
2902dae2a74SNavdeep Parhar {
2912dae2a74SNavdeep Parhar switch (e->state) {
2922dae2a74SNavdeep Parhar case SMT_STATE_SWITCHING: return 'X';
2932dae2a74SNavdeep Parhar case SMT_STATE_ERROR: return 'E';
2942dae2a74SNavdeep Parhar default: return 'U';
2952dae2a74SNavdeep Parhar }
2962dae2a74SNavdeep Parhar }
2972dae2a74SNavdeep Parhar
2982dae2a74SNavdeep Parhar int
sysctl_smt(SYSCTL_HANDLER_ARGS)2992dae2a74SNavdeep Parhar sysctl_smt(SYSCTL_HANDLER_ARGS)
3002dae2a74SNavdeep Parhar {
3012dae2a74SNavdeep Parhar struct adapter *sc = arg1;
3022dae2a74SNavdeep Parhar struct smt_data *smt = sc->smt;
3032dae2a74SNavdeep Parhar struct smt_entry *e;
3042dae2a74SNavdeep Parhar struct sbuf *sb;
3052dae2a74SNavdeep Parhar int rc, i, header = 0;
3062dae2a74SNavdeep Parhar
3072dae2a74SNavdeep Parhar if (smt == NULL)
3082dae2a74SNavdeep Parhar return (ENXIO);
3092dae2a74SNavdeep Parhar
3102dae2a74SNavdeep Parhar rc = sysctl_wire_old_buffer(req, 0);
3112dae2a74SNavdeep Parhar if (rc != 0)
3122dae2a74SNavdeep Parhar return (rc);
3132dae2a74SNavdeep Parhar
3142dae2a74SNavdeep Parhar sb = sbuf_new_for_sysctl(NULL, NULL, SMT_SIZE, req);
3152dae2a74SNavdeep Parhar if (sb == NULL)
3162dae2a74SNavdeep Parhar return (ENOMEM);
3172dae2a74SNavdeep Parhar
3182dae2a74SNavdeep Parhar e = &smt->smtab[0];
3192dae2a74SNavdeep Parhar for (i = 0; i < smt->smt_size; i++, e++) {
3202dae2a74SNavdeep Parhar mtx_lock(&e->lock);
3212dae2a74SNavdeep Parhar if (e->state == SMT_STATE_UNUSED)
3222dae2a74SNavdeep Parhar goto skip;
3232dae2a74SNavdeep Parhar
3242dae2a74SNavdeep Parhar if (header == 0) {
3252dae2a74SNavdeep Parhar sbuf_printf(sb, " Idx "
3262dae2a74SNavdeep Parhar "Ethernet address State Users");
3272dae2a74SNavdeep Parhar header = 1;
3282dae2a74SNavdeep Parhar }
3292dae2a74SNavdeep Parhar sbuf_printf(sb, "\n%4u %02x:%02x:%02x:%02x:%02x:%02x "
3302dae2a74SNavdeep Parhar "%c %5u",
3312dae2a74SNavdeep Parhar e->idx, e->smac[0], e->smac[1], e->smac[2],
3322dae2a74SNavdeep Parhar e->smac[3], e->smac[4], e->smac[5],
3332dae2a74SNavdeep Parhar smt_state(e), atomic_load_acq_int(&e->refcnt));
3342dae2a74SNavdeep Parhar skip:
3352dae2a74SNavdeep Parhar mtx_unlock(&e->lock);
3362dae2a74SNavdeep Parhar }
3372dae2a74SNavdeep Parhar
3382dae2a74SNavdeep Parhar rc = sbuf_finish(sb);
3392dae2a74SNavdeep Parhar sbuf_delete(sb);
3402dae2a74SNavdeep Parhar
3412dae2a74SNavdeep Parhar return (rc);
3422dae2a74SNavdeep Parhar }
343