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Searched refs:CDIV (Results 1 – 7 of 7) sorted by relevance

/freebsd/sys/dev/clk/rockchip/
H A Drk3568_cru.c329 CDIV(0, "atclk_core_div", "armclk", 0, 3, 0, 5),
331 CDIV(0, "gicclk_core_div", "armclk", 0, 3, 8, 5),
335 CDIV(0, "pclk_core_pre_div", "armclk", 0, 4, 0, 5),
337 CDIV(0, "periphclk_core_pre_div", "armclk", 0, 4, 8, 5),
349 CDIV(0, "aclk_gpu_pre_div", "clk_gpu_pre_c", 0, 6, 8, 2),
352 CDIV(0, "pclk_gpu_pre_div", "clk_gpu_pre_c", 0, 6, 12, 4),
363 CDIV(0, "hclk_npu_pre_div", "clk_npu", 0, 8, 0, 4),
364 CDIV(0, "pclk_npu_pre_div", "clk_npu", 0, 8, 4, 4),
375 CDIV(0, "clk_msch_div", "clk_ddr1x", 0, 10, 0, 2),
489 CDIV(0, "pclk_pipe_div", "aclk_pipe", 0, 29, 4, 4),
[all …]
H A Drk3399_cru.c792 CDIV(0, "aclkm_core_l_c", "armclkl", 0,
797 CDIV(0, "pclk_dbg_core_l_c", "armclkl", 0,
799 CDIV(0, "atclk_core_l_c", "armclkl", 0,
803 CDIV(0, "aclkm_core_b_c", "armclkb", 0,
809 CDIV(0, "pclken_dbg_core_b", "pclk_dbg_core_b", 0,
811 CDIV(0, "pclk_dbg_core_b_c", "armclkb", 0,
813 CDIV(0, "atclk_core_b_c", "armclkb", 0,
833 CDIV(0, "hclk_vcodec_pre_c", "aclk_vcodec_pre", 0,
839 CDIV(0, "hclk_vdu_pre_c", "aclk_vdu_pre", 0,
851 CDIV(0, "hclk_iep_pre_c", "aclk_iep_pre", 0,
[all …]
H A Drk3288_cru.c590 CDIV(0, "aclk_core_mp_s", "armclk", 0,
592 CDIV(0, "aclk_core_m0_s", "armclk", 0,
596 CDIV(0, "pclk_cpu_s", "aclk_cpu_pre", 0,
598 CDIV(0, "hclk_cpu_s", "aclk_cpu_pre", RK_CLK_COMPOSITE_DIV_EXP,
602 CDIV(0, "aclk_cpu_pre", "aclk_cpu_src", 0,
607 CDIV(0, "sclk_tsadc_s", "xin32k", 0,
613 CDIV(0, "uart4_src_s", "uart_src", 0,
629 CDIV(0, "spdif_pre_s", "spdif_src", 0,
651 CDIV(0, "pclk_peri_s", "aclk_peri_src", RK_CLK_COMPOSITE_DIV_EXP,
653 CDIV(0, "hclk_peri_s", "aclk_peri_src", RK_CLK_COMPOSITE_DIV_EXP,
[all …]
H A Drk3568_pmucru.c110 CDIV(0, "xin_osc0_div_div", "xin24m", 0, 0, 0, 5),
117 CDIV(0, "pclk_pdpmu_pre", "clk_pdpmu", 0, 2, 0, 5),
121 CDIV(0, "clk_i2c0_div", "clk_pdpmu", 0, 3, 0, 7),
124 CDIV(0, "sclk_uart0_div_div", "sclk_uart0_div_sel", 0, 4, 0, 7),
132 CDIV(0, "clk_pwm0_div", "clk_pwm0_sel", 0, 6, 0, 7),
137 CDIV(0, "clk_ref24m_div", "clk_pdpmu", 0, 7, 0, 6),
145 CDIV(0, "clk_wifi_div_div", "clk_pdpmu", 0, 8, 8, 6),
149 CDIV(0, "clk_pciephy0_div_div", "ppll_ph0", 0, 9, 0, 3),
152 CDIV(0, "clk_pciephy1_div_div", "ppll_ph0", 0, 9, 4, 3),
155 CDIV(0, "clk_pciephy2_div_div", "ppll_ph0", 0, 9, 8, 3),
H A Drk3328_cru.c864 CDIV(0, "hclk_bus_pre_c", "aclk_bus_pre", 0, 1, 8, 2),
865 CDIV(0, "pclk_bus_pre_c", "aclk_bus_pre", 0, 1, 12, 2),
907 CDIV(0, "clk_spdif_div_c", "clk_spdif_pll", 0, 12, 0, 7),
915 CDIV(0, "clk_uart0_div_c", "clk_uart0_pll", 0, 14, 0, 7),
923 CDIV(0, "clk_uart1_div_c", "clk_uart1_pll", 0, 16, 0, 7),
931 CDIV(0, "clk_uart2_div_c", "clk_uart2_pll", 0, 18, 0, 7),
944 CDIV(0, "clk_tsadc_c", "xin24m", 0, 22, 0, 10),
947 CDIV(0, "clk_saradc_c", "xin24m", 0, 23, 0, 10),
955 CDIV(0, "pclk_gmac_c", "pclk_gmac", 0, 25, 8, 3),
958 CDIV(0, "clk_mac2phy_out_c", "clk_mac2phy", 0, 26, 8, 2),
[all …]
H A Drk3399_pmucru.c786 CDIV(PCLK_PMU_SRC, "pclk_pmu_src", "ppll", 0, 0, 0, 5),
799 CDIV(0, "clk_i2c0_div", "ppll", 0, 2, 0, 7),
801 CDIV(0, "clk_i2c8_div", "ppll", 0, 2, 8, 7),
805 CDIV(0, "clk_i2c4_div", "ppll", 0, 3, 0, 7),
H A Drk_cru.h158 #define CDIV(_id, _name, _pname, _f, _o, _ds, _dw) \ macro