Lines Matching refs:CDIV
590 CDIV(0, "aclk_core_mp_s", "armclk", 0,
592 CDIV(0, "aclk_core_m0_s", "armclk", 0,
596 CDIV(0, "pclk_cpu_s", "aclk_cpu_pre", 0,
598 CDIV(0, "hclk_cpu_s", "aclk_cpu_pre", RK_CLK_COMPOSITE_DIV_EXP,
602 CDIV(0, "aclk_cpu_pre", "aclk_cpu_src", 0,
607 CDIV(0, "sclk_tsadc_s", "xin32k", 0,
613 CDIV(0, "uart4_src_s", "uart_src", 0,
629 CDIV(0, "spdif_pre_s", "spdif_src", 0,
651 CDIV(0, "pclk_peri_s", "aclk_peri_src", RK_CLK_COMPOSITE_DIV_EXP,
653 CDIV(0, "hclk_peri_s", "aclk_peri_src", RK_CLK_COMPOSITE_DIV_EXP,
681 CDIV(0, "uart1_src_s", "uart_src", 0,
688 CDIV(0, "uart2_src_s", "uart_src", 0,
694 CDIV(0, "uart3_src_s", "uart_src", 0,
733 CDIV(0, "sclk_saradc_s", "xin24m", 0,
747 CDIV(0, "crypto_s", "aclk_cpu_pre", 0,
758 CDIV(0, "hclk_vio", "aclk_vio0", 0,
788 CDIV(0, "pclk_pd_alive", "gpll", 0,
790 CDIV(0, "pclk_pd_pmu_s", "gpll", 0,
806 CDIV(0, "armcore3_s", "armclk", 0,
808 CDIV(0, "armcore2_s", "armclk", 0,
810 CDIV(0, "armcore1_s", "armclk", 0,
812 CDIV(0, "armcore0_s", "armclk", 0,
816 CDIV(0, "pclk_dbg_pre_s", "armclk", 0,
818 CDIV(0, "atclk_s", "armclk", 0,
820 CDIV(0, "l2ram_s", "armclk", 0,
836 CDIV(HCLK_HEVC, "hclk_hevc", "aclk_hevc", 0,
840 CDIV(0, "spdif_8ch_pre_s", "spdif_src", 0,