Lines Matching refs:CDIV
329 CDIV(0, "atclk_core_div", "armclk", 0, 3, 0, 5),
331 CDIV(0, "gicclk_core_div", "armclk", 0, 3, 8, 5),
335 CDIV(0, "pclk_core_pre_div", "armclk", 0, 4, 0, 5),
337 CDIV(0, "periphclk_core_pre_div", "armclk", 0, 4, 8, 5),
349 CDIV(0, "aclk_gpu_pre_div", "clk_gpu_pre_c", 0, 6, 8, 2),
352 CDIV(0, "pclk_gpu_pre_div", "clk_gpu_pre_c", 0, 6, 12, 4),
363 CDIV(0, "hclk_npu_pre_div", "clk_npu", 0, 8, 0, 4),
364 CDIV(0, "pclk_npu_pre_div", "clk_npu", 0, 8, 4, 4),
375 CDIV(0, "clk_msch_div", "clk_ddr1x", 0, 10, 0, 2),
489 CDIV(0, "pclk_pipe_div", "aclk_pipe", 0, 29, 4, 4),
499 CDIV(0, "pclk_php_div", "aclk_php", 0, 30, 4, 4),
525 CDIV(0, "pclk_usb_div", "aclk_usb", 0, 32, 4, 4),
550 CDIV(0, "hclk_vi_div", "aclk_vi", 0, 34, 4, 4),
551 CDIV(0, "pclk_vi_div", "aclk_vi", 0, 34, 8, 4),
567 CDIV(0, "hclk_vo_div", "aclk_vo", 0, 37, 8, 4),
568 CDIV(0, "pclk_vo_div", "aclk_vo", 0, 37, 12, 4),
591 CDIV(0, "hclk_vpu_pre_div", "aclk_vpu_pre", 0, 42, 8, 4),
599 CDIV(0, "hclk_rga_pre_div", "aclk_rga_pre", 0, 43, 8, 4),
600 CDIV(0, "pclk_rga_pre_div", "aclk_rga_pre", 0, 43, 12, 4),
605 CDIV(0, "hclk_rkvenc_pre_div", "aclk_rkvenc_pre", 0, 44, 8, 4),
617 CDIV(0, "hclk_rkvdec_pre_div", "aclk_rkvdec_pre", 0, 47, 8, 4),
640 CDIV(0, "clk_tsadc_div", "clk_tsadc_tsen", 0, 51, 8, 7),
763 CDIV(0, "clk_gpll_div_400m_div", "gpll", 0, 75, 0, 5),
764 CDIV(0, "clk_gpll_div_300m_div", "gpll", 0, 75, 8, 5),
767 CDIV(0, "clk_gpll_div_200m_div", "gpll", 0, 76, 0, 5),
768 CDIV(0, "clk_gpll_div_150m_div", "gpll", 0, 76, 8, 5),
771 CDIV(0, "clk_gpll_div_100m_div", "gpll", 0, 77, 0, 5),
772 CDIV(0, "clk_gpll_div_75m_div", "gpll", 0, 77, 8, 5),
775 CDIV(0, "clk_gpll_div_20m_div", "gpll", 0, 78, 0, 6),
776 CDIV(0, "clk_cpll_div_500m_div", "cpll", 0, 78, 8, 5),
779 CDIV(0, "clk_cpll_div_333m_div", "cpll", 0, 79, 0, 6),
780 CDIV(0, "clk_cpll_div_250m_div", "cpll", 0, 79, 8, 5),
783 CDIV(0, "clk_cpll_div_125m_div", "cpll", 0, 80, 0, 6),
784 CDIV(0, "clk_cpll_div_62P5m_div", "cpll", 0, 80, 8, 5),
787 CDIV(0, "clk_cpll_div_50m_div", "cpll", 0, 81, 0, 6),
788 CDIV(0, "clk_cpll_div_25m_div", "cpll", 0, 81, 8, 5),
791 CDIV(0, "clk_cpll_div_100m_div", "cpll", 0, 82, 0, 6),
792 CDIV(0, "clk_osc0_div_750k_div", "xin24m", 0, 82, 8, 5),
795 CDIV(0, "clk_i2s3_2ch_rx_src_div", "clk_i2s3_2ch_rx_src_sel", 0, 83, 0, 7),