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Searched refs:CCR (Results 1 – 25 of 46) sorted by relevance

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/freebsd/contrib/llvm-project/llvm/lib/Target/M68k/
H A DM68kInstrControl.td95 let Uses = [CCR] in {
98 [(set i8:$dst, (MxSetCC !cast<PatLeaf>("MxCOND"#CC), CCR))]> {
106 [(store (MxSetCC !cast<PatLeaf>("MxCOND"#CC), CCR), MEMPat:$dst)]> {
163 let isBranch = 1, isTerminator = 1, Uses = [CCR] in
197 def : Pat<(MxBrCond bb:$target, !cast<PatLeaf>("MxCOND"#cc), CCR),
344 let Uses = [CCR], Defs = [CCR], isPseudo = 1 in {
349 [(set MxDRD8:$dst, (MxSetCC_C MxCONDcs, CCR))]>;
351 [(set MxDRD16:$dst, (MxSetCC_C MxCONDcs, CCR))]>;
353 [(set MxXRD32:$dst, (MxSetCC_C MxCONDcs, CCR))]>;
[all...]
H A DM68kInstrBits.td60 let Defs = [CCR] in {
86 } // Defs = [CCR]
H A DM68kInstrArithmetic.td56 let Defs = [CCR] in {
72 [(set DST_TYPE.VT:$dst, CCR, (NODE DST_TYPE.VT:$src, SRC_TYPE.VT:$opd))]> {
92 [(set TYPE.VT:$dst, CCR, (NODE TYPE.VT:$src, TYPE.VT:$opd))]> {
106 [(set TYPE.VT:$dst, CCR, (NODE TYPE.VT:$src, (TYPE.Load PAT:$opd)))]> {
133 [(set TYPE.VT:$dst, CCR, (NODE TYPE.VT:$src, TYPE.IPat:$opd))]> {
148 [(set TYPE.VT:$dst, CCR, (NODE TYPE.VT:$src, TYPE.IPat:$opd))]> {
164 // FIXME MxBiArOp_FMR/FMI cannot consume CCR from MxAdd/MxSub which leads for
193 } // Defs = [CCR]
281 // operations do not produce CCR we should not match them against Mx nodes that
304 // NOTE These naturally produce CCR
[all …]
H A DM68kInstrCompiler.td57 let usesCustomInserter = 1, Uses = [CCR] in
61 (TYPE.VT (MxCmov TYPE.VT:$t, TYPE.VT:$f, imm:$cond, CCR)))]>;
76 // sub / add which can clobber CCR.
77 let Defs = [SP, CCR], Uses = [SP] in {
123 let Defs = [SP, CCR], Uses = [SP] in
H A DM68kISelLowering.cpp1551 SDValue &Result, SDValue &CCR, in lowerOverflowArithmetic() argument
1622 CCR = DAG.getConstant(0, DL, N->getValueType(1)); in lowerOverflowArithmetic()
1624 CCR = Arith.getValue(1); in lowerOverflowArithmetic()
1633 SDValue Result, CCR; in LowerXALUO() local
1635 lowerOverflowArithmetic(Op, DAG, Result, CCR, CC); in LowerXALUO()
1638 if (isa<ConstantSDNode>(CCR)) { in LowerXALUO()
1641 Overflow = CCR; in LowerXALUO()
1645 DAG.getConstant(CC, DL, MVT::i8), CCR); in LowerXALUO()
2203 SDValue CCR = EmitCmp(Op0, Op1, M68kCC, DL, DAG); in LowerSETCC() local
2205 DAG.getConstant(M68kCC, DL, MVT::i8), CCR); in LowerSETCC()
[all …]
H A DM68kInstrData.td105 let Defs = [CCR] in
257 let Defs = [CCR] in
359 // MOVE to/from SR/CCR
361 // A special care must be taken working with to/from CCR since it is basically
363 // instructions. Plus the original M68000 does not support moves from CCR. So in
364 // order to use CCR effectively one MUST use proper byte-size pseudo instructi-
374 let Defs = [CCR] in
397 /// Move from CCR
404 let Uses = [CCR] in {
422 } // let Uses = [CCR]
[all …]
H A DM68kInstrInfo.td37 /* CCR */ SDTCisVT<1, i8>,
41 // RES, CCR <- op LHS, RHS
44 /* CCR */ SDTCisVT<1, i8>,
49 // RES, CCR <- op LHS, RHS, CCR
52 /* CCR */ SDTCisVT<1, i8>,
55 /* CCR */ SDTCisSameAs<1, 4>
59 /* CCR */ SDTCisVT<0, i8>,
67 /* CCR */ SDTCisVT<4, i8>
73 /* CCR */ SDTCisVT<2, i8>
79 /* CCR */ SDTCisVT<2, i8>
[all …]
H A DM68kInstrShiftRotate.td77 let Defs = [CCR] in {
89 } // Defs = [CCR]
H A DM68kRegisterInfo.td89 def CCR : MxPseudoReg<"ccr">;
125 def CCRC : MxRegClass<[i8], 16, (add CCR)>;
H A DM68kInstrInfo.cpp705 bool FromCCR = SrcReg == M68k::CCR; in copyPhysReg()
707 bool ToCCR = DstReg == M68k::CCR; in copyPhysReg()
/freebsd/contrib/llvm-project/clang/lib/AST/
H A DComparisonCategories.cpp205 using CCR = ComparisonCategoryResult; in getPossibleResultsForType() typedef
206 std::vector<CCR> Values; in getPossibleResultsForType()
209 Values.push_back(IsStrong ? CCR::Equal : CCR::Equivalent); in getPossibleResultsForType()
210 Values.push_back(CCR::Less); in getPossibleResultsForType()
211 Values.push_back(CCR::Greater); in getPossibleResultsForType()
213 Values.push_back(CCR::Unordered); in getPossibleResultsForType()
/freebsd/contrib/llvm-project/clang/include/clang/AST/
H A DComparisonCategories.h153 using CCR = ComparisonCategoryResult; in makeWeakResult() local
154 if (!isStrong() && Res == CCR::Equal) in makeWeakResult()
155 return CCR::Equivalent; in makeWeakResult()
/freebsd/contrib/llvm-project/llvm/lib/Target/AArch64/
H A DAArch64RegisterBanks.td19 def CCRegBank : RegisterBank<"CC", [CCR]>;
H A DAArch64GenRegisterBankInfo.def222 PMI_None, // CCR
/freebsd/sys/dev/xdma/controller/
H A Dpl330.h49 #define CCR(n) (0x408 + 0x20 * (n)) /* Channel control for DMA channel n */ macro
/freebsd/sys/dev/cardbus/
H A Dcard_if.m133 # Read the CCR register
143 # Write the CCR register
/freebsd/sys/kern/
H A Dtty_ttydisc.c68 #define CCR '\r' macro
74 (c) == CNL || (c) == CCR))
508 case CCR: in ttydisc_write_oproc()
1163 case CCR: in ttydisc_rint()
1171 c = CCR; in ttydisc_rint()
/freebsd/contrib/llvm-project/llvm/lib/Target/Lanai/
H A DLanaiRegisterInfo.td60 def CCR : RegisterClass<"Lanai", [i32], 32, (add SR)> {
/freebsd/contrib/llvm-project/llvm/lib/Target/M68k/AsmParser/
H A DM68kAsmParser.cpp260 case M68k::CCR: in getRegisterIndex()
522 case M68k::CCR: in checkRegisterClass()
641 RegNo = M68k::CCR; in parseRegisterName()
/freebsd/contrib/llvm-project/llvm/lib/Target/Hexagon/
H A DHexagonRegisterInfo.td296 def CCR : Rs<7, "ccr", ["s7"]>, DwarfRegNum<[151]>;
377 def S7_6 : Rss<6, "s7:6", [SSR, CCR], ["ccr:ssr"]>, DwarfRegNum<[150]>;
599 SSR, CCR, HTID, BADVA, IMASK,
/freebsd/contrib/llvm-project/llvm/lib/Target/Mips/
H A DMipsRegisterInfo.td423 def CCR : RegisterClass<"Mips", [i32], 32, (sequence "FCR%u", 0, 31)>,
656 def CCROpnd : RegisterOperand<CCR> {
/freebsd/contrib/llvm-project/llvm/lib/Target/AVR/
H A DAVRRegisterInfo.td222 def CCR : RegisterClass<"AVR", [i8], 8, (add SREG)> {
/freebsd/contrib/llvm-project/llvm/lib/Target/ARM/
H A DARMISelLowering.cpp5004 SDValue CCR = DAG.getRegister(ARM::CPSR, MVT::i32); in LowerSignedALUO() local
5012 ARMcc, CCR, OverflowCmp); in LowerSignedALUO()
5149 SDValue CCR = DAG.getRegister(ARM::CPSR, MVT::i32); in LowerSELECT() local
5152 return getCMOV(dl, VT, SelectTrue, SelectFalse, ARMcc, CCR, in LowerSELECT()
5184 SDValue CCR = Cond.getOperand(3); in LowerSELECT() local
5187 return getCMOV(dl, VT, True, False, ARMcc, CCR, Cmp, DAG); in LowerSELECT()
5253 SDValue TrueVal, SDValue ARMcc, SDValue CCR, in getCMOV() argument
5267 ARMcc, CCR, Cmp); in getCMOV()
5269 ARMcc, CCR, duplicateCmp(Cmp, DAG)); in getCMOV()
5273 return DAG.getNode(ARMISD::CMOV, dl, VT, FalseVal, TrueVal, ARMcc, CCR, in getCMOV()
[all …]
/freebsd/contrib/llvm-project/llvm/lib/Target/X86/
H A DX86RegisterInfo.td777 def CCR : RegisterClass<"X86", [i32], 32, (add EFLAGS)> {
845 def FixedRegisters : RegisterCategory<[DEBUG_REG, CONTROL_REG, CCR, FPCCR,
/freebsd/contrib/llvm-project/llvm/lib/Target/SystemZ/
H A DSystemZRegisterInfo.td323 def CCR : RegisterClass<"SystemZ", [i32], 32, (add CC)>;

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