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Searched refs:BaseOp (Results 1 – 25 of 30) sorted by relevance

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/freebsd/contrib/llvm-project/llvm/lib/Target/AArch64/
H A DAArch64StorePairSuppress.cpp160 const MachineOperand *BaseOp; in runOnMachineFunction() local
163 if (TII->getMemOperandWithOffset(MI, BaseOp, Offset, OffsetIsScalable, in runOnMachineFunction()
165 BaseOp->isReg()) { in runOnMachineFunction()
166 Register BaseReg = BaseOp->getReg(); in runOnMachineFunction()
H A DAArch64InstrInfo.h312 const MachineOperand *&BaseOp,
H A DAArch64InstrInfo.cpp2986 const MachineOperand *BaseOp; in getMemOperandsWithOffsetWidth() local
2988 if (!getMemOperandWithOffsetWidth(LdSt, BaseOp, Offset, OffsetIsScalable, in getMemOperandsWithOffsetWidth()
2994 BaseOps.push_back(BaseOp); in getMemOperandsWithOffsetWidth()
3996 const MachineInstr &LdSt, const MachineOperand *&BaseOp, int64_t &Offset, in getMemOperandWithOffsetWidth() argument
4028 BaseOp = &LdSt.getOperand(2); in getMemOperandWithOffsetWidth()
4031 BaseOp = &LdSt.getOperand(1); in getMemOperandWithOffsetWidth()
4035 BaseOp = &LdSt.getOperand(2); in getMemOperandWithOffsetWidth()
4040 return BaseOp->isReg() || BaseOp->isFI(); in getMemOperandWithOffsetWidth()
/freebsd/contrib/llvm-project/llvm/lib/Target/Hexagon/
H A DHexagonGenMemAbsolute.cpp121 const MachineOperand *BaseOp = nullptr; in runOnMachineFunction() local
124 TII->getMemOperandWithOffset(*NextMI, BaseOp, Offset, Scalable, TRI); in runOnMachineFunction()
127 if (!BaseOp || !BaseOp->isReg()) in runOnMachineFunction()
133 unsigned BaseReg = BaseOp->getReg(); in runOnMachineFunction()
H A DHexagonInstrInfo.cpp1176 const MachineOperand &BaseOp = MI.getOperand(1); in expandPostRAPseudo() local
1177 assert(BaseOp.getSubReg() == 0); in expandPostRAPseudo()
1183 .addReg(BaseOp.getReg(), getRegState(BaseOp)) in expandPostRAPseudo()
1191 const MachineOperand &BaseOp = MI.getOperand(1); in expandPostRAPseudo() local
1192 assert(BaseOp.getSubReg() == 0); in expandPostRAPseudo()
1200 .addReg(BaseOp.getReg(), getRegState(BaseOp) & ~RegState::Kill) in expandPostRAPseudo()
1205 .addReg(BaseOp.getReg(), getRegState(BaseOp)) in expandPostRAPseudo()
1214 const MachineOperand &BaseOp = MI.getOperand(0); in expandPostRAPseudo() local
1215 assert(BaseOp.getSubReg() == 0); in expandPostRAPseudo()
1221 .addReg(BaseOp.getReg(), getRegState(BaseOp)) in expandPostRAPseudo()
[all …]
H A DHexagonOptAddrMode.cpp714 MachineOperand BaseOp = MI->getOperand(getBaseOpPosition(MI)); in processAddUses() local
716 if (!BaseOp.isReg() || BaseOp.getReg() != AddDefR) in processAddUses()
780 MachineOperand &BaseOp = UseMI->getOperand(getBaseOpPosition(UseMI)); in updateAddUses() local
782 BaseOp.setReg(NewReg); in updateAddUses()
783 BaseOp.setIsUndef(AddRegOp.isUndef()); in updateAddUses()
784 BaseOp.setImplicit(AddRegOp.isImplicit()); in updateAddUses()
/freebsd/contrib/llvm-project/llvm/lib/Target/ARM/
H A DARMHazardRecognizer.cpp107 static bool getBaseOffset(const MachineInstr &MI, const MachineOperand *&BaseOp, in getBaseOffset() argument
127 BaseOp = &MI.getOperand(1); in getBaseOffset()
139 BaseOp = &MI.getOperand(1); in getBaseOffset()
144 BaseOp = &MI.getOperand(2); in getBaseOffset()
158 BaseOp = &MI.getOperand(1); in getBaseOffset()
H A DARMLoadStoreOptimizer.cpp1621 const MachineOperand &BaseOp = MI.getOperand(2); in MergeBaseUpdateLSDouble() local
1622 Register Base = BaseOp.getReg(); in MergeBaseUpdateLSDouble()
1652 MIB.add(Reg0Op).add(Reg1Op).addReg(BaseOp.getReg(), RegState::Define); in MergeBaseUpdateLSDouble()
1655 MIB.addReg(BaseOp.getReg(), RegState::Define).add(Reg0Op).add(Reg1Op); in MergeBaseUpdateLSDouble()
1657 MIB.addReg(BaseOp.getReg(), RegState::Kill) in MergeBaseUpdateLSDouble()
1767 const MachineOperand &BaseOp = MI->getOperand(2); in FixInvalidRegPairOp() local
1768 Register BaseReg = BaseOp.getReg(); in FixInvalidRegPairOp()
1793 bool BaseKill = BaseOp.isKill(); in FixInvalidRegPairOp()
1794 bool BaseUndef = BaseOp.isUndef(); in FixInvalidRegPairOp()
3011 unsigned BaseOp = getBaseOperandIndex(*MI); in AdjustBaseAndOffset() local
[all …]
/freebsd/contrib/llvm-project/llvm/lib/Target/Lanai/
H A DLanaiInstrInfo.cpp756 const MachineInstr &LdSt, const MachineOperand *&BaseOp, int64_t &Offset, in getMemOperandWithOffsetWidth() argument
787 BaseOp = &LdSt.getOperand(1); in getMemOperandWithOffsetWidth()
790 if (!BaseOp->isReg()) in getMemOperandWithOffsetWidth()
812 const MachineOperand *BaseOp; in getMemOperandsWithOffsetWidth() local
814 if (!getMemOperandWithOffsetWidth(LdSt, BaseOp, Offset, Width, TRI)) in getMemOperandsWithOffsetWidth()
816 BaseOps.push_back(BaseOp); in getMemOperandsWithOffsetWidth()
H A DLanaiInstrInfo.h79 const MachineOperand *&BaseOp,
/freebsd/contrib/llvm-project/llvm/lib/Target/BPF/
H A DBPFMISimplifyPatchable.cpp135 const MachineOperand *BaseOp = (RelocOp == Op1) ? Op2 : Op1; in checkADDrr() local
172 .add(DefInst->getOperand(0)).addImm(Opcode).add(*BaseOp) in checkADDrr()
/freebsd/contrib/llvm-project/llvm/lib/Target/AMDGPU/
H A DEvergreenInstructions.td644 field string BaseOp;
653 let BaseOp = name;
659 let BaseOp = name;
675 field string BaseOp;
683 let BaseOp = name;
689 let BaseOp = name;
H A DSIInstrInfo.cpp371 const MachineOperand *BaseOp, *OffsetOp; in getMemOperandsWithOffsetWidth() local
375 BaseOp = getNamedOperand(LdSt, AMDGPU::OpName::addr); in getMemOperandsWithOffsetWidth()
379 if (!BaseOp) { in getMemOperandsWithOffsetWidth()
384 BaseOps.push_back(BaseOp); in getMemOperandsWithOffsetWidth()
423 BaseOps.push_back(BaseOp); in getMemOperandsWithOffsetWidth()
445 BaseOp = getNamedOperand(LdSt, AMDGPU::OpName::vaddr); in getMemOperandsWithOffsetWidth()
446 if (BaseOp && !BaseOp->isFI()) in getMemOperandsWithOffsetWidth()
447 BaseOps.push_back(BaseOp); in getMemOperandsWithOffsetWidth()
492 BaseOp = getNamedOperand(LdSt, AMDGPU::OpName::sbase); in getMemOperandsWithOffsetWidth()
493 if (!BaseOp) // e.g. S_MEMTIME in getMemOperandsWithOffsetWidth()
[all …]
/freebsd/contrib/llvm-project/llvm/lib/CodeGen/
H A DTargetInstrInfo.cpp1736 const MachineInstr &MI, const MachineOperand *&BaseOp, int64_t &Offset, in getMemOperandWithOffset() argument
1744 BaseOp = BaseOps.front(); in getMemOperandWithOffset()
1903 const MachineOperand *BaseOp; in describeLoadedValue() local
1904 if (!TII->getMemOperandWithOffset(MI, BaseOp, Offset, OffsetIsScalable, in describeLoadedValue()
1929 return ParamLoadedValue(*BaseOp, Expr); in describeLoadedValue()
H A DMachineSink.cpp1530 const MachineOperand *BaseOp; in SinkingPreventsImplicitNullCheck() local
1533 if (!TII->getMemOperandWithOffset(MI, BaseOp, Offset, OffsetIsScalable, TRI)) in SinkingPreventsImplicitNullCheck()
1536 if (!BaseOp->isReg()) in SinkingPreventsImplicitNullCheck()
1549 MBP.LHS.getReg() == BaseOp->getReg(); in SinkingPreventsImplicitNullCheck()
H A DMachinePipeliner.cpp2851 const MachineOperand *BaseOp; in findLoopIncrementValue() local
2854 if (TII->getMemOperandWithOffset(*Def, BaseOp, Offset, OffsetIsScalable, in findLoopIncrementValue()
2857 CurReg = BaseOp->getReg(); in findLoopIncrementValue()
2883 const MachineOperand *BaseOp; in computeDelta() local
2886 if (!TII->getMemOperandWithOffset(MI, BaseOp, Offset, OffsetIsScalable, TRI)) in computeDelta()
2893 if (!BaseOp->isReg()) in computeDelta()
2896 return findLoopIncrementValue(*BaseOp, Delta); in computeDelta()
H A DModuloSchedule.cpp947 const MachineOperand *BaseOp; in computeDelta() local
950 if (!TII->getMemOperandWithOffset(MI, BaseOp, Offset, OffsetIsScalable, TRI)) in computeDelta()
957 if (!BaseOp->isReg()) in computeDelta()
960 Register BaseReg = BaseOp->getReg(); in computeDelta()
/freebsd/contrib/llvm-project/llvm/lib/Target/RISCV/
H A DRISCVInstrInfo.h186 const MachineOperand *&BaseOp,
H A DRISCVInstrInfo.cpp3191 const MachineOperand *BaseOp; in getMemOperandsWithOffsetWidth() local
3193 if (!getMemOperandWithOffsetWidth(LdSt, BaseOp, Offset, Width, TRI)) in getMemOperandsWithOffsetWidth()
3195 BaseOps.push_back(BaseOp); in getMemOperandsWithOffsetWidth()
/freebsd/contrib/llvm-project/llvm/lib/Target/M68k/
H A DM68kISelLowering.cpp1576 unsigned BaseOp = 0; in lowerOverflowArithmetic() local
1581 BaseOp = M68kISD::ADD; in lowerOverflowArithmetic()
1585 BaseOp = M68kISD::ADD; in lowerOverflowArithmetic()
1589 BaseOp = M68kISD::SUB; in lowerOverflowArithmetic()
1593 BaseOp = M68kISD::SUB; in lowerOverflowArithmetic()
1599 BaseOp = NoOverflow ? (unsigned)ISD::MUL : (unsigned)M68kISD::UMUL; in lowerOverflowArithmetic()
1605 BaseOp = NoOverflow ? (unsigned)ISD::MUL : (unsigned)M68kISD::SMUL; in lowerOverflowArithmetic()
1617 SDValue Arith = DAG.getNode(BaseOp, DL, VTs, LHS, RHS); in lowerOverflowArithmetic()
/freebsd/contrib/llvm-project/llvm/lib/Target/SystemZ/
H A DSystemZISelLowering.cpp4749 unsigned BaseOp = 0; in lowerXALUO() local
4755 BaseOp = ISD::ADD; in lowerXALUO()
4759 BaseOp = ISD::SUB; in lowerXALUO()
4764 SDValue Result = DAG.getNode(BaseOp, DL, MVT::i128, LHS, RHS); in lowerXALUO()
4775 unsigned BaseOp = 0; in lowerXALUO() local
4782 BaseOp = SystemZISD::SADDO; in lowerXALUO()
4787 BaseOp = SystemZISD::SSUBO; in lowerXALUO()
4792 BaseOp = SystemZISD::UADDO; in lowerXALUO()
4797 BaseOp = SystemZISD::USUBO; in lowerXALUO()
4804 SDValue Result = DAG.getNode(BaseOp, DL, VTs, LHS, RHS); in lowerXALUO()
[all …]
/freebsd/contrib/llvm-project/llvm/lib/Target/PowerPC/
H A DPPCInstrInfo.h669 const MachineOperand *&BaseOp,
/freebsd/contrib/llvm-project/llvm/include/llvm/Target/
H A DTarget.td1871 // let RowFields = BaseOp
1872 // All add instruction predicated/non-predicated will have to set their BaseOp
1875 // def Add: { let BaseOp = 'ADD'; let predSense = 'nopred' }
1876 // def Add_predtrue: { let BaseOp = 'ADD'; let predSense = 'true' }
1877 // def Add_predfalse: { let BaseOp = 'ADD'; let predSense = 'false' }
/freebsd/contrib/llvm-project/llvm/include/llvm/CodeGen/
H A DTargetInstrInfo.h1536 const MachineOperand *&BaseOp, int64_t &Offset,
/freebsd/contrib/llvm-project/llvm/lib/Target/X86/
H A DX86InstrInfo.cpp4563 auto &BaseOp = MemI.getOperand(MemRefBegin + X86::AddrBaseReg); in getAddrModeFromMemoryOp() local
4564 if (!BaseOp.isReg()) // Can be an MO_FrameIndex in getAddrModeFromMemoryOp()
4573 AM.BaseReg = BaseOp.getReg(); in getAddrModeFromMemoryOp()
4690 const MachineOperand *BaseOp = in getMemOperandsWithOffsetWidth() local
4692 if (!BaseOp->isReg()) // Can be an MO_FrameIndex in getMemOperandsWithOffsetWidth()
4710 if (!BaseOp->isReg()) in getMemOperandsWithOffsetWidth()
4719 BaseOps.push_back(BaseOp); in getMemOperandsWithOffsetWidth()

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