| /freebsd/contrib/llvm-project/llvm/lib/Target/AArch64/ |
| H A D | AArch64StorePairSuppress.cpp | 162 const MachineOperand *BaseOp; in runOnMachineFunction() local
165 if (TII->getMemOperandWithOffset(MI, BaseOp, Offset, OffsetIsScalable, in runOnMachineFunction()
167 BaseOp->isReg()) { in runOnMachineFunction()
168 Register BaseReg = BaseOp->getReg(); in runOnMachineFunction()
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| H A D | AArch64InstrInfo.h | 309 const MachineOperand *&BaseOp,
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| H A D | AArch64InstrInfo.cpp | 2706 const MachineOperand *BaseOp; in getMemOperandsWithOffsetWidth() local
2708 if (!getMemOperandWithOffsetWidth(LdSt, BaseOp, Offset, OffsetIsScalable, in getMemOperandsWithOffsetWidth()
2714 BaseOps.push_back(BaseOp); in getMemOperandsWithOffsetWidth()
3491 const MachineInstr &LdSt, const MachineOperand *&BaseOp, int64_t &Offset, in getMemOperandWithOffsetWidth() argument
3523 BaseOp = &LdSt.getOperand(1); in getMemOperandWithOffsetWidth()
3527 BaseOp = &LdSt.getOperand(2); in getMemOperandWithOffsetWidth()
3532 if (!BaseOp->isReg() && !BaseOp->isFI()) in getMemOperandWithOffsetWidth()
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| /freebsd/contrib/llvm-project/llvm/lib/Target/Hexagon/ |
| H A D | HexagonGenMemAbsolute.cpp | 131 const MachineOperand *BaseOp = nullptr; in runOnMachineFunction() local
134 TII->getMemOperandWithOffset(*NextMI, BaseOp, Offset, Scalable, TRI); in runOnMachineFunction()
137 if (!BaseOp || !BaseOp->isReg()) in runOnMachineFunction()
143 unsigned BaseReg = BaseOp->getReg(); in runOnMachineFunction()
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| H A D | HexagonOptAddrMode.cpp | 432 MachineOperand BaseOp = MI->getOperand(getBaseOpPosition(MI)); in processAddUses() local
434 if (!BaseOp.isReg() || BaseOp.getReg() != AddDefR) in processAddUses()
498 MachineOperand &BaseOp = UseMI->getOperand(getBaseOpPosition(UseMI)); in updateAddUses() local
500 BaseOp.setReg(NewReg); in updateAddUses()
501 BaseOp.setIsUndef(AddRegOp.isUndef()); in updateAddUses()
502 BaseOp.setImplicit(AddRegOp.isImplicit()); in updateAddUses()
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| H A D | HexagonInstrInfo.cpp | 1173 const MachineOperand &BaseOp = MI.getOperand(1); in expandPostRAPseudo() local
1174 assert(BaseOp.getSubReg() == 0); in expandPostRAPseudo()
1180 .addReg(BaseOp.getReg(), getRegState(BaseOp)) in expandPostRAPseudo()
1188 const MachineOperand &BaseOp = MI.getOperand(1); in expandPostRAPseudo() local
1189 assert(BaseOp.getSubReg() == 0); in expandPostRAPseudo()
1197 .addReg(BaseOp.getReg(), getRegState(BaseOp) & ~RegState::Kill) in expandPostRAPseudo()
1202 .addReg(BaseOp.getReg(), getRegState(BaseOp)) in expandPostRAPseudo()
1211 const MachineOperand &BaseOp = MI.getOperand(0); in expandPostRAPseudo() local
1212 assert(BaseOp.getSubReg() == 0); in expandPostRAPseudo()
1218 .addReg(BaseOp.getReg(), getRegState(BaseOp)) in expandPostRAPseudo()
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| /freebsd/contrib/llvm-project/llvm/lib/Target/ARM/ |
| H A D | ARMHazardRecognizer.cpp | 109 static bool getBaseOffset(const MachineInstr &MI, const MachineOperand *&BaseOp, in getBaseOffset() argument
129 BaseOp = &MI.getOperand(1); in getBaseOffset()
141 BaseOp = &MI.getOperand(1); in getBaseOffset()
146 BaseOp = &MI.getOperand(2); in getBaseOffset()
160 BaseOp = &MI.getOperand(1); in getBaseOffset()
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| H A D | ARMLoadStoreOptimizer.cpp | 1624 const MachineOperand &BaseOp = MI.getOperand(2); in MergeBaseUpdateLSDouble() local
1625 Register Base = BaseOp.getReg(); in MergeBaseUpdateLSDouble()
1655 MIB.add(Reg0Op).add(Reg1Op).addReg(BaseOp.getReg(), RegState::Define); in MergeBaseUpdateLSDouble()
1658 MIB.addReg(BaseOp.getReg(), RegState::Define).add(Reg0Op).add(Reg1Op); in MergeBaseUpdateLSDouble()
1660 MIB.addReg(BaseOp.getReg(), RegState::Kill) in MergeBaseUpdateLSDouble()
1770 const MachineOperand &BaseOp = MI->getOperand(2); in FixInvalidRegPairOp() local
1771 Register BaseReg = BaseOp.getReg(); in FixInvalidRegPairOp()
1796 bool BaseKill = BaseOp.isKill(); in FixInvalidRegPairOp()
1797 bool BaseUndef = BaseOp.isUndef(); in FixInvalidRegPairOp()
3019 unsigned BaseOp = getBaseOperandIndex(*MI); in AdjustBaseAndOffset() local
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| /freebsd/contrib/llvm-project/llvm/lib/Target/Lanai/ |
| H A D | LanaiInstrInfo.cpp | 755 const MachineInstr &LdSt, const MachineOperand *&BaseOp, int64_t &Offset, in getMemOperandWithOffsetWidth() argument
786 BaseOp = &LdSt.getOperand(1); in getMemOperandWithOffsetWidth()
789 if (!BaseOp->isReg()) in getMemOperandWithOffsetWidth()
811 const MachineOperand *BaseOp; in getMemOperandsWithOffsetWidth() local
813 if (!getMemOperandWithOffsetWidth(LdSt, BaseOp, Offset, Width, TRI)) in getMemOperandsWithOffsetWidth()
815 BaseOps.push_back(BaseOp); in getMemOperandsWithOffsetWidth()
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| H A D | LanaiInstrInfo.h | 77 const MachineOperand *&BaseOp,
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| /freebsd/contrib/llvm-project/llvm/lib/Target/BPF/ |
| H A D | BPFMISimplifyPatchable.cpp | 133 const MachineOperand *BaseOp = (RelocOp == Op1) ? Op2 : Op1; in checkADDrr() local
170 .add(DefInst->getOperand(0)).addImm(Opcode).add(*BaseOp) in checkADDrr()
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| /freebsd/contrib/llvm-project/llvm/lib/Target/AMDGPU/ |
| H A D | EvergreenInstructions.td | 644 field string BaseOp;
653 let BaseOp = name;
659 let BaseOp = name;
675 field string BaseOp;
683 let BaseOp = name;
689 let BaseOp = name;
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| H A D | SIInstrInfo.cpp | 365 const MachineOperand *BaseOp, *OffsetOp; in getMemOperandsWithOffsetWidth() local
369 BaseOp = getNamedOperand(LdSt, AMDGPU::OpName::addr); in getMemOperandsWithOffsetWidth()
373 if (!BaseOp) { in getMemOperandsWithOffsetWidth()
378 BaseOps.push_back(BaseOp); in getMemOperandsWithOffsetWidth()
414 BaseOps.push_back(BaseOp); in getMemOperandsWithOffsetWidth()
435 BaseOp = getNamedOperand(LdSt, AMDGPU::OpName::vaddr); in getMemOperandsWithOffsetWidth()
436 if (BaseOp && !BaseOp->isFI()) in getMemOperandsWithOffsetWidth()
437 BaseOps.push_back(BaseOp); in getMemOperandsWithOffsetWidth()
482 BaseOp = getNamedOperand(LdSt, AMDGPU::OpName::sbase); in getMemOperandsWithOffsetWidth()
483 if (!BaseOp) // e.g. S_MEMTIME in getMemOperandsWithOffsetWidth()
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| /freebsd/contrib/llvm-project/llvm/lib/CodeGen/ |
| H A D | TargetInstrInfo.cpp | 1425 const MachineInstr &MI, const MachineOperand *&BaseOp, int64_t &Offset, in getMemOperandWithOffset() argument
1433 BaseOp = BaseOps.front(); in getMemOperandWithOffset()
1593 const MachineOperand *BaseOp; in describeLoadedValue() local
1594 if (!TII->getMemOperandWithOffset(MI, BaseOp, Offset, OffsetIsScalable, in describeLoadedValue()
1619 return ParamLoadedValue(*BaseOp, Expr); in describeLoadedValue()
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| H A D | MachineSink.cpp | 1359 const MachineOperand *BaseOp; in SinkingPreventsImplicitNullCheck() local
1362 if (!TII->getMemOperandWithOffset(MI, BaseOp, Offset, OffsetIsScalable, TRI)) in SinkingPreventsImplicitNullCheck()
1365 if (!BaseOp->isReg()) in SinkingPreventsImplicitNullCheck()
1378 MBP.LHS.getReg() == BaseOp->getReg(); in SinkingPreventsImplicitNullCheck()
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| H A D | ModuloSchedule.cpp | 929 const MachineOperand *BaseOp; in computeDelta() local
932 if (!TII->getMemOperandWithOffset(MI, BaseOp, Offset, OffsetIsScalable, TRI)) in computeDelta()
939 if (!BaseOp->isReg()) in computeDelta()
942 Register BaseReg = BaseOp->getReg(); in computeDelta()
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| H A D | MachinePipeliner.cpp | 2570 const MachineOperand *BaseOp; in computeDelta() local
2573 if (!TII->getMemOperandWithOffset(MI, BaseOp, Offset, OffsetIsScalable, TRI)) in computeDelta()
2580 if (!BaseOp->isReg()) in computeDelta()
2583 Register BaseReg = BaseOp->getReg(); in computeDelta()
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| /freebsd/contrib/llvm-project/llvm/lib/Target/RISCV/ |
| H A D | RISCVInstrInfo.h | 182 const MachineOperand *&BaseOp,
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| H A D | RISCVInstrInfo.cpp | 2647 const MachineOperand *BaseOp;
2649 if (!getMemOperandWithOffsetWidth(LdSt, BaseOp, Offset, Width, TRI))
2651 BaseOps.push_back(BaseOp); in memOpsHaveSameBasePtr()
2640 const MachineOperand *BaseOp; getMemOperandsWithOffsetWidth() local
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| /freebsd/contrib/llvm-project/llvm/lib/Target/M68k/ |
| H A D | M68kISelLowering.cpp | 1574 unsigned BaseOp = 0; in lowerOverflowArithmetic() local
1579 BaseOp = M68kISD::ADD; in lowerOverflowArithmetic()
1583 BaseOp = M68kISD::ADD; in lowerOverflowArithmetic()
1587 BaseOp = M68kISD::SUB; in lowerOverflowArithmetic()
1591 BaseOp = M68kISD::SUB; in lowerOverflowArithmetic()
1597 BaseOp = NoOverflow ? ISD::MUL : M68kISD::UMUL; in lowerOverflowArithmetic()
1603 BaseOp = NoOverflow ? ISD::MUL : M68kISD::SMUL; in lowerOverflowArithmetic()
1615 SDValue Arith = DAG.getNode(BaseOp, DL, VTs, LHS, RHS); in lowerOverflowArithmetic()
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| /freebsd/contrib/llvm-project/llvm/lib/Target/SystemZ/ |
| H A D | SystemZISelLowering.cpp | 4278 unsigned BaseOp = 0; in lowerXALUO() local
4284 BaseOp = ISD::ADD; in lowerXALUO()
4288 BaseOp = ISD::SUB; in lowerXALUO()
4293 SDValue Result = DAG.getNode(BaseOp, DL, MVT::i128, LHS, RHS); in lowerXALUO()
4304 unsigned BaseOp = 0; in lowerXALUO() local
4311 BaseOp = SystemZISD::SADDO; in lowerXALUO()
4316 BaseOp = SystemZISD::SSUBO; in lowerXALUO()
4321 BaseOp = SystemZISD::UADDO; in lowerXALUO()
4326 BaseOp = SystemZISD::USUBO; in lowerXALUO()
4333 SDValue Result = DAG.getNode(BaseOp, DL, VTs, LHS, RHS); in lowerXALUO()
[all …]
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| /freebsd/contrib/llvm-project/llvm/lib/Target/PowerPC/ |
| H A D | PPCInstrInfo.h | 559 const MachineOperand *&BaseOp,
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| /freebsd/contrib/llvm-project/llvm/include/llvm/Target/ |
| H A D | Target.td | 1849 // let RowFields = BaseOp
1850 // All add instruction predicated/non-predicated will have to set their BaseOp
1853 // def Add: { let BaseOp = 'ADD'; let predSense = 'nopred' }
1854 // def Add_predtrue: { let BaseOp = 'ADD'; let predSense = 'true' }
1855 // def Add_predfalse: { let BaseOp = 'ADD'; let predSense = 'false' }
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| /freebsd/contrib/llvm-project/llvm/include/llvm/CodeGen/ |
| H A D | TargetInstrInfo.h | 1470 const MachineOperand *&BaseOp, int64_t &Offset,
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| /freebsd/contrib/llvm-project/llvm/lib/Target/X86/ |
| H A D | X86InstrInfo.cpp | 4498 auto &BaseOp = MemI.getOperand(MemRefBegin + X86::AddrBaseReg); in getAddrModeFromMemoryOp() local
4499 if (!BaseOp.isReg()) // Can be an MO_FrameIndex in getAddrModeFromMemoryOp()
4508 AM.BaseReg = BaseOp.getReg(); in getAddrModeFromMemoryOp()
4625 const MachineOperand *BaseOp = in getMemOperandsWithOffsetWidth() local
4627 if (!BaseOp->isReg()) // Can be an MO_FrameIndex in getMemOperandsWithOffsetWidth()
4645 if (!BaseOp->isReg()) in getMemOperandsWithOffsetWidth()
4654 BaseOps.push_back(BaseOp); in getMemOperandsWithOffsetWidth()
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