1173       const MachineOperand &BaseOp = MI.getOperand(1);  in expandPostRAPseudo()  local
1174       assert(BaseOp.getSubReg() == 0);  in expandPostRAPseudo()
1180           .addReg(BaseOp.getReg(), getRegState(BaseOp))  in expandPostRAPseudo()
1188       const MachineOperand &BaseOp = MI.getOperand(1);  in expandPostRAPseudo()  local
1189       assert(BaseOp.getSubReg() == 0);  in expandPostRAPseudo()
1197           .addReg(BaseOp.getReg(), getRegState(BaseOp) & ~RegState::Kill)  in expandPostRAPseudo()
1202           .addReg(BaseOp.getReg(), getRegState(BaseOp))  in expandPostRAPseudo()
1211       const MachineOperand &BaseOp = MI.getOperand(0);  in expandPostRAPseudo()  local
1212       assert(BaseOp.getSubReg() == 0);  in expandPostRAPseudo()
1218           .addReg(BaseOp.getReg(), getRegState(BaseOp))  in expandPostRAPseudo()
1227       const MachineOperand &BaseOp = MI.getOperand(0);  in expandPostRAPseudo()  local
1228       assert(BaseOp.getSubReg() == 0);  in expandPostRAPseudo()
1235           .addReg(BaseOp.getReg(), getRegState(BaseOp) & ~RegState::Kill)  in expandPostRAPseudo()
1240           .addReg(BaseOp.getReg(), getRegState(BaseOp))  in expandPostRAPseudo()
3077   const MachineOperand *BaseOp = getBaseAndOffset(LdSt, Offset, Width);  in getMemOperandsWithOffsetWidth()  local
3078   if (!BaseOp || !BaseOp->isReg())  in getMemOperandsWithOffsetWidth()
3080   BaseOps.push_back(BaseOp);  in getMemOperandsWithOffsetWidth()
3316   const MachineOperand &BaseOp = MI.getOperand(BasePos);  in getBaseAndOffset()  local
3317   if (BaseOp.getSubReg() != 0)  in getBaseAndOffset()
3319   return &const_cast<MachineOperand&>(BaseOp);  in getBaseAndOffset()