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Searched refs:BITCAST (Results 1 – 25 of 57) sorted by relevance

123

/freebsd/contrib/llvm-project/llvm/lib/CodeGen/SelectionDAG/
H A DLegalizeTypesGeneric.cpp58 Lo = DAG.getNode(ISD::BITCAST, dl, NOutVT, Lo); in ExpandRes_BITCAST()
59 Hi = DAG.getNode(ISD::BITCAST, dl, NOutVT, Hi); in ExpandRes_BITCAST()
69 Lo = DAG.getNode(ISD::BITCAST, dl, NOutVT, Lo); in ExpandRes_BITCAST()
70 Hi = DAG.getNode(ISD::BITCAST, dl, NOutVT, Hi); in ExpandRes_BITCAST()
77 Lo = DAG.getNode(ISD::BITCAST, dl, NOutVT, Lo); in ExpandRes_BITCAST()
78 Hi = DAG.getNode(ISD::BITCAST, dl, NOutVT, Hi); in ExpandRes_BITCAST()
83 Lo = DAG.getNode(ISD::BITCAST, dl, NOutVT, Lo); in ExpandRes_BITCAST()
84 Hi = DAG.getNode(ISD::BITCAST, dl, NOutVT, Hi); in ExpandRes_BITCAST()
89 assert(!(InVT.getVectorNumElements() & 1) && "Unsupported BITCAST"); in ExpandRes_BITCAST()
96 Lo = DAG.getNode(ISD::BITCAST, d in ExpandRes_BITCAST()
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H A DLegalizeVectorOps.cpp726 Operands[j] = DAG.getNode(ISD::BITCAST, dl, NVT, Node->getOperand(j)); in Promote()
740 Res = DAG.getNode(ISD::BITCAST, dl, VT, Res); in Promote()
1188 Op1 = DAG.getNode(ISD::BITCAST, DL, MaskTy, Op1); in ExpandSELECT()
1189 Op2 = DAG.getNode(ISD::BITCAST, DL, MaskTy, Op2); in ExpandSELECT()
1196 return DAG.getNode(ISD::BITCAST, DL, Node->getValueType(0), Val); in ExpandSELECT()
1251 ISD::BITCAST, DL, VT, in ExpandANY_EXTEND_VECTOR_INREG()
1311 return DAG.getNode(ISD::BITCAST, DL, VT, in ExpandZERO_EXTEND_VECTOR_INREG()
1337 SDValue Op = DAG.getNode(ISD::BITCAST, DL, ByteVT, Node->getOperand(0)); in ExpandBSWAP()
1339 return DAG.getNode(ISD::BITCAST, DL, VT, Op); in ExpandBSWAP()
1387 SDValue Op = DAG.getNode(ISD::BITCAST, DL, ByteVT, Node->getOperand(0)); in ExpandBITREVERSE()
[all …]
H A DLegalizeDAG.cpp522 Value = DAG.getNode(ISD::BITCAST, dl, NVT, Value); in LegalizeStoreOps()
695 RVal = DAG.getNode(ISD::BITCAST, dl, VT, Res); in LegalizeLoadOps()
1575 State.IntValue = DAG.getNode(ISD::BITCAST, DL, IVT, Value); in getSignAsIntValue()
1622 return DAG.getNode(ISD::BITCAST, DL, State.FloatVT, NewIntValue); in modifySignAsInt()
2516 SDValue AsFP = DAG.getNode(ISD::BITCAST, dl, VT, AsInt); in expandLdexp()
2583 SDValue AsInt = DAG.getNode(ISD::BITCAST, dl, AsIntVT, Val); in expandFrexp()
2598 SDValue ScaledAsInt = DAG.getNode(ISD::BITCAST, dl, AsIntVT, ScaleUp); in expandFrexp()
2625 SDValue MaskedFract = DAG.getNode(ISD::BITCAST, dl, VT, Or); in expandFrexp()
3279 case ISD::BITCAST: in ExpandNode()
3326 DAG.getNode(ISD::BITCAST, dl, MVT::i16, Op)); in ExpandNode()
[all …]
H A DLegalizeVectorTypes.cpp57 case ISD::BITCAST: R = ScalarizeVecRes_BITCAST(N); break; in ScalarizeVectorResult()
395 return DAG.getNode(ISD::BITCAST, SDLoc(N), in ScalarizeVecRes_BUILD_VECTOR()
746 case ISD::BITCAST: in ScalarizeVectorOperand()
840 return DAG.getNode(ISD::BITCAST, SDLoc(N),
1082 case ISD::BITCAST: SplitVecRes_BITCAST(N, Lo, Hi); break; in SplitVectorResult()
1506 Lo = DAG.getNode(ISD::BITCAST, dl, LoVT, Lo); in SplitVecRes_BITCAST()
1507 Hi = DAG.getNode(ISD::BITCAST, dl, HiVT, Hi); in SplitVecRes_BITCAST()
1515 Lo = DAG.getNode(ISD::BITCAST, dl, LoVT, Lo); in SplitVecRes_BITCAST()
1516 Hi = DAG.getNode(ISD::BITCAST, dl, HiVT, Hi); in SplitVecRes_BITCAST()
1524 Lo = DAG.getNode(ISD::BITCAST, d in SplitVecRes_BITCAST()
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H A DSelectionDAGBuilder.cpp208 Lo = DAG.getNode(ISD::BITCAST, DL, HalfVT, Parts[0]); in getCopyFromParts()
209 Hi = DAG.getNode(ISD::BITCAST, DL, HalfVT, Parts[1]); in getCopyFromParts()
242 Lo = DAG.getNode(ISD::BITCAST, DL, EVT(MVT::f64), Parts[0]); in getCopyFromParts()
243 Hi = DAG.getNode(ISD::BITCAST, DL, EVT(MVT::f64), Parts[1]); in getCopyFromParts()
275 return DAG.getNode(ISD::BITCAST, DL, ValueVT, Val); in getCopyFromParts()
315 Val = DAG.getNode(ISD::BITCAST, DL, MVT::i64, Val); in getCopyFromParts()
420 return DAG.getNode(ISD::BITCAST, DL, ValueVT, Val); in getCopyFromPartsVector()
439 return DAG.getNode(ISD::BITCAST, DL, ValueVT, Val); in getCopyFromPartsVector()
443 return DAG.getNode(ISD::BITCAST, DL, ValueVT, Val); in getCopyFromPartsVector()
454 return DAG.getNode(ISD::BITCAST, DL, ValueVT, Val); in getCopyFromPartsVector()
[all …]
H A DLegalizeFloatTypes.cpp67 case ISD::BITCAST: R = SoftenFloatRes_BITCAST(N); break; in SoftenFloatResult()
637 DAG.getNode(ISD::BITCAST, DL, MVT::i16, Op)); in SoftenFloatRes_BF16_TO_FP()
998 case ISD::BITCAST: Res = SoftenFloatOp_BITCAST(N); break; in SoftenFloatOperand()
1050 return DAG.getNode(ISD::BITCAST, SDLoc(N), N->getValueType(0), Op0); in SoftenFloatOp_BITCAST()
1395 case ISD::BITCAST: ExpandRes_BITCAST(N, Lo, Hi); break; in ExpandFloatResult()
2071 case ISD::BITCAST: Res = ExpandOp_BITCAST(N); break; in ExpandFloatOperand()
2408 case ISD::BITCAST: R = PromoteFloatOp_BITCAST(N, OpNo); break; in PromoteFloatOperand()
2590 case ISD::BITCAST: R = PromoteFloatRes_BITCAST(N); break; in PromoteFloatResult()
3029 case ISD::BITCAST: R = SoftPromoteHalfRes_BITCAST(N); break; in SoftPromoteHalfResult()
3397 case ISD::BITCAST: Res = SoftPromoteHalfOp_BITCAST(N); break; in SoftPromoteHalfOperand()
[all …]
H A DLegalizeTypes.cpp880 return DAG.getNode(ISD::BITCAST, SDLoc(Op), in BitConvertToInteger()
890 return DAG.getNode(ISD::BITCAST, SDLoc(Op), in BitConvertVectorToIntegerVector()
H A DSelectionDAG.cpp182 while (N->getOpcode() == ISD::BITCAST) in isConstantSplatVectorAllOnes()
231 while (N->getOpcode() == ISD::BITCAST) in isConstantSplatVectorAllZeros()
1719 getNode(ISD::BITCAST, DL, VT, getBuildVector(ViaVecVT, DL, Ops)); in getConstant()
2190 while (V.getOpcode() == ISD::BITCAST) in getVectorShuffle()
2222 NewBV = getNode(ISD::BITCAST, dl, VT, NewBV); in getVectorShuffle()
2375 return getNode(ISD::BITCAST, SDLoc(V), VT, V); in getBitcast()
2890 case ISD::BITCAST: { in isSplatValue()
3356 case ISD::BITCAST: { in computeKnownBits()
4543 case ISD::BITCAST: { in ComputeNumSignBits()
5282 case ISD::BITCAST: in canCreateUndefOrPoison()
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/freebsd/contrib/llvm-project/llvm/lib/Target/LoongArch/
H A DLoongArchISelDAGToDAG.cpp84 case ISD::BITCAST: { in INITIALIZE_PASS()
357 if (N->getOpcode() == ISD::BITCAST) in selectVSplatImm()
382 if (N->getOpcode() == ISD::BITCAST) in selectVSplatUimmInvPow2()
403 if (N->getOpcode() == ISD::BITCAST) in selectVSplatUimmPow2()
/freebsd/contrib/llvm-project/llvm/lib/Target/AMDGPU/
H A DAMDGPUISelLowering.cpp613 setTargetDAGCombine({ISD::BITCAST, ISD::SHL, in AMDGPUTargetLowering()
675 case ISD::BITCAST: in fnegFoldsIntoOpcode()
684 if (Opc == ISD::BITCAST) { in fnegFoldsIntoOp()
735 case ISD::BITCAST: in hasSourceMods()
1522 SDValue NewIn = DAG.getNode(ISD::BITCAST, SL, NewEltVT, In); in LowerCONCAT_VECTORS()
1532 return DAG.getNode(ISD::BITCAST, SL, VT, BV); in LowerCONCAT_VECTORS()
1560 SDValue Tmp = DAG.getNode(ISD::BITCAST, SL, NewSrcVT, Op.getOperand(0)); in LowerEXTRACT_SUBVECTOR()
1568 return DAG.getNode(ISD::BITCAST, SL, VT, Tmp); in LowerEXTRACT_SUBVECTOR()
1706 SDValue Vec = DAG.getNode(ISD::BITCAST, SL, MVT::v2i32, Op); in split64BitValue()
1720 SDValue Vec = DAG.getNode(ISD::BITCAST, SL, MVT::v2i32, Op); in getLoHalf64()
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H A DSIISelLowering.cpp326 case ISD::BITCAST: in SITargetLowering()
627 case ISD::BITCAST: in SITargetLowering()
2067 ArgVal = DAG.getNode(ISD::BITCAST, SL, MemVT, ArgVal); in lowerKernargMemParameter()
2971 ArgVal = DAG.getNode(ISD::BITCAST, DL, MemVT, ArgVal); in LowerFormalArguments()
3090 Val = DAG.getNode(ISD::BITCAST, DL, ValVT, Val); in LowerFormalArguments()
3205 Arg = DAG.getNode(ISD::BITCAST, DL, VA.getLocVT(), Arg); in LowerReturn()
3283 Val = DAG.getNode(ISD::BITCAST, DL, VA.getValVT(), Val); in LowerCallResult()
3764 Arg = DAG.getNode(ISD::BITCAST, DL, VA.getLocVT(), Arg); in LowerCall()
4220 DAG.getNode(ISD::BITCAST, SL, SrcVT.changeTypeToInteger(), Src); in lowerFP_EXTEND()
4254 SDValue Result = DAG.getNode(ISD::BITCAST, SL, MVT::i64, CvtPtr); in lowerGET_FPENV()
[all …]
H A DR600ISelLowering.cpp892 True = DAG.getNode(ISD::BITCAST, DL, CompareVT, True); in LowerSELECT_CC()
893 False = DAG.getNode(ISD::BITCAST, DL, CompareVT, False); in LowerSELECT_CC()
912 return DAG.getNode(ISD::BITCAST, DL, VT, SelectNode); in LowerSELECT_CC()
1821 if (Arg.getOpcode() == ISD::BITCAST && in PerformDAGCombine()
1827 return DAG.getNode(ISD::BITCAST, DL, N->getVTList(), in PerformDAGCombine()
/freebsd/contrib/llvm-project/llvm/lib/Target/ARM/
H A DARMISelLowering.cpp245 setOperationAction(ISD::BITCAST, VT, Legal); in setAllExpand()
794 setOperationAction(ISD::BITCAST, MVT::i16, Custom); in ARMTargetLowering()
795 setOperationAction(ISD::BITCAST, MVT::f16, Custom); in ARMTargetLowering()
805 setOperationAction(ISD::BITCAST, MVT::bf16, Custom); in ARMTargetLowering()
1037 ISD::INTRINSIC_VOID, ISD::VECREDUCE_ADD, ISD::ADD, ISD::BITCAST}); in ARMTargetLowering()
1413 setOperationAction(ISD::BITCAST, MVT::i64, Custom); in ARMTargetLowering()
2174 Val = DAG.getNode(ISD::BITCAST, dl, MVT::getIntegerVT(LocVT.getSizeInBits()), in MoveToHPR()
2181 Val = DAG.getNode(ISD::BITCAST, dl, ValVT, Val); in MoveToHPR()
2193 Val = DAG.getNode(ISD::BITCAST, dl, in MoveFromHPR()
2198 return DAG.getNode(ISD::BITCAST, dl, LocVT, Val); in MoveFromHPR()
[all …]
/freebsd/contrib/llvm-project/llvm/lib/Target/SystemZ/
H A DSystemZISelLowering.cpp358 setOperationAction(ISD::BITCAST, MVT::i128, Custom); in SystemZTargetLowering()
411 setOperationAction(ISD::BITCAST, VT, Legal); in SystemZTargetLowering()
703 setOperationAction(ISD::BITCAST, MVT::i32, Custom); in SystemZTargetLowering()
704 setOperationAction(ISD::BITCAST, MVT::f32, Custom); in SystemZTargetLowering()
1496 Value = DAG.getNode(ISD::BITCAST, DL, VA.getValVT(), Value); in convertLocVTToValVT()
1525 Value = DAG.getNode(ISD::BITCAST, DL, BitCastToType, Value); in convertValVTToLocVT()
2859 C.Op1 = DAG.getNode(ISD::BITCAST, DL, MVT::v16i8, C.Op0.getOperand(1)); in adjustForTestUnderMask()
2860 C.Op0 = DAG.getNode(ISD::BITCAST, DL, MVT::v16i8, C.Op0.getOperand(0)); in adjustForTestUnderMask()
2969 C.Op0 = DAG.getNode(ISD::BITCAST, DL, MVT::v2i64, C.Op0); in adjustICmp128()
2970 C.Op1 = DAG.getNode(ISD::BITCAST, DL, MVT::v2i64, C.Op1); in adjustICmp128()
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H A DSystemZISelDAGToDAG.cpp1194 SDValue BitCast = CurDAG->getNode(ISD::BITCAST, DL, VT, Op); in loadVectorConstant()
1651 Src = CurDAG->getNode(ISD::BITCAST, DL, MVT::v16i8, Src); in Select()
1659 Res = CurDAG->getNode(ISD::BITCAST, DL, MVT::i128, Res); in Select()
/freebsd/contrib/llvm-project/llvm/lib/Target/PowerPC/
H A DPPCISelLowering.cpp561 setOperationAction(ISD::BITCAST, MVT::f32, Legal); in PPCTargetLowering()
562 setOperationAction(ISD::BITCAST, MVT::i32, Legal); in PPCTargetLowering()
563 setOperationAction(ISD::BITCAST, MVT::i64, Legal); in PPCTargetLowering()
564 setOperationAction(ISD::BITCAST, MVT::f64, Legal); in PPCTargetLowering()
576 setOperationAction(ISD::BITCAST, MVT::f32, Expand); in PPCTargetLowering()
577 setOperationAction(ISD::BITCAST, MVT::i32, Expand); in PPCTargetLowering()
578 setOperationAction(ISD::BITCAST, MVT::i64, Expand); in PPCTargetLowering()
579 setOperationAction(ISD::BITCAST, MVT::f64, Expand); in PPCTargetLowering()
1243 setOperationAction(ISD::BITCAST, MVT::i128, Custom); in PPCTargetLowering()
3761 dl, MVT::v4i32, DAG.getNode(ISD::BITCAST, dl, MVT::v4i32, LHS), in LowerSETCC()
[all …]
/freebsd/contrib/llvm-project/llvm/lib/Target/Mips/
H A DMipsSEISelDAGToDAG.cpp556 if (N->getOpcode() == ISD::BITCAST) in selectVSplatCommon()
632 if (N->getOpcode() == ISD::BITCAST) in selectVSplatUimmPow2()
663 if (N->getOpcode() == ISD::BITCAST) in selectVSplatMaskL()
696 if (N->getOpcode() == ISD::BITCAST) in selectVSplatMaskR()
717 if (N->getOpcode() == ISD::BITCAST) in selectVSplatUimmInvPow2()
738 if (N->getOpcode() == ISD::BITCAST) in selectVSplatImmEq1()
H A DMipsISelLowering.cpp2359 DAG.getNode(ISD::BITCAST, DL, MVT::i32, Op.getOperand(0)) : in lowerFCOPYSIGN32()
2363 DAG.getNode(ISD::BITCAST, DL, MVT::i32, Op.getOperand(1)) : in lowerFCOPYSIGN32()
2386 return DAG.getNode(ISD::BITCAST, DL, Op.getOperand(0).getValueType(), Res); in lowerFCOPYSIGN32()
2403 SDValue X = DAG.getNode(ISD::BITCAST, DL, TyX, Op.getOperand(0)); in lowerFCOPYSIGN64()
2404 SDValue Y = DAG.getNode(ISD::BITCAST, DL, TyY, Op.getOperand(1)); in lowerFCOPYSIGN64()
2420 return DAG.getNode(ISD::BITCAST, DL, Op.getOperand(0).getValueType(), I); in lowerFCOPYSIGN64()
2441 return DAG.getNode(ISD::BITCAST, DL, Op.getOperand(0).getValueType(), Or); in lowerFCOPYSIGN64()
2463 ? DAG.getNode(ISD::BITCAST, DL, MVT::i32, Op.getOperand(0)) in lowerFABS32()
2480 return DAG.getNode(ISD::BITCAST, DL, MVT::f32, Res); in lowerFABS32()
2501 SDValue X = DAG.getNode(ISD::BITCAST, DL, MVT::i64, Op.getOperand(0)); in lowerFABS64()
[all …]
H A DMipsSEISelLowering.cpp98 setOperationAction(ISD::BITCAST, VecTy, Legal); in MipsSETargetLowering()
216 setOperationAction(ISD::BITCAST, MVT::i64, Custom); in MipsSETargetLowering()
322 setOperationAction(ISD::BITCAST, Ty, Legal); in addMSAIntType()
378 setOperationAction(ISD::BITCAST, Ty, Legal); in addMSAFloatType()
468 case ISD::BITCAST: return lowerBITCAST(Op, DAG); in LowerOperation()
556 if (N->getOpcode() == ISD::BITCAST) in isVectorAllOnes()
1406 Result = DAG.getNode(ISD::BITCAST, DL, ResVecTy, in lowerMSASplatZExt()
1453 Result = DAG.getNode(ISD::BITCAST, DL, VecTy, Result); in getBuildVectorSplat()
1479 ISD::BITCAST, DL, MVT::v2i64, in lowerMSABinaryBitImmIntr()
2504 Result = DAG.getNode(ISD::BITCAST, SDLoc(Node), ResTy, Result); in lowerBUILD_VECTOR()
/freebsd/contrib/llvm-project/llvm/lib/Target/Sparc/
H A DSparcISelLowering.cpp492 WholeValue = DAG.getNode(ISD::BITCAST, dl, VA.getLocVT(), WholeValue); in LowerFormalArguments_32()
500 Arg = DAG.getNode(ISD::BITCAST, dl, MVT::f32, Arg); in LowerFormalArguments_32()
548 WholeValue = DAG.getNode(ISD::BITCAST, dl, VA.getValVT(), WholeValue); in LowerFormalArguments_32()
923 Arg = DAG.getNode(ISD::BITCAST, dl, VA.getLocVT(), Arg); in LowerCall_32()
969 Arg = DAG.getNode(ISD::BITCAST, dl, MVT::v2i32, Arg); in LowerCall_32()
1018 Arg = DAG.getNode(ISD::BITCAST, dl, MVT::i32, Arg); in LowerCall_32()
1295 Arg = DAG.getNode(ISD::BITCAST, DL, VA.getLocVT(), Arg); in LowerCall_64()
1706 setOperationAction(ISD::BITCAST, MVT::f32, Expand); in SparcTargetLowering()
1707 setOperationAction(ISD::BITCAST, MVT::i32, Expand); in SparcTargetLowering()
1744 setOperationAction(ISD::BITCAST, MVT::f64, Expand); in SparcTargetLowering()
[all …]
/freebsd/contrib/llvm-project/llvm/lib/Target/AArch64/
H A DAArch64ISelLowering.cpp1047 setOperationAction(ISD::BITCAST, MVT::i16, Custom); in AArch64TargetLowering()
1048 setOperationAction(ISD::BITCAST, MVT::f16, Custom); in AArch64TargetLowering()
1049 setOperationAction(ISD::BITCAST, MVT::bf16, Custom); in AArch64TargetLowering()
1371 setOperationAction(ISD::BITCAST, MVT::i2, Custom); in AArch64TargetLowering()
1372 setOperationAction(ISD::BITCAST, MVT::i4, Custom); in AArch64TargetLowering()
1373 setOperationAction(ISD::BITCAST, MVT::i8, Custom); in AArch64TargetLowering()
1374 setOperationAction(ISD::BITCAST, MVT::i16, Custom); in AArch64TargetLowering()
1376 setOperationAction(ISD::BITCAST, MVT::v2i8, Custom); in AArch64TargetLowering()
1377 setOperationAction(ISD::BITCAST, MVT::v2i16, Custom); in AArch64TargetLowering()
1378 setOperationAction(ISD::BITCAST, MVT::v4i8, Custom); in AArch64TargetLowering()
[all …]
/freebsd/contrib/llvm-project/llvm/lib/Target/Xtensa/
H A DXtensaISelLowering.cpp65 setOperationAction(ISD::BITCAST, MVT::i32, Expand); in XtensaTargetLowering()
66 setOperationAction(ISD::BITCAST, MVT::f32, Expand); in XtensaTargetLowering()
253 ArgValue = DAG.getNode((VA.getValVT() == MVT::f32) ? ISD::BITCAST in LowerFormalArguments()
/freebsd/contrib/llvm-project/llvm/include/llvm/CodeGen/
H A DISDOpcodes.h931 BITCAST, enumerator
/freebsd/contrib/llvm-project/llvm/lib/Target/Hexagon/
H A DHexagonISelLoweringHVX.cpp110 setOperationAction(ISD::BITCAST, MVT::i16, Custom); in initializeHVXLowering()
111 setOperationAction(ISD::BITCAST, MVT::i32, Custom); in initializeHVXLowering()
112 setOperationAction(ISD::BITCAST, MVT::i64, Custom); in initializeHVXLowering()
113 setOperationAction(ISD::BITCAST, MVT::v16i1, Custom); in initializeHVXLowering()
114 setOperationAction(ISD::BITCAST, MVT::v128i1, Custom); in initializeHVXLowering()
115 setOperationAction(ISD::BITCAST, MVT::i128, Custom); in initializeHVXLowering()
1888 // a BITCAST. Here we can skip the BITCAST (so we don't have to handle in LowerHvxCttz()
3210 case ISD::BITCAST: return LowerHvxBitcast(Op, DAG); in LowerHvxOperation()
3457 case ISD::BITCAST in ReplaceHvxNodeResults()
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/freebsd/contrib/llvm-project/llvm/lib/Target/NVPTX/
H A DNVPTXISelLowering.cpp1566 StVal = DAG.getNode(ISD::BITCAST, dl, ElementType, StVal); in LowerUnalignedStoreParam()
1631 RetVal = DAG.getNode(ISD::BITCAST, dl, ElementType, RetVal); in LowerUnalignedLoadRetParam()
2307 return DAG.getNode(ISD::BITCAST, DL, VT, E0123); in LowerBUILD_VECTOR()
2341 return DAG.getNode(ISD::BITCAST, SDLoc(Op), Op->getValueType(0), Const); in LowerBUILD_VECTOR()
2400 return DAG.getNode(ISD::BITCAST, DL, Op->getValueType(0), BFI); in LowerINSERT_VECTOR_ELT()
2573 SDValue Bitcast = DAG.getNode(ISD::BITCAST, SL, MVT::i32, A); in LowerFROUND32()
2582 DAG.getNode(ISD::BITCAST, SL, VT, PointFiveWithSignRaw); in LowerFROUND32()
3312 Elt = DAG.getNode(ISD::BITCAST, dl, EltVT, Elt); in LowerFormalArguments()
3372 RetVal = DAG.getNode(ISD::BITCAST, dl, ElementType, RetVal); in LowerUnalignedStoreRet()
5928 ISD::SRA, DL, IVT, DCI.DAG.getNode(ISD::BITCAST, DL, IVT, Vector), in PerformEXTRACTCombine()
[all …]

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