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Searched refs:BITCAST (Results 1 – 25 of 59) sorted by relevance

123

/freebsd/contrib/llvm-project/llvm/lib/CodeGen/SelectionDAG/
H A DLegalizeTypesGeneric.cpp58 Lo = DAG.getNode(ISD::BITCAST, dl, NOutVT, Lo); in ExpandRes_BITCAST()
59 Hi = DAG.getNode(ISD::BITCAST, dl, NOutVT, Hi); in ExpandRes_BITCAST()
69 Lo = DAG.getNode(ISD::BITCAST, dl, NOutVT, Lo); in ExpandRes_BITCAST()
70 Hi = DAG.getNode(ISD::BITCAST, dl, NOutVT, Hi); in ExpandRes_BITCAST()
77 Lo = DAG.getNode(ISD::BITCAST, dl, NOutVT, Lo); in ExpandRes_BITCAST()
78 Hi = DAG.getNode(ISD::BITCAST, dl, NOutVT, Hi); in ExpandRes_BITCAST()
83 Lo = DAG.getNode(ISD::BITCAST, dl, NOutVT, Lo); in ExpandRes_BITCAST()
84 Hi = DAG.getNode(ISD::BITCAST, dl, NOutVT, Hi); in ExpandRes_BITCAST()
96 Lo = DAG.getNode(ISD::BITCAST, dl, NOutVT, Lo); in ExpandRes_BITCAST()
97 Hi = DAG.getNode(ISD::BITCAST, dl, NOutVT, Hi); in ExpandRes_BITCAST()
[all …]
H A DLegalizeVectorOps.cpp795 Operands[j] = DAG.getNode(ISD::BITCAST, dl, NVT, Node->getOperand(j)); in Promote()
816 Res = DAG.getNode(ISD::BITCAST, dl, VT, Res); in Promote()
1370 Op1 = DAG.getNode(ISD::BITCAST, DL, MaskTy, Op1); in ExpandSELECT()
1371 Op2 = DAG.getNode(ISD::BITCAST, DL, MaskTy, Op2); in ExpandSELECT()
1378 return DAG.getNode(ISD::BITCAST, DL, Node->getValueType(0), Val); in ExpandSELECT()
1432 ISD::BITCAST, DL, VT, in ExpandANY_EXTEND_VECTOR_INREG()
1491 return DAG.getNode(ISD::BITCAST, DL, VT, in ExpandZERO_EXTEND_VECTOR_INREG()
1517 SDValue Op = DAG.getNode(ISD::BITCAST, DL, ByteVT, Node->getOperand(0)); in ExpandBSWAP()
1519 return DAG.getNode(ISD::BITCAST, DL, VT, Op); in ExpandBSWAP()
1561 SDValue Op = DAG.getNode(ISD::BITCAST, DL, ByteVT, Node->getOperand(0)); in ExpandBITREVERSE()
[all …]
H A DLegalizeDAG.cpp532 Value = DAG.getNode(ISD::BITCAST, dl, NVT, Value); in LegalizeStoreOps()
712 RVal = DAG.getNode(ISD::BITCAST, dl, VT, Res); in LegalizeLoadOps()
1641 State.IntValue = DAG.getNode(ISD::BITCAST, DL, IVT, Value); in getSignAsIntValue()
1688 return DAG.getNode(ISD::BITCAST, DL, State.FloatVT, NewIntValue); in modifySignAsInt()
2543 SDValue AsFP = DAG.getNode(ISD::BITCAST, dl, VT, AsInt); in expandLdexp()
2610 SDValue AsInt = DAG.getNode(ISD::BITCAST, dl, AsIntVT, Val); in expandFrexp()
2625 SDValue ScaledAsInt = DAG.getNode(ISD::BITCAST, dl, AsIntVT, ScaleUp); in expandFrexp()
2652 SDValue MaskedFract = DAG.getNode(ISD::BITCAST, dl, VT, Or); in expandFrexp()
3310 case ISD::BITCAST: in ExpandNode()
3357 DAG.getNode(ISD::BITCAST, dl, MVT::i16, Op)); in ExpandNode()
[all …]
H A DLegalizeVectorTypes.cpp57 case ISD::BITCAST: R = ScalarizeVecRes_BITCAST(N); break; in ScalarizeVectorResult()
404 return DAG.getNode(ISD::BITCAST, SDLoc(N), in ScalarizeVecRes_BITCAST()
747 case ISD::BITCAST: in ScalarizeVectorOperand()
853 return DAG.getNode(ISD::BITCAST, SDLoc(N), in ScalarizeVecOp_BITCAST()
1130 case ISD::BITCAST: SplitVecRes_BITCAST(N, Lo, Hi); break; in SplitVectorResult()
1574 Lo = DAG.getNode(ISD::BITCAST, dl, LoVT, Lo); in SplitVecRes_BITCAST()
1575 Hi = DAG.getNode(ISD::BITCAST, dl, HiVT, Hi); in SplitVecRes_BITCAST()
1583 Lo = DAG.getNode(ISD::BITCAST, dl, LoVT, Lo); in SplitVecRes_BITCAST()
1584 Hi = DAG.getNode(ISD::BITCAST, dl, HiVT, Hi); in SplitVecRes_BITCAST()
1592 Lo = DAG.getNode(ISD::BITCAST, dl, LoVT, InLo); in SplitVecRes_BITCAST()
[all …]
H A DSelectionDAGBuilder.cpp204 Lo = DAG.getNode(ISD::BITCAST, DL, HalfVT, Parts[0]); in getCopyFromParts()
205 Hi = DAG.getNode(ISD::BITCAST, DL, HalfVT, Parts[1]); in getCopyFromParts()
238 Lo = DAG.getNode(ISD::BITCAST, DL, EVT(MVT::f64), Parts[0]); in getCopyFromParts()
239 Hi = DAG.getNode(ISD::BITCAST, DL, EVT(MVT::f64), Parts[1]); in getCopyFromParts()
271 return DAG.getNode(ISD::BITCAST, DL, ValueVT, Val); in getCopyFromParts()
311 Val = DAG.getNode(ISD::BITCAST, DL, MVT::i64, Val); in getCopyFromParts()
417 return DAG.getNode(ISD::BITCAST, DL, ValueVT, Val); in getCopyFromPartsVector()
436 return DAG.getNode(ISD::BITCAST, DL, ValueVT, Val); in getCopyFromPartsVector()
440 return DAG.getNode(ISD::BITCAST, DL, ValueVT, Val); in getCopyFromPartsVector()
451 return DAG.getNode(ISD::BITCAST, DL, ValueVT, Val); in getCopyFromPartsVector()
[all …]
H A DLegalizeFloatTypes.cpp67 case ISD::BITCAST: R = SoftenFloatRes_BITCAST(N); break; in SoftenFloatResult()
682 DAG.getNode(ISD::BITCAST, DL, MVT::i16, Op)); in SoftenFloatRes_BF16_TO_FP()
1140 case ISD::BITCAST: Res = SoftenFloatOp_BITCAST(N); break; in SoftenFloatOperand()
1195 return DAG.getNode(ISD::BITCAST, SDLoc(N), N->getValueType(0), Op0); in SoftenFloatOp_BITCAST()
1547 case ISD::BITCAST: ExpandRes_BITCAST(N, Lo, Hi); break; in ExpandFloatResult()
2287 case ISD::BITCAST: Res = ExpandOp_BITCAST(N); break; in ExpandFloatOperand()
2618 case ISD::BITCAST: R = PromoteFloatOp_BITCAST(N, OpNo); break; in PromoteFloatOperand()
2819 case ISD::BITCAST: in PromoteFloatResult()
3307 case ISD::BITCAST: R = SoftPromoteHalfRes_BITCAST(N); break; in SoftPromoteHalfResult()
3575 return DAG.getNode(ISD::BITCAST, SDLoc(N), MVT::i16, Tmp.first); in SoftPromoteHalfRes_FP_ROUND()
[all …]
H A DLegalizeTypes.cpp883 return DAG.getNode(ISD::BITCAST, SDLoc(Op), in BitConvertToInteger()
893 return DAG.getNode(ISD::BITCAST, SDLoc(Op), in BitConvertVectorToIntegerVector()
H A DSelectionDAG.cpp184 while (N->getOpcode() == ISD::BITCAST) in isConstantSplatVectorAllOnes()
230 while (N->getOpcode() == ISD::BITCAST) in isConstantSplatVectorAllZeros()
1758 getNode(ISD::BITCAST, DL, VT, getBuildVector(ViaVecVT, DL, Ops)); in getConstant()
2247 while (V.getOpcode() == ISD::BITCAST) in getVectorShuffle()
2279 NewBV = getNode(ISD::BITCAST, dl, VT, NewBV); in getVectorShuffle()
2433 return getNode(ISD::BITCAST, SDLoc(V), VT, V); in getBitcast()
3138 case ISD::BITCAST: { in isSplatValue()
3599 case ISD::BITCAST: { in computeKnownBits()
4814 case ISD::BITCAST: { in ComputeNumSignBits()
5568 case ISD::BITCAST: in canCreateUndefOrPoison()
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/freebsd/contrib/llvm-project/llvm/lib/Target/LoongArch/
H A DLoongArchISelDAGToDAG.cpp101 case ISD::BITCAST: { in INITIALIZE_PASS()
396 if (N->getOpcode() == ISD::BITCAST) in selectVSplatImm()
421 if (N->getOpcode() == ISD::BITCAST) in selectVSplatUimmInvPow2()
442 if (N->getOpcode() == ISD::BITCAST) in selectVSplatUimmPow2()
H A DLoongArchISelLowering.cpp145 setOperationAction(ISD::BITCAST, MVT::i32, Custom); in LoongArchTargetLowering()
173 setOperationAction(ISD::BITCAST, MVT::i64, Custom); in LoongArchTargetLowering()
284 setOperationAction(ISD::BITCAST, VT, Legal); in LoongArchTargetLowering()
350 setOperationAction(ISD::BITCAST, VT, Legal); in LoongArchTargetLowering()
412 setTargetDAGCombine(ISD::BITCAST); in LoongArchTargetLowering()
484 case ISD::BITCAST: in LowerOperation()
884 SDValue NewSrc = DAG.getNode(ISD::BITCAST, DL, NewVT, Src); in lowerBITREVERSE()
896 DAG.getNode(ISD::BITCAST, DL, ResTy, DAG.getBuildVector(NewVT, DL, Ops)); in lowerBITREVERSE()
2503 Result = DAG.getNode(ISD::BITCAST, SDLoc(Node), ResTy, Result); in lowerBUILD_VECTOR()
2824 return DAG.getNode(ISD::BITCAST, DL, Op.getValueType(), Trunc); in lowerFP_TO_SINT()
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/freebsd/contrib/llvm-project/llvm/lib/Target/AMDGPU/
H A DAMDGPUISelLowering.cpp626 setTargetDAGCombine({ISD::BITCAST, ISD::SHL, in AMDGPUTargetLowering()
690 case ISD::BITCAST: in fnegFoldsIntoOpcode()
699 if (Opc == ISD::BITCAST) { in fnegFoldsIntoOp()
750 case ISD::BITCAST: in hasSourceMods()
1579 SDValue NewIn = DAG.getNode(ISD::BITCAST, SL, NewEltVT, In); in LowerCONCAT_VECTORS()
1589 return DAG.getNode(ISD::BITCAST, SL, VT, BV); in LowerCONCAT_VECTORS()
1617 SDValue Tmp = DAG.getNode(ISD::BITCAST, SL, NewSrcVT, Op.getOperand(0)); in LowerEXTRACT_SUBVECTOR()
1625 return DAG.getNode(ISD::BITCAST, SL, VT, Tmp); in LowerEXTRACT_SUBVECTOR()
1763 SDValue Vec = DAG.getNode(ISD::BITCAST, SL, MVT::v2i32, Op); in split64BitValue()
1777 SDValue Vec = DAG.getNode(ISD::BITCAST, SL, MVT::v2i32, Op); in getLoHalf64()
[all …]
H A DSIISelLowering.cpp333 case ISD::BITCAST: in SITargetLowering()
643 case ISD::BITCAST: in SITargetLowering()
2174 ArgVal = DAG.getNode(ISD::BITCAST, SL, MemVT, ArgVal); in lowerKernargMemParameter()
3077 ArgVal = DAG.getNode(ISD::BITCAST, DL, MemVT, ArgVal); in LowerFormalArguments()
3211 Val = DAG.getNode(ISD::BITCAST, DL, ValVT, Val); in LowerFormalArguments()
3325 Arg = DAG.getNode(ISD::BITCAST, DL, VA.getLocVT(), Arg); in LowerReturn()
3406 Val = DAG.getNode(ISD::BITCAST, DL, VA.getValVT(), Val); in LowerCallResult()
3933 Arg = DAG.getNode(ISD::BITCAST, DL, VA.getLocVT(), Arg); in LowerCall()
4436 DAG.getNode(ISD::BITCAST, SL, SrcVT.changeTypeToInteger(), Src); in lowerFP_EXTEND()
4470 SDValue Result = DAG.getNode(ISD::BITCAST, SL, MVT::i64, CvtPtr); in lowerGET_FPENV()
[all …]
H A DR600ISelLowering.cpp896 True = DAG.getNode(ISD::BITCAST, DL, CompareVT, True); in LowerSELECT_CC()
897 False = DAG.getNode(ISD::BITCAST, DL, CompareVT, False); in LowerSELECT_CC()
916 return DAG.getNode(ISD::BITCAST, DL, VT, SelectNode); in LowerSELECT_CC()
1826 if (Arg.getOpcode() == ISD::BITCAST && in PerformDAGCombine()
1832 return DAG.getNode(ISD::BITCAST, DL, N->getVTList(), in PerformDAGCombine()
/freebsd/contrib/llvm-project/llvm/lib/Target/ARM/
H A DARMISelLowering.cpp250 setOperationAction(ISD::BITCAST, VT, Legal); in setAllExpand()
779 setOperationAction(ISD::BITCAST, MVT::i16, Custom); in ARMTargetLowering()
780 setOperationAction(ISD::BITCAST, MVT::f16, Custom); in ARMTargetLowering()
790 setOperationAction(ISD::BITCAST, MVT::bf16, Custom); in ARMTargetLowering()
1035 ISD::INTRINSIC_VOID, ISD::VECREDUCE_ADD, ISD::ADD, ISD::BITCAST}); in ARMTargetLowering()
1372 setOperationAction(ISD::BITCAST, MVT::i64, Custom); in ARMTargetLowering()
2168 Val = DAG.getNode(ISD::BITCAST, dl, MVT::getIntegerVT(LocVT.getSizeInBits()), in MoveToHPR()
2175 Val = DAG.getNode(ISD::BITCAST, dl, ValVT, Val); in MoveToHPR()
2187 Val = DAG.getNode(ISD::BITCAST, dl, in MoveFromHPR()
2192 return DAG.getNode(ISD::BITCAST, dl, LocVT, Val); in MoveFromHPR()
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/freebsd/contrib/llvm-project/llvm/lib/Target/Mips/
H A DMipsSEISelDAGToDAG.cpp552 if (N->getOpcode() == ISD::BITCAST) in selectVSplatCommon()
582 if (N->getOpcode() == ISD::BITCAST) in selectVSplatUimmPow2()
613 if (N->getOpcode() == ISD::BITCAST) in selectVSplatMaskL()
644 if (N->getOpcode() == ISD::BITCAST) in selectVSplatMaskR()
663 if (N->getOpcode() == ISD::BITCAST) in selectVSplatUimmInvPow2()
684 if (N->getOpcode() == ISD::BITCAST) in selectVSplatImmEq1()
H A DMipsISelLowering.cpp2500 DAG.getNode(ISD::BITCAST, DL, MVT::i32, Op.getOperand(0)) : in lowerFCOPYSIGN32()
2504 DAG.getNode(ISD::BITCAST, DL, MVT::i32, Op.getOperand(1)) : in lowerFCOPYSIGN32()
2527 return DAG.getNode(ISD::BITCAST, DL, Op.getOperand(0).getValueType(), Res); in lowerFCOPYSIGN32()
2544 SDValue X = DAG.getNode(ISD::BITCAST, DL, TyX, Op.getOperand(0)); in lowerFCOPYSIGN64()
2545 SDValue Y = DAG.getNode(ISD::BITCAST, DL, TyY, Op.getOperand(1)); in lowerFCOPYSIGN64()
2561 return DAG.getNode(ISD::BITCAST, DL, Op.getOperand(0).getValueType(), I); in lowerFCOPYSIGN64()
2582 return DAG.getNode(ISD::BITCAST, DL, Op.getOperand(0).getValueType(), Or); in lowerFCOPYSIGN64()
2604 ? DAG.getNode(ISD::BITCAST, DL, MVT::i32, Op.getOperand(0)) in lowerFABS32()
2621 return DAG.getNode(ISD::BITCAST, DL, MVT::f32, Res); in lowerFABS32()
2642 SDValue X = DAG.getNode(ISD::BITCAST, DL, MVT::i64, Op.getOperand(0)); in lowerFABS64()
[all …]
H A DMipsSEISelLowering.cpp137 setOperationAction(ISD::BITCAST, VecTy, Legal); in MipsSETargetLowering()
255 setOperationAction(ISD::BITCAST, MVT::i64, Custom); in MipsSETargetLowering()
361 setOperationAction(ISD::BITCAST, Ty, Legal); in addMSAIntType()
417 setOperationAction(ISD::BITCAST, Ty, Legal); in addMSAFloatType()
507 case ISD::BITCAST: return lowerBITCAST(Op, DAG); in LowerOperation()
595 if (N->getOpcode() == ISD::BITCAST) in isVectorAllOnes()
1450 Result = DAG.getNode(ISD::BITCAST, DL, ResVecTy, in lowerMSASplatZExt()
1497 Result = DAG.getNode(ISD::BITCAST, DL, VecTy, Result); in getBuildVectorSplat()
1523 ISD::BITCAST, DL, MVT::v2i64, in lowerMSABinaryBitImmIntr()
2548 Result = DAG.getNode(ISD::BITCAST, SDLoc(Node), ResTy, Result); in lowerBUILD_VECTOR()
/freebsd/contrib/llvm-project/llvm/lib/Target/SystemZ/
H A DSystemZISelLowering.cpp380 setOperationAction(ISD::BITCAST, MVT::i128, Custom); in SystemZTargetLowering()
433 setOperationAction(ISD::BITCAST, VT, Legal); in SystemZTargetLowering()
554 setOperationAction(ISD::BITCAST, MVT::i16, Custom); in SystemZTargetLowering()
763 setOperationAction(ISD::BITCAST, MVT::i32, Custom); in SystemZTargetLowering()
764 setOperationAction(ISD::BITCAST, MVT::f32, Custom); in SystemZTargetLowering()
1824 Value = DAG.getNode(ISD::BITCAST, DL, VA.getValVT(), Value); in convertLocVTToValVT()
1853 Value = DAG.getNode(ISD::BITCAST, DL, BitCastToType, Value); in convertValVTToLocVT()
3207 C.Op1 = DAG.getNode(ISD::BITCAST, DL, MVT::v16i8, C.Op0.getOperand(1)); in adjustForTestUnderMask()
3208 C.Op0 = DAG.getNode(ISD::BITCAST, DL, MVT::v16i8, C.Op0.getOperand(0)); in adjustForTestUnderMask()
3356 C.Op0 = DAG.getNode(ISD::BITCAST, DL, MVT::v2i64, C.Op0); in adjustICmp128()
[all …]
/freebsd/contrib/llvm-project/llvm/lib/Target/PowerPC/
H A DPPCISelLowering.cpp568 setOperationAction(ISD::BITCAST, MVT::f32, Legal); in PPCTargetLowering()
569 setOperationAction(ISD::BITCAST, MVT::i32, Legal); in PPCTargetLowering()
570 setOperationAction(ISD::BITCAST, MVT::i64, Legal); in PPCTargetLowering()
571 setOperationAction(ISD::BITCAST, MVT::f64, Legal); in PPCTargetLowering()
583 setOperationAction(ISD::BITCAST, MVT::f32, Expand); in PPCTargetLowering()
584 setOperationAction(ISD::BITCAST, MVT::i32, Expand); in PPCTargetLowering()
585 setOperationAction(ISD::BITCAST, MVT::i64, Expand); in PPCTargetLowering()
586 setOperationAction(ISD::BITCAST, MVT::f64, Expand); in PPCTargetLowering()
1261 setOperationAction(ISD::BITCAST, MVT::i128, Custom); in PPCTargetLowering()
3776 dl, MVT::v4i32, DAG.getNode(ISD::BITCAST, dl, MVT::v4i32, LHS), in LowerSETCC()
[all …]
/freebsd/contrib/llvm-project/llvm/lib/Target/Sparc/
H A DSparcISelLowering.cpp496 WholeValue = DAG.getNode(ISD::BITCAST, dl, VA.getLocVT(), WholeValue); in LowerFormalArguments_32()
504 Arg = DAG.getNode(ISD::BITCAST, dl, MVT::f32, Arg); in LowerFormalArguments_32()
552 WholeValue = DAG.getNode(ISD::BITCAST, dl, VA.getValVT(), WholeValue); in LowerFormalArguments_32()
927 Arg = DAG.getNode(ISD::BITCAST, dl, VA.getLocVT(), Arg); in LowerCall_32()
973 Arg = DAG.getNode(ISD::BITCAST, dl, MVT::v2i32, Arg); in LowerCall_32()
1022 Arg = DAG.getNode(ISD::BITCAST, dl, MVT::i32, Arg); in LowerCall_32()
1290 Arg = DAG.getNode(ISD::BITCAST, DL, VA.getLocVT(), Arg); in LowerCall_64()
1697 setOperationAction(ISD::BITCAST, MVT::f32, in SparcTargetLowering()
1699 setOperationAction(ISD::BITCAST, MVT::i32, in SparcTargetLowering()
1738 setOperationAction(ISD::BITCAST, MVT::f64, in SparcTargetLowering()
[all …]
/freebsd/contrib/llvm-project/llvm/lib/Target/Xtensa/
H A DXtensaISelLowering.cpp87 setOperationAction(ISD::BITCAST, MVT::i32, Expand); in XtensaTargetLowering()
88 setOperationAction(ISD::BITCAST, MVT::f32, Expand); in XtensaTargetLowering()
229 setOperationAction(ISD::BITCAST, MVT::i32, Legal); in XtensaTargetLowering()
230 setOperationAction(ISD::BITCAST, MVT::f32, Legal); in XtensaTargetLowering()
236 setOperationAction(ISD::BITCAST, MVT::i32, Expand); in XtensaTargetLowering()
237 setOperationAction(ISD::BITCAST, MVT::f32, Expand); in XtensaTargetLowering()
482 ArgValue = DAG.getNode((VA.getValVT() == MVT::f32) ? ISD::BITCAST in LowerFormalArguments()
/freebsd/contrib/llvm-project/llvm/lib/Target/AArch64/
H A DAArch64ISelLowering.cpp1089 setOperationAction(ISD::BITCAST, MVT::i16, Custom); in AArch64TargetLowering()
1090 setOperationAction(ISD::BITCAST, MVT::f16, Custom); in AArch64TargetLowering()
1091 setOperationAction(ISD::BITCAST, MVT::bf16, Custom); in AArch64TargetLowering()
1426 setOperationAction(ISD::BITCAST, MVT::i2, Custom); in AArch64TargetLowering()
1427 setOperationAction(ISD::BITCAST, MVT::i4, Custom); in AArch64TargetLowering()
1428 setOperationAction(ISD::BITCAST, MVT::i8, Custom); in AArch64TargetLowering()
1429 setOperationAction(ISD::BITCAST, MVT::i16, Custom); in AArch64TargetLowering()
1431 setOperationAction(ISD::BITCAST, MVT::v2i8, Custom); in AArch64TargetLowering()
1432 setOperationAction(ISD::BITCAST, MVT::v2i16, Custom); in AArch64TargetLowering()
1433 setOperationAction(ISD::BITCAST, MVT::v4i8, Custom); in AArch64TargetLowering()
[all …]
/freebsd/contrib/llvm-project/llvm/include/llvm/CodeGen/
H A DISDOpcodes.h975 BITCAST, enumerator
/freebsd/contrib/llvm-project/llvm/lib/Target/NVPTX/
H A DNVPTXISelLowering.cpp635 setOperationAction(ISD::BITCAST, MVT::v2i8, Custom); in NVPTXTargetLowering()
1342 StVal = DAG.getNode(ISD::BITCAST, dl, ElementType, StVal); in LowerUnalignedStoreParam()
1407 RetVal = DAG.getNode(ISD::BITCAST, dl, ElementType, RetVal); in LowerUnalignedLoadRetParam()
2122 return DAG.getNode(ISD::BITCAST, DL, VT, PRMT3210); in LowerBUILD_VECTOR()
2165 return DAG.getNode(ISD::BITCAST, DL, Op->getValueType(0), Const); in LowerBUILD_VECTOR()
2225 return DAG.getNode(ISD::BITCAST, DL, Op->getValueType(0), BFI); in LowerINSERT_VECTOR_ELT()
2415 SDValue Bitcast = DAG.getNode(ISD::BITCAST, SL, MVT::i32, A); in LowerFROUND32()
2424 DAG.getNode(ISD::BITCAST, SL, VT, PointFiveWithSignRaw); in LowerFROUND32()
2720 SDValue Cast = DAG.getNode(ISD::BITCAST, DL, MVT::v2i64, TryCancelResponse); in LowerClusterLaunchControlQueryCancel()
2894 case ISD::BITCAST: in LowerOperation()
[all …]
/freebsd/contrib/llvm-project/llvm/lib/Target/Hexagon/
H A DHexagonISelLoweringHVX.cpp110 setOperationAction(ISD::BITCAST, MVT::i16, Custom); in initializeHVXLowering()
111 setOperationAction(ISD::BITCAST, MVT::i32, Custom); in initializeHVXLowering()
112 setOperationAction(ISD::BITCAST, MVT::i64, Custom); in initializeHVXLowering()
113 setOperationAction(ISD::BITCAST, MVT::v16i1, Custom); in initializeHVXLowering()
114 setOperationAction(ISD::BITCAST, MVT::v128i1, Custom); in initializeHVXLowering()
115 setOperationAction(ISD::BITCAST, MVT::i128, Custom); in initializeHVXLowering()
121 setOperationAction(ISD::BITCAST, MVT::v32i1, Custom); in initializeHVXLowering()
2023 Val32 = DAG.getNode(ISD::BITCAST, dl, MVT::i32, Val); in LowerHvxBitcast()
3247 case ISD::BITCAST: return LowerHvxBitcast(Op, DAG); in LowerHvxOperation()
3494 case ISD::BITCAST: in ReplaceHvxNodeResults()
[all …]

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