Lines Matching refs:BITCAST
245 setOperationAction(ISD::BITCAST, VT, Legal); in setAllExpand()
794 setOperationAction(ISD::BITCAST, MVT::i16, Custom); in ARMTargetLowering()
795 setOperationAction(ISD::BITCAST, MVT::f16, Custom); in ARMTargetLowering()
805 setOperationAction(ISD::BITCAST, MVT::bf16, Custom); in ARMTargetLowering()
1037 ISD::INTRINSIC_VOID, ISD::VECREDUCE_ADD, ISD::ADD, ISD::BITCAST}); in ARMTargetLowering()
1413 setOperationAction(ISD::BITCAST, MVT::i64, Custom); in ARMTargetLowering()
2174 Val = DAG.getNode(ISD::BITCAST, dl, MVT::getIntegerVT(LocVT.getSizeInBits()), in MoveToHPR()
2181 Val = DAG.getNode(ISD::BITCAST, dl, ValVT, Val); in MoveToHPR()
2193 Val = DAG.getNode(ISD::BITCAST, dl, in MoveFromHPR()
2198 return DAG.getNode(ISD::BITCAST, dl, LocVT, Val); in MoveFromHPR()
2274 Val = DAG.getNode(ISD::BITCAST, dl, VA.getValVT(), Val); in LowerCallResult()
2524 Arg = DAG.getNode(ISD::BITCAST, dl, VA.getLocVT(), Arg); in LowerCall()
2548 Arg = DAG.getNode(ISD::BITCAST, dl, MVT::getIntegerVT(LocBits), Arg); in LowerCall()
2550 Arg = DAG.getNode(ISD::BITCAST, dl, VA.getLocVT(), Arg); in LowerCall()
3249 if (Arg.getValueType() == MVT::f32 && Arg.getOpcode() == ISD::BITCAST) { in LowerReturn()
3253 if (BC.getOpcode() == ISD::BITCAST && BC.getValueType() == MVT::i16) { in LowerReturn()
3266 Arg = DAG.getNode(ISD::BITCAST, dl, VA.getLocVT(), Arg); in LowerReturn()
3280 Arg = DAG.getNode(ISD::BITCAST, dl, MVT::getIntegerVT(LocBits), Arg); in LowerReturn()
3282 Arg = DAG.getNode(ISD::BITCAST, dl, VA.getLocVT(), Arg); in LowerReturn()
3410 } else if (Copy->getOpcode() == ISD::BITCAST) { in isUsedByReturnOnly()
4468 Val = DAG.getNode(ISD::BITCAST, DL, MVT::getIntegerVT(ValueBits), Val); in splitValueIntoRegisterParts()
4470 Val = DAG.getNode(ISD::BITCAST, DL, PartVT, Val); in splitValueIntoRegisterParts()
4485 Val = DAG.getNode(ISD::BITCAST, DL, MVT::getIntegerVT(PartBits), Val); in joinRegisterPartsIntoValue()
4487 Val = DAG.getNode(ISD::BITCAST, DL, ValueVT, Val); in joinRegisterPartsIntoValue()
4623 ArgValue = DAG.getNode(ISD::BITCAST, dl, VA.getValVT(), ArgValue); in LowerFormalArguments()
4733 } else if (Op->getOpcode() == ISD::BITCAST && in isFloatingPointZero()
6044 bool InGPR = Tmp0.getOpcode() == ISD::BITCAST || in LowerFCOPYSIGN()
6056 DAG.getNode(ISD::BITCAST, dl, OpVT, Mask), in LowerFCOPYSIGN()
6064 DAG.getNode(ISD::BITCAST, dl, OpVT, Tmp1), in LowerFCOPYSIGN()
6068 DAG.getNode(ISD::BITCAST, dl, MVT::v1i64, Tmp1), in LowerFCOPYSIGN()
6070 Tmp0 = DAG.getNode(ISD::BITCAST, dl, OpVT, Tmp0); in LowerFCOPYSIGN()
6071 Tmp1 = DAG.getNode(ISD::BITCAST, dl, OpVT, Tmp1); in LowerFCOPYSIGN()
6077 DAG.getNode(ISD::BITCAST, dl, OpVT, AllOnes)); in LowerFCOPYSIGN()
6083 Res = DAG.getNode(ISD::BITCAST, dl, MVT::v2f32, Res); in LowerFCOPYSIGN()
6087 Res = DAG.getNode(ISD::BITCAST, dl, MVT::f64, Res); in LowerFCOPYSIGN()
6097 Tmp1 = DAG.getNode(ISD::BITCAST, dl, MVT::i32, Tmp1); in LowerFCOPYSIGN()
6105 DAG.getNode(ISD::BITCAST, dl, MVT::i32, Tmp0), Mask2); in LowerFCOPYSIGN()
6106 return DAG.getNode(ISD::BITCAST, dl, MVT::f32, in LowerFCOPYSIGN()
6239 SDValue BitCast = DAG.getNode(ISD::BITCAST, dl, VecVT, ExtractSrc); in CombineVMOVDRRCandidateWithVecOp()
6282 return DAG.getNode(ISD::BITCAST, dl, DstVT, in ExpandBITCAST()
6316 return DAG.getNode(ISD::BITCAST, dl, VT, Vmov); in getZeroVector()
6612 while (Op.getOpcode() == ISD::BITCAST) in getVShiftImm()
6817 SDValue CastOp0 = DAG.getNode(ISD::BITCAST, dl, SplitVT, Op0); in LowerVSETCC()
6818 SDValue CastOp1 = DAG.getNode(ISD::BITCAST, dl, SplitVT, Op1); in LowerVSETCC()
6823 Merged = DAG.getNode(ISD::BITCAST, dl, CmpVT, Merged); in LowerVSETCC()
6913 if (AndOp.getNode() && AndOp.getOpcode() == ISD::BITCAST) in LowerVSETCC()
6917 Op0 = DAG.getNode(ISD::BITCAST, dl, CmpVT, AndOp.getOperand(0)); in LowerVSETCC()
6918 Op1 = DAG.getNode(ISD::BITCAST, dl, CmpVT, AndOp.getOperand(1)); in LowerVSETCC()
7226 return DAG.getNode(ISD::BITCAST, DL, MVT::f64, VecConstant); in LowerConstantFP()
7229 SDValue VecFConstant = DAG.getNode(ISD::BITCAST, DL, MVT::v2f32, in LowerConstantFP()
7243 return DAG.getNode(ISD::BITCAST, DL, MVT::f64, VecConstant); in LowerConstantFP()
7246 SDValue VecFConstant = DAG.getNode(ISD::BITCAST, DL, MVT::v2f32, in LowerConstantFP()
7959 return DAG.getNode(ISD::BITCAST, dl, VT, Vmov); in LowerBUILD_VECTOR()
7969 return DAG.getNode(ISD::BITCAST, dl, VT, Vmov); in LowerBUILD_VECTOR()
8097 Ops.push_back(DAG.getNode(ISD::BITCAST, dl, IVT, in LowerBUILD_VECTOR()
8103 return DAG.getNode(ISD::BITCAST, dl, VT, Val); in LowerBUILD_VECTOR()
8159 Ops.push_back(DAG.getNode(ISD::BITCAST, dl, EltVT, Op.getOperand(i))); in LowerBUILD_VECTOR()
8161 return DAG.getNode(ISD::BITCAST, dl, VT, Val); in LowerBUILD_VECTOR()
8621 return DAG.getNode(ISD::BITCAST, dl, NewVT, PredAsVector); in PromoteMVEPredVector()
9010 V1 = DAG.getNode(ISD::BITCAST, dl, VecVT, V1); in LowerVECTOR_SHUFFLE()
9011 V2 = DAG.getNode(ISD::BITCAST, dl, VecVT, V2); in LowerVECTOR_SHUFFLE()
9023 return DAG.getNode(ISD::BITCAST, dl, VT, Val); in LowerVECTOR_SHUFFLE()
9094 SDValue IElt = DAG.getNode(ISD::BITCAST, dl, IEltVT, Elt); in LowerINSERT_VECTOR_ELT()
9095 SDValue IVecIn = DAG.getNode(ISD::BITCAST, dl, IVecVT, VecIn); in LowerINSERT_VECTOR_ELT()
9098 return DAG.getNode(ISD::BITCAST, dl, VecVT, IVecOut); in LowerINSERT_VECTOR_ELT()
9241 DAG.getNode(ISD::BITCAST, dl, MVT::f64, Op0), in LowerCONCAT_VECTORS()
9245 DAG.getNode(ISD::BITCAST, dl, MVT::f64, Op1), in LowerCONCAT_VECTORS()
9247 return DAG.getNode(ISD::BITCAST, dl, Op.getValueType(), Val); in LowerCONCAT_VECTORS()
9420 if (VT == MVT::v2i64 && N->getOpcode() == ISD::BITCAST) { in isExtendedBUILD_VECTOR()
9578 if (N->getOpcode() == ISD::BITCAST) { in SkipExtensionForVMULL()
9696 DAG.getNode(ISD::BITCAST, DL, Op1VT, N00), Op1), in LowerMUL()
9698 DAG.getNode(ISD::BITCAST, DL, Op1VT, N01), Op1)); in LowerMUL()
9722 X = DAG.getNode(ISD::BITCAST, dl, MVT::v4i32, X); in LowerSDIV_v4i8()
9725 X = DAG.getNode(ISD::BITCAST, dl, MVT::v4f32, X); in LowerSDIV_v4i8()
9760 N0 = DAG.getNode(ISD::BITCAST, dl, MVT::v4i32, N0); in LowerSDIV_v4i16()
9763 N0 = DAG.getNode(ISD::BITCAST, dl, MVT::v4f32, N0); in LowerSDIV_v4i16()
9873 N0 = DAG.getNode(ISD::BITCAST, dl, MVT::v4i32, N0); in LowerUDIV()
9876 N0 = DAG.getNode(ISD::BITCAST, dl, MVT::v4f32, N0); in LowerUDIV()
10282 bool PassThruIsCastZero = (PassThru.getOpcode() == ISD::BITCAST || in LowerMLOAD()
10601 case ISD::BITCAST: return ExpandBITCAST(Op.getNode(), DAG, Subtarget); in LowerOperation()
10735 case ISD::BITCAST: in ReplaceNodeResults()
14090 if (VMov->getOpcode() == ISD::BITCAST) in PerformSUBCombine()
14176 if (And->getOpcode() == ISD::BITCAST) in PerformMVEVMULLCombine()
14181 if (Mask->getOpcode() == ISD::BITCAST) in PerformMVEVMULLCombine()
14438 DAG.getNode(ISD::BITCAST, dl, VbicVT, N->getOperand(0)); in PerformANDCombine()
14440 return DAG.getNode(ISD::BITCAST, dl, VT, Vbic); in PerformANDCombine()
14734 DAG.getNode(ISD::BITCAST, dl, VorrVT, N->getOperand(0)); in PerformORCombine()
14736 return DAG.getNode(ISD::BITCAST, dl, VT, Vorr); in PerformORCombine()
15099 bool BVSwap = BV.getOpcode() == ISD::BITCAST; in PerformVMOVRRDCombine()
15101 (BV.getOpcode() == ISD::BITCAST || in PerformVMOVRRDCombine()
15104 BVSwap = BV.getOpcode() == ISD::BITCAST; in PerformVMOVRRDCombine()
15149 if (Op0.getOpcode() == ISD::BITCAST) in PerformVMOVDRRCombine()
15151 if (Op1.getOpcode() == ISD::BITCAST) in PerformVMOVDRRCombine()
15156 return DAG.getNode(ISD::BITCAST, SDLoc(N), in PerformVMOVDRRCombine()
15177 if (Op0->getOpcode() == ISD::BITCAST) { in PerformVMOVhrCombine()
15291 SDValue V = DAG.getNode(ISD::BITCAST, dl, MVT::f64, N->getOperand(i)); in PerformBUILD_VECTORCombine()
15298 return DAG.getNode(ISD::BITCAST, dl, VT, BV); in PerformBUILD_VECTORCombine()
15328 if (Use->getOpcode() != ISD::BITCAST || in PerformARMBUILD_VECTORCombine()
15342 if (Elt->getOpcode() == ISD::BITCAST) { in PerformARMBUILD_VECTORCombine()
15375 if (V.getOpcode() == ISD::BITCAST && in PerformARMBUILD_VECTORCombine()
15380 V = DAG.getNode(ISD::BITCAST, SDLoc(V), MVT::i32, V); in PerformARMBUILD_VECTORCombine()
15387 Vec = DAG.getNode(ISD::BITCAST, dl, VT, Vec); in PerformARMBUILD_VECTORCombine()
15435 return DAG.getNode(ISD::BITCAST, dl, VT, Op); in PerformVECTOR_REG_CASTCombine()
15498 SDValue Vec = DAG.getNode(ISD::BITCAST, dl, FloatVT, N->getOperand(0)); in PerformInsertEltCombine()
15499 SDValue V = DAG.getNode(ISD::BITCAST, dl, MVT::f64, N->getOperand(1)); in PerformInsertEltCombine()
15505 return DAG.getNode(ISD::BITCAST, dl, VT, InsElt); in PerformInsertEltCombine()
15522 if (Ext.getOpcode() == ISD::BITCAST && in PerformExtractEltToVMOVRRD()
15556 OtherExt->use_begin()->getOpcode() != ISD::BITCAST || in PerformExtractEltToVMOVRRD()
15589 return DCI.DAG.getNode(ISD::BITCAST, dl, VT, X); in PerformExtractEltCombine()
15591 while (X.getValueType() != VT && X->getOpcode() == ISD::BITCAST) in PerformExtractEltCombine()
15607 Op0.getOpcode() == ISD::BITCAST && in PerformExtractEltCombine()
16062 StVal = DAG.getNode(ISD::BITCAST, dl, AlignedVecTy, StVal); in TryCombineBaseUpdate()
16078 LdVal = DAG.getNode(ISD::BITCAST, dl, VecTy, LdVal); in TryCombineBaseUpdate()
16479 while (Op.getOpcode() == ISD::BITCAST) in PerformVDUPLANECombine()
16494 return DCI.DAG.getNode(ISD::BITCAST, SDLoc(N), VT, Op); in PerformVDUPLANECombine()
16508 DAG.getNode(ISD::BITCAST, dl, MVT::i32, Op)); in PerformVDUPCombine()
16583 SDValue WideVec = DAG.getNode(ISD::BITCAST, DL, WideVecVT, StVal); in PerformTruncatingStoreCombine()
16613 SDValue ShuffWide = DAG.getNode(ISD::BITCAST, DL, StoreVecVT, Shuff); in PerformTruncatingStoreCombine()
16866 SDValue Vec = DAG.getNode(ISD::BITCAST, dl, FloatVT, IntVec); in PerformSTORECombine()
16870 SDValue V = DAG.getNode(ISD::BITCAST, dl, MVT::i64, ExtElt); in PerformSTORECombine()
16961 if (Op.getOpcode() != ISD::BITCAST || in PerformFAddVSelectCombine()
18659 (Op.getOpcode() == ISD::BITCAST && in PerformMVETruncCombine()
18959 case ISD::BITCAST: in PerformDAGCombine()