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Searched refs:ArgLocs (Results 1 – 25 of 42) sorted by relevance

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/freebsd/contrib/llvm-project/llvm/lib/Target/Mips/
H A DMipsCallLowering.cpp336 SmallVector<CCValAssign, 16> ArgLocs; in lowerReturn() local
339 MipsCCState CCInfo(F.getCallingConv(), F.isVarArg(), MF, ArgLocs, in lowerReturn()
350 if (!handleAssignments(RetHandler, RetInfos, CCInfo, ArgLocs, MIRBuilder)) in lowerReturn()
388 SmallVector<CCValAssign, 16> ArgLocs; in lowerFormalArguments() local
389 MipsCCState CCInfo(F.getCallingConv(), F.isVarArg(), MF, ArgLocs, in lowerFormalArguments()
405 if (!handleAssignments(Handler, ArgInfos, CCInfo, ArgLocs, MIRBuilder)) in lowerFormalArguments()
500 SmallVector<CCValAssign, 8> ArgLocs; in lowerCall() local
509 MipsCCState CCInfo(Info.CallConv, IsCalleeVarArg, MF, ArgLocs, in lowerCall()
524 if (!handleAssignments(ArgHandler, ArgInfos, CCInfo, ArgLocs, MIRBuilder)) in lowerCall()
557 SmallVector<CCValAssign, 8> ArgLocs; in lowerCall() local
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H A DMipsISelLowering.cpp3200 SmallVector<CCValAssign, 16> ArgLocs; in LowerCall() local
3202 CallConv, IsVarArg, DAG.getMachineFunction(), ArgLocs, *DAG.getContext(), in LowerCall()
3291 for (unsigned i = 0, e = ArgLocs.size(), OutIdx = 0; i != e; ++i, ++OutIdx) { in LowerCall()
3293 CCValAssign &VA = ArgLocs[i]; in LowerCall()
3337 Register LocRegHigh = ArgLocs[++i].getLocReg(); in LowerCall()
3660 SmallVector<CCValAssign, 16> ArgLocs; in LowerFormalArguments() local
3661 MipsCCState CCInfo(CallConv, IsVarArg, DAG.getMachineFunction(), ArgLocs, in LowerFormalArguments()
3678 for (unsigned i = 0, e = ArgLocs.size(), InsIdx = 0; i != e; ++i, ++InsIdx) { in LowerFormalArguments()
3679 CCValAssign &VA = ArgLocs[i]; in LowerFormalArguments()
3726 CCValAssign &NextVA = ArgLocs[++i]; in LowerFormalArguments()
[all …]
H A DMipsFastISel.cpp1134 SmallVector<CCValAssign, 16> ArgLocs; in processCallArgs() local
1135 CCState CCInfo(CC, false, *FuncInfo.MF, ArgLocs, *Context); in processCallArgs()
1146 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) { in processCallArgs()
1147 CCValAssign &VA = ArgLocs[i]; in processCallArgs()
/freebsd/contrib/llvm-project/llvm/lib/Target/X86/
H A DX86ISelLoweringCall.cpp1455 static bool isSortedByValueNo(ArrayRef<CCValAssign> ArgLocs) { in isSortedByValueNo() argument
1457 ArgLocs, [](const CCValAssign &A, const CCValAssign &B) -> bool { in isSortedByValueNo()
1691 SmallVector<CCValAssign, 16> ArgLocs; in LowerFormalArguments() local
1692 CCState CCInfo(CallConv, IsVarArg, MF, ArgLocs, *DAG.getContext()); in LowerFormalArguments()
1708 assert(isSortedByValueNo(ArgLocs) && in LowerFormalArguments()
1712 for (unsigned I = 0, InsIndex = 0, E = ArgLocs.size(); I != E; in LowerFormalArguments()
1715 CCValAssign &VA = ArgLocs[I]; in LowerFormalArguments()
1727 getv64i1Argument(VA, ArgLocs[++I], Chain, DAG, dl, Subtarget); in LowerFormalArguments()
2027 SmallVector<CCValAssign, 16> ArgLocs; in LowerCall() local
2028 CCState CCInfo(CallConv, isVarArg, MF, ArgLocs, *DAG.getContext()); in LowerCall()
[all …]
/freebsd/contrib/llvm-project/llvm/lib/Target/AMDGPU/
H A DAMDGPUCallLowering.cpp291 SmallVector<CCValAssign, 16> ArgLocs; in canLowerReturn() local
293 CCState CCInfo(CallConv, IsVarArg, MF, ArgLocs, in canLowerReturn()
521 SmallVector<CCValAssign, 16> ArgLocs; in lowerFormalArgumentsKernel() local
522 CCState CCInfo(F.getCallingConv(), F.isVarArg(), MF, ArgLocs, F.getContext()); in lowerFormalArgumentsKernel()
603 SmallVector<CCValAssign, 16> ArgLocs; in lowerFormalArguments() local
604 CCState CCInfo(CC, F.isVarArg(), MF, ArgLocs, F.getContext()); in lowerFormalArguments()
729 if (!handleAssignments(Handler, SplitArgs, CCInfo, ArgLocs, B)) in lowerFormalArguments()
1279 SmallVector<CCValAssign, 16> ArgLocs; in lowerTailCall() local
1280 CCState CCInfo(Info.CallConv, Info.IsVarArg, MF, ArgLocs, F.getContext()); in lowerTailCall()
1301 if (!handleAssignments(Handler, OutArgs, CCInfo, ArgLocs, MIRBuilder)) in lowerTailCall()
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/freebsd/contrib/llvm-project/llvm/lib/Target/ARC/
H A DARCISelLowering.cpp278 SmallVector<CCValAssign, 16> ArgLocs; in LowerCall() local
279 CCState CCInfo(CallConv, IsVarArg, DAG.getMachineFunction(), ArgLocs, in LowerCall()
301 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) { in LowerCall()
302 CCValAssign &VA = ArgLocs[i]; in LowerCall()
494 SmallVector<CCValAssign, 16> ArgLocs; in LowerCallArguments() local
495 CCState CCInfo(CallConv, IsVarArg, DAG.getMachineFunction(), ArgLocs, in LowerCallArguments()
517 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) { in LowerCallArguments()
518 CCValAssign &VA = ArgLocs[i]; in LowerCallArguments()
/freebsd/contrib/llvm-project/llvm/lib/Target/Xtensa/
H A DXtensaISelLowering.cpp218 SmallVector<CCValAssign, 16> ArgLocs; in LowerFormalArguments() local
219 CCState CCInfo(CallConv, IsVarArg, DAG.getMachineFunction(), ArgLocs, in LowerFormalArguments()
224 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) { in LowerFormalArguments()
225 CCValAssign &VA = ArgLocs[i]; in LowerFormalArguments()
316 SmallVector<CCValAssign, 16> ArgLocs; in LowerCall() local
317 CCState CCInfo(CallConv, IsVarArg, MF, ArgLocs, *DAG.getContext()); in LowerCall()
335 for (unsigned I = 0, E = ArgLocs.size(); I != E; ++I) { in LowerCall()
336 CCValAssign &VA = ArgLocs[I]; in LowerCall()
/freebsd/contrib/llvm-project/llvm/lib/Target/BPF/
H A DBPFISelLowering.cpp341 SmallVector<CCValAssign, 16> ArgLocs; in LowerFormalArguments() local
342 CCState CCInfo(CallConv, IsVarArg, MF, ArgLocs, *DAG.getContext()); in LowerFormalArguments()
346 for (size_t I = 0; I < ArgLocs.size(); ++I) { in LowerFormalArguments()
347 auto &VA = ArgLocs[I]; in LowerFormalArguments()
430 SmallVector<CCValAssign, 16> ArgLocs; in LowerCall() local
431 CCState CCInfo(CallConv, IsVarArg, MF, ArgLocs, *DAG.getContext()); in LowerCall()
454 for (size_t i = 0; i < std::min(ArgLocs.size(), MaxArgs); ++i) { in LowerCall()
455 CCValAssign &VA = ArgLocs[i]; in LowerCall()
/freebsd/contrib/llvm-project/llvm/lib/Target/M68k/
H A DM68kISelLowering.cpp574 SmallVector<CCValAssign, 16> ArgLocs; in LowerCall() local
578 M68kCCState CCInfo(ArgTypes, CallConv, IsVarArg, MF, ArgLocs, in LowerCall()
614 if (!ArgLocs.back().isMemLoc()) in LowerCall()
617 if (ArgLocs.back().getLocMemOffset() != 0) in LowerCall()
638 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) { in LowerCall()
645 CCValAssign &VA = ArgLocs[i]; in LowerCall()
723 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) { in LowerCall()
724 CCValAssign &VA = ArgLocs[i]; in LowerCall()
929 SmallVector<CCValAssign, 16> ArgLocs; in LowerFormalArguments() local
933 M68kCCState CCInfo(ArgTypes, CCID, IsVarArg, MF, ArgLocs, *DAG.getContext()); in LowerFormalArguments()
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/freebsd/contrib/llvm-project/llvm/lib/Target/MSP430/
H A DMSP430ISelLowering.cpp457 SmallVectorImpl<CCValAssign> &ArgLocs, in AnalyzeArguments() argument
628 SmallVector<CCValAssign, 16> ArgLocs; in LowerCCCArguments() local
629 CCState CCInfo(CallConv, isVarArg, DAG.getMachineFunction(), ArgLocs, in LowerCCCArguments()
631 AnalyzeArguments(CCInfo, ArgLocs, Ins); in LowerCCCArguments()
639 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) { in LowerCCCArguments()
640 CCValAssign &VA = ArgLocs[i]; in LowerCCCArguments()
707 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) { in LowerCCCArguments()
812 SmallVector<CCValAssign, 16> ArgLocs; in LowerCCCCallTo() local
813 CCState CCInfo(CallConv, isVarArg, DAG.getMachineFunction(), ArgLocs, in LowerCCCCallTo()
815 AnalyzeArguments(CCInfo, ArgLocs, Outs); in LowerCCCCallTo()
[all …]
/freebsd/contrib/llvm-project/llvm/lib/CodeGen/GlobalISel/
H A DCallLowering.cpp656 SmallVector<CCValAssign, 16> ArgLocs; in determineAndHandleAssignments() local
658 CCState CCInfo(CallConv, IsVarArg, MF, ArgLocs, F.getContext()); in determineAndHandleAssignments()
662 return handleAssignments(Handler, Args, CCInfo, ArgLocs, MIRBuilder, in determineAndHandleAssignments()
738 SmallVectorImpl<CCValAssign> &ArgLocs, in handleAssignments() argument
763 assert(j < ArgLocs.size() && "Skipped too many arg locs"); in handleAssignments()
764 CCValAssign &VA = ArgLocs[j]; in handleAssignments()
770 Args[i], ArrayRef(ArgLocs).slice(j), &Thunk); in handleAssignments()
819 assert((j + (NumParts - 1)) < ArgLocs.size() && in handleAssignments()
839 CCValAssign &VA = ArgLocs[j + Idx]; in handleAssignments()
/freebsd/contrib/llvm-project/llvm/lib/Target/Sparc/
H A DSparcISelLowering.cpp440 SmallVector<CCValAssign, 16> ArgLocs; in LowerFormalArguments_32() local
441 CCState CCInfo(CallConv, isVarArg, DAG.getMachineFunction(), ArgLocs, in LowerFormalArguments_32()
449 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i, ++InIdx) { in LowerFormalArguments_32()
450 CCValAssign &VA = ArgLocs[i]; in LowerFormalArguments_32()
473 CCValAssign &NextVA = ArgLocs[++i]; in LowerFormalArguments_32()
633 SmallVector<CCValAssign, 16> ArgLocs; in LowerFormalArguments_64() local
634 CCState CCInfo(CallConv, IsVarArg, DAG.getMachineFunction(), ArgLocs, in LowerFormalArguments_64()
641 for (const CCValAssign &VA : ArgLocs) { in LowerFormalArguments_64()
836 SmallVector<CCValAssign, 16> ArgLocs; in LowerCall_32() local
837 CCState CCInfo(CallConv, isVarArg, DAG.getMachineFunction(), ArgLocs, in LowerCall_32()
[all …]
/freebsd/contrib/llvm-project/llvm/lib/Target/AArch64/GISel/
H A DAArch64CallLowering.cpp478 SmallVector<CCValAssign, 16> ArgLocs; in canLowerReturn() local
480 CCState CCInfo(CallConv, IsVarArg, MF, ArgLocs, in canLowerReturn()
503 SmallVector<CCValAssign, 16> ArgLocs; in handleMustTailForwardedRegisters() local
504 CCState CCInfo(F.getCallingConv(), /*IsVarArg=*/true, MF, ArgLocs, in handleMustTailForwardedRegisters()
710 SmallVector<CCValAssign, 16> ArgLocs; in lowerFormalArguments() local
711 CCState CCInfo(F.getCallingConv(), F.isVarArg(), MF, ArgLocs, F.getContext()); in lowerFormalArguments()
713 !handleAssignments(Handler, SplitArgs, CCInfo, ArgLocs, MIRBuilder)) in lowerFormalArguments()
/freebsd/contrib/llvm-project/llvm/lib/Target/CSKY/
H A DCSKYISelLowering.cpp346 SmallVector<CCValAssign, 16> ArgLocs; in LowerFormalArguments() local
347 CCState CCInfo(CallConv, IsVarArg, MF, ArgLocs, *DAG.getContext()); in LowerFormalArguments()
351 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) { in LowerFormalArguments()
352 CCValAssign &VA = ArgLocs[i]; in LowerFormalArguments()
523 SmallVector<CCValAssign, 16> ArgLocs; in LowerCall() local
524 CCState ArgCCInfo(CallConv, IsVarArg, MF, ArgLocs, *DAG.getContext()); in LowerCall()
571 for (unsigned i = 0, j = 0, e = ArgLocs.size(); i != e; ++i) { in LowerCall()
572 CCValAssign &VA = ArgLocs[i]; in LowerCall()
/freebsd/contrib/llvm-project/llvm/include/llvm/CodeGen/GlobalISel/
H A DCallLowering.h423 CCState &CCState, SmallVectorImpl<CCValAssign> &ArgLocs,
432 const SmallVectorImpl<CCValAssign> &ArgLocs,
/freebsd/contrib/llvm-project/llvm/lib/Target/Lanai/
H A DLanaiISelLowering.cpp445 SmallVector<CCValAssign, 16> ArgLocs; in LowerCCCArguments() local
446 CCState CCInfo(CallConv, IsVarArg, DAG.getMachineFunction(), ArgLocs, in LowerCCCArguments()
454 for (const CCValAssign &VA : ArgLocs) { in LowerCCCArguments()
609 SmallVector<CCValAssign, 16> ArgLocs; in LowerCCCCallTo() local
610 CCState CCInfo(CallConv, IsVarArg, DAG.getMachineFunction(), ArgLocs, in LowerCCCCallTo()
663 for (unsigned I = 0, J = 0, E = ArgLocs.size(); I != E; ++I) { in LowerCCCCallTo()
664 CCValAssign &VA = ArgLocs[I]; in LowerCCCCallTo()
/freebsd/contrib/llvm-project/llvm/lib/Target/RISCV/GISel/
H A DRISCVCallLowering.cpp551 SmallVector<CCValAssign, 16> ArgLocs; in lowerFormalArguments() local
552 CCState CCInfo(CC, F.isVarArg(), MIRBuilder.getMF(), ArgLocs, F.getContext()); in lowerFormalArguments()
554 !handleAssignments(Handler, SplitArgInfos, CCInfo, ArgLocs, MIRBuilder)) in lowerFormalArguments()
/freebsd/contrib/llvm-project/llvm/lib/Target/AVR/
H A DAVRISelLowering.cpp1227 SmallVectorImpl<CCValAssign> &ArgLocs, in analyzeArguments() argument
1376 SmallVector<CCValAssign, 16> ArgLocs; in LowerFormalArguments() local
1377 CCState CCInfo(CallConv, isVarArg, DAG.getMachineFunction(), ArgLocs, in LowerFormalArguments()
1384 analyzeArguments(nullptr, &MF.getFunction(), &DL, Ins, ArgLocs, CCInfo, in LowerFormalArguments()
1389 for (CCValAssign &VA : ArgLocs) { in LowerFormalArguments()
1486 SmallVector<CCValAssign, 16> ArgLocs; in LowerCall() local
1487 CCState CCInfo(CallConv, isVarArg, DAG.getMachineFunction(), ArgLocs, in LowerCall()
1510 analyzeArguments(&CLI, F, &DAG.getDataLayout(), Outs, ArgLocs, CCInfo, in LowerCall()
1524 for (AI = 0, AE = ArgLocs.size(); AI != AE; ++AI) { in LowerCall()
1525 CCValAssign &VA = ArgLocs[AI]; in LowerCall()
[all …]
/freebsd/contrib/llvm-project/llvm/lib/Target/XCore/
H A DXCoreISelLowering.cpp1023 SmallVector<CCValAssign, 16> ArgLocs; in LowerCCCCallTo() local
1024 CCState CCInfo(CallConv, isVarArg, DAG.getMachineFunction(), ArgLocs, in LowerCCCCallTo()
1049 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) { in LowerCCCCallTo()
1050 CCValAssign &VA = ArgLocs[i]; in LowerCCCCallTo()
1176 SmallVector<CCValAssign, 16> ArgLocs; in LowerCCCArguments() local
1177 CCState CCInfo(CallConv, isVarArg, DAG.getMachineFunction(), ArgLocs, in LowerCCCArguments()
1201 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) { in LowerCCCArguments()
1203 CCValAssign &VA = ArgLocs[i]; in LowerCCCArguments()
/freebsd/contrib/llvm-project/llvm/lib/Target/ARM/
H A DARMFastISel.cpp1883 SmallVector<CCValAssign, 16> ArgLocs; in ProcessCallArgs() local
1884 CCState CCInfo(CC, isVarArg, *FuncInfo.MF, ArgLocs, *Context); in ProcessCallArgs()
1890 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) { in ProcessCallArgs()
1891 CCValAssign &VA = ArgLocs[i]; in ProcessCallArgs()
1905 !VA.isRegLoc() || !ArgLocs[++i].isRegLoc()) in ProcessCallArgs()
1940 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) { in ProcessCallArgs()
1941 CCValAssign &VA = ArgLocs[i]; in ProcessCallArgs()
1989 CCValAssign &NextVA = ArgLocs[++i]; in ProcessCallArgs()
/freebsd/contrib/llvm-project/llvm/lib/Target/LoongArch/
H A DLoongArchISelLowering.h334 const SmallVectorImpl<CCValAssign> &ArgLocs) const;
H A DLoongArchISelLowering.cpp5075 SmallVector<CCValAssign> ArgLocs; in LowerFormalArguments() local
5076 CCState CCInfo(CallConv, IsVarArg, MF, ArgLocs, *DAG.getContext()); in LowerFormalArguments()
5083 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) { in LowerFormalArguments()
5084 CCValAssign &VA = ArgLocs[i]; in LowerFormalArguments()
5099 CCValAssign &PartVA = ArgLocs[i + 1]; in LowerFormalArguments()
5218 const SmallVectorImpl<CCValAssign> &ArgLocs) const { in isEligibleForTailCallOptimization()
5230 for (auto &VA : ArgLocs) in isEligibleForTailCallOptimization()
5283 SmallVector<CCValAssign> ArgLocs; in LowerCall() local
5284 CCState ArgCCInfo(CallConv, IsVarArg, MF, ArgLocs, *DAG.getContext()); in LowerCall()
5293 IsTailCall = isEligibleForTailCallOptimization(ArgCCInfo, CLI, MF, ArgLocs); in LowerCall()
[all …]
/freebsd/contrib/llvm-project/llvm/lib/Target/VE/
H A DVEISelLowering.cpp453 SmallVector<CCValAssign, 16> ArgLocs; in LowerFormalArguments() local
454 CCState CCInfo(CallConv, IsVarArg, DAG.getMachineFunction(), ArgLocs, in LowerFormalArguments()
462 for (const CCValAssign &VA : ArgLocs) { in LowerFormalArguments()
546 unsigned ArgOffset = ArgLocs.size() * 8; in LowerFormalArguments()
596 SmallVector<CCValAssign, 16> ArgLocs; in LowerCall() local
597 CCState CCInfo(CLI.CallConv, CLI.IsVarArg, DAG.getMachineFunction(), ArgLocs, in LowerCall()
684 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) { in LowerCall()
685 CCValAssign &VA = ArgLocs[i]; in LowerCall()
/freebsd/contrib/llvm-project/llvm/lib/Target/PowerPC/
H A DPPCISelLowering.cpp4273 SmallVector<CCValAssign, 16> ArgLocs; in LowerFormalArguments_32SVR4() local
4274 PPCCCState CCInfo(CallConv, isVarArg, DAG.getMachineFunction(), ArgLocs, in LowerFormalArguments_32SVR4()
4286 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) { in LowerFormalArguments_32SVR4()
4287 CCValAssign &VA = ArgLocs[i]; in LowerFormalArguments_32SVR4()
4338 Register RegHi = MF.addLiveIn(ArgLocs[++i].getLocReg(), RC); in LowerFormalArguments_32SVR4()
6006 SmallVector<CCValAssign, 16> ArgLocs; in LowerCall_32SVR4() local
6007 PPCCCState CCInfo(CallConv, IsVarArg, MF, ArgLocs, *DAG.getContext()); in LowerCall_32SVR4()
6090 for (unsigned i = 0, RealArgIdx = 0, j = 0, e = ArgLocs.size(); in LowerCall_32SVR4()
6093 CCValAssign &VA = ArgLocs[i]; in LowerCall_32SVR4()
6151 RegsToPass.push_back(std::make_pair(ArgLocs[++i].getLocReg(), in LowerCall_32SVR4()
[all …]
/freebsd/contrib/llvm-project/llvm/lib/Target/Hexagon/
H A DHexagonISelLowering.cpp429 SmallVector<CCValAssign, 16> ArgLocs; in LowerCall() local
430 HexagonCCState CCInfo(CallConv, TreatAsVarArg, MF, ArgLocs, *DAG.getContext(), in LowerCall()
445 for (const CCValAssign &VA : ArgLocs) { in LowerCall()
467 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) { in LowerCall()
468 CCValAssign &VA = ArgLocs[i]; in LowerCall()
804 SmallVector<CCValAssign, 16> ArgLocs; in LowerFormalArguments() local
805 HexagonCCState CCInfo(CallConv, TreatAsVarArg, MF, ArgLocs, in LowerFormalArguments()
841 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) { in LowerFormalArguments()
842 CCValAssign &VA = ArgLocs[i]; in LowerFormalArguments()

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