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Searched refs:AVX512 (Results 1 – 17 of 17) sorted by relevance

/freebsd/contrib/llvm-project/llvm/lib/Target/X86/
H A DX86Subtarget.h55 NoSSE, SSE1, SSE2, SSE3, SSSE3, SSE41, SSE42, AVX, AVX2, AVX512 enumerator
201 bool hasAVX512() const { return X86SSELevel >= AVX512; } in hasAVX512()
H A DX86InstrFormats.td271 // The scaling factor for AVX512's compressed displacement is either
275 // Possible values are: 0 (non-AVX512 inst), 1, 2, 4, 8, 16, 32 and 64.
H A DX86.td118 def FeatureAVX512 : SubtargetFeature<"avx512f", "X86SSELevel", "AVX512",
207 "Promote selected AES instructions to AVX512/AVX registers",
588 // Prefer lowering shuffles on AVX512 targets (e.g. Skylake Server) to
705 "Prefer AVX512 mask registers over PTEST/MOVMSK">;
970 // Skylake-AVX512
H A DX86InstrAVX512.td1 //===-- X86InstrAVX512.td - AVX512 Instruction Set ---------*- tablegen -*-===//
9 // This file describes the X86 AVX512 instruction set, defining the
33 def NAME: AVX512<O, F, Outs, Ins,
40 def NAME#k: AVX512<O, F, Outs, MaskingIns,
55 def NAME#kz: AVX512<O, F, Outs, ZeroMaskingIns,
220 def NAME: AVX512<O, F, Outs, Ins,
225 def NAME#k: AVX512<O, F, Outs, MaskingIns,
1935 // avx512_cmp_scalar - AVX512 CMPSS and CMPSD
2460 def rr : AVX512<opc, MRMSrcReg, (outs _.KRC:$dst),
2466 def rrk : AVX512<opc, MRMSrcReg, (outs _.KRC:$dst),
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H A DX86InstrUtils.td59 // Specify AVX512 8-bit compressed displacement encoding based on the vector
498 // SI - SSE 1 & 2 scalar intrinsics - vex form available on AVX512
514 // SIi8 - SSE 1 & 2 scalar instructions - vex form available on AVX512
839 class AVX512<bits<8> o, Format F, dag outs, dag ins, string asm,
H A DX86ScheduleZnver4.td302 // AVX512 Opmask pipelines
/freebsd/contrib/llvm-project/llvm/lib/Analysis/
H A DVFABIDemangling.cpp
/freebsd/sys/contrib/libsodium/
H A Dconfigure.ac333 AC_MSG_CHECKING(for a broken clang + AVX512 combination)
336 #error Not a broken clang + AVX512 combination
339 [AC_MSG_RESULT(yes - disabling AVX512 optimizations)
H A DChangeLog82 - An AVX512 optimized implementation of Argon2 has been added (written
/freebsd/contrib/llvm-project/clang/lib/CodeGen/
H A DTargetInfo.h561 AVX512, enumerator
H A DCodeGenModule.cpp267 X86AVXABILevel AVXLevel = (ABI == "avx512" ? X86AVXABILevel::AVX512 in createTargetCodeGenInfo()
/freebsd/sys/contrib/openzfs/module/
H A DKbuild.in501 # aware of x86 EVEX prefix instructions used for AVX512.
/freebsd/crypto/openssl/
H A DINSTALL.md1796 | AVX512 | 2.25 | 2.11.8 | 3.6 (*) |
1802 (*) Even though AVX512 support was implemented in llvm 3.6, prior to version 7.0
H A DCHANGES.md230 x86_64 processors supporting the AVX512-IFMA instructions.
/freebsd/contrib/llvm-project/clang/include/clang/Basic/
H A DBuiltinsX86.def860 // AVX-VNNI and AVX512-VNNI
1727 // AVX512 fp16 intrinsics
/freebsd/contrib/llvm-project/clang/lib/CodeGen/Targets/
H A DX86.cpp1197 case X86AVXABILevel::AVX512: in getNativeVectorSizeForAVXABI()
/freebsd/contrib/llvm-project/llvm/include/llvm/IR/
H A DIntrinsicsX86.td2769 // AVX512
4051 // AVX512 gather/scatter intrinsics that use vXi1 masks.