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Searched refs:ATA_INL (Results 1 – 18 of 18) sorted by relevance

/freebsd/sys/dev/ahci/
H A Dahci.c116 ATA_OUTL(ctlr->r_mem, AHCI_IS, ATA_INL(ctlr->r_mem, AHCI_IS)); in ahci_ctlr_setup()
119 ATA_OUTL(ctlr->r_mem, AHCI_CCCP, ATA_INL(ctlr->r_mem, AHCI_PI)); in ahci_ctlr_setup()
124 ctlr->cccv = (ATA_INL(ctlr->r_mem, AHCI_CCCC) & in ahci_ctlr_setup()
134 ATA_INL(ctlr->r_mem, AHCI_GHC) | AHCI_GHC_IE); in ahci_ctlr_setup()
146 if ((ATA_INL(ctlr->r_mem, AHCI_VS) >= 0x00010200) && in ahci_ctlr_reset()
147 (ATA_INL(ctlr->r_mem, AHCI_CAP2) & AHCI_CAP2_BOH) && in ahci_ctlr_reset()
148 ((v = ATA_INL(ctlr->r_mem, AHCI_BOHC)) & AHCI_BOHC_OOS) == 0) { in ahci_ctlr_reset()
155 v = ATA_INL(ctlr->r_mem, AHCI_BOHC); in ahci_ctlr_reset()
169 if ((ATA_INL(ctlr->r_mem, AHCI_GHC) & AHCI_GHC_HR) == 0) in ahci_ctlr_reset()
223 version = ATA_INL(ctlr->r_mem, AHCI_VS); in ahci_attach()
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H A Dahci_pci.c551 vscap = ATA_INL(ctlr->r_mem, AHCI_VSCAP); in ahci_pci_attach()
553 uint32_t cap = ATA_INL(ctlr->r_mem, 0x800); /* Intel's REMAP CAP */ in ahci_pci_attach()
566 (ATA_INL(ctlr->r_mem, 0x880 + i * 0x80) == in ahci_pci_attach()
643 caps = ATA_INL(ctlr->r_mem, AHCI_CAP); in ahci_pci_attach()
644 pi = ATA_INL(ctlr->r_mem, AHCI_PI); in ahci_pci_attach()
720 ATA_INL(ctlr->r_mem, AHCI_GHC) & (~AHCI_GHC_IE)); in ahci_pci_suspend()
H A Dahci_fsl_fdt.c213 val = ATA_INL(ctrl->r_ecc, AHCI_FSL_REG_ECC); in ahci_fsl_fdt_ecc_init()
226 val = ATA_INL(ctrl->r_ecc, AHCI_FSL_REG_ECC); in ahci_fsl_fdt_ecc_init()
H A Dahci.h557 #define ATA_INL(res, offset) \ macro
/freebsd/sys/arm/allwinner/
H A Da10_ahci.c129 uint32_t val = ATA_INL(m, off); in ahci_set()
138 uint32_t val = ATA_INL(m, off); in ahci_clr()
147 uint32_t val = ATA_INL(m, off); in ahci_mask_set()
231 val = ATA_INL(ctlr->r_mem, AHCI_PHYCS0R); in ahci_a10_phy_reset()
245 val = ATA_INL(ctlr->r_mem, AHCI_PHYCS2R); in ahci_a10_phy_reset()
273 reg = ATA_INL(ch->r_mem, AHCI_P0DMACR); in ahci_a10_ch_start()
/freebsd/sys/powerpc/mpc85xx/
H A Dfsl_sata.c306 #define ATA_INL(res, offset) \ macro
457 while (((rval = ATA_INL(ch->r_mem, off)) & mask) != val) { in fsl_sata_wait_register()
475 r = ATA_INL(ch->r_mem, FSL_SATA_P_HCTRL); in fsl_sata_init()
487 r = ATA_INL(ch->r_mem, FSL_SATA_P_PCC); in fsl_sata_init()
501 r = ATA_INL(ch->r_mem, FSL_SATA_P_HCTRL); in fsl_sata_deinit()
510 r = ATA_INL(ch->r_mem, FSL_SATA_P_HCTRL); in fsl_sata_deinit()
679 u_int32_t status = ATA_INL(ch->r_mem, FSL_SATA_P_SSTS); in fsl_sata_phy_check_events()
747 istatus = ATA_INL(ch->r_mem, FSL_SATA_P_HSTS) & 0x7ffff; in fsl_sata_intr()
778 work = ATA_INL(ch->r_mem, FSL_SATA_P_PCC) & ~FSL_SATA_PCC_LPB_EN; in fsl_sata_pm()
795 ok = ATA_INL(ch->r_mem, FSL_SATA_P_CCR); in fsl_sata_intr_main()
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/freebsd/sys/arm/freescale/imx/
H A Dimx6_ahci.c76 v = ATA_INL(sc->r_mem, SATA_P0PHYCR); in imx6_ahci_phy_ctrl()
85 v = ATA_INL(sc->r_mem, SATA_P0PHYSR); in imx6_ahci_phy_ctrl()
199 v = ATA_INL(sc->r_mem, SATA_P0PHYSR); in imx6_ahci_phy_read()
307 v = ATA_INL(ctlr->r_mem, AHCI_CAP); in imx6_ahci_attach()
311 v = ATA_INL(ctlr->r_mem, AHCI_PI); in imx6_ahci_attach()
/freebsd/sys/dev/mvs/
H A Dmvs.c261 reg = ATA_INL(ch->r_mem, SATA_FISC); in mvs_ch_init()
264 reg = ATA_INL(ch->r_mem, SATA_FISIM); in mvs_ch_init()
502 while (ATA_INL(ch->r_mem, EDMA_CMD) & EDMA_CMD_EENEDMA) { in mvs_set_edma_mode()
540 fcfg = ATA_INL(ch->r_mem, SATA_FISC); in mvs_set_edma_mode()
541 ltm = ATA_INL(ch->r_mem, SATA_LTM); in mvs_set_edma_mode()
542 hc = ATA_INL(ch->r_mem, EDMA_HC); in mvs_set_edma_mode()
564 unkn = ATA_INL(ch->r_mem, EDMA_UNKN_RESD); in mvs_set_edma_mode()
598 u_int32_t status = ATA_INL(ch->r_mem, SATA_SS); in mvs_phy_check_events()
631 fis = ATA_INL(ch->r_mem, SATA_FISDW0); in mvs_notify_events()
667 work = ATA_INL(ch->r_mem, SATA_SC); in mvs_ch_pm()
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H A Dmvs_soc.c143 if (ATA_INL(ctlr->r_mem, PORT_BASE(0) + SATA_PHYCFG_OFS) != 0) in mvs_attach()
307 ic = ATA_INL(ctlr->r_mem, CHIP_SOC_MIC); in mvs_intr()
H A Dmvs.h637 #define ATA_INL(res, offset) \ macro
H A Dmvs_pci.c338 ic = ATA_INL(ctlr->r_mem, CHIP_MIC); in mvs_intr()
/freebsd/sys/dev/siis/
H A Dsiis.c155 ctlr->gctl = ATA_INL(ctlr->r_gmem, SIIS_GCTL); in siis_attach()
302 is = ATA_INL(ctlr->r_gmem, SIIS_IS); in siis_intr()
782 status = ATA_INL(ch->r_mem, SIIS_P_SNTF); in siis_notify_events()
812 u_int32_t status = ATA_INL(ch->r_mem, SIIS_P_SSTS); in siis_phy_check_events()
858 sstatus = ATA_INL(ch->r_mem, SIIS_P_SS); in siis_ch_intr()
869 istatus = ATA_INL(ch->r_mem, SIIS_P_IS) & in siis_ch_intr()
880 estatus = ATA_INL(ch->r_mem, SIIS_P_CMDERR); in siis_ch_intr()
881 ctx = ATA_INL(ch->r_mem, SIIS_P_CTX); in siis_ch_intr()
1193 __func__, ATA_INL(ch->r_mem, SIIS_P_IS), in siis_timeout()
1194 ATA_INL(ch->r_mem, SIIS_P_SS), ch->rslots, in siis_timeout()
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H A Dsiis.h433 #define ATA_INL(res, offset) \ macro
/freebsd/sys/dev/ata/chipsets/
H A Data-siliconimage.c314 (ATA_INL(ctlr->r_res2, 0x10 + offset0) & 0x00000010)) in ata_sii_status()
317 if (ATA_INL(ctlr->r_res2, 0xa0 + offset1) & 0x00000800) in ata_sii_status()
332 val = ATA_INL(ctlr->r_res2, 0x14c + offset); in ata_sii_reset()
H A Data-nvidia.c225 ATA_INL(ctlr->r_res2, 0x0400) & 0xfffffff9); in ata_nvidia_chipinit()
291 istatus = ATA_INL(ctlr->r_res2, offset); in ata_nvidia_status()
H A Data-serverworks.c109 if (!(ATA_INL(ctlr->r_res2, 0x1f80) & (1 << ch->unit))) in ata_serverworks_status()
217 ATA_INL(ctlr->r_res2, ch_offset + 0x80) & ~0x00040000); in ata_serverworks_ch_attach()
H A Data-intel.c278 ATA_INL(ctlr->r_res2, 0x0C) | 0xf); in ata_intel_chipinit()
627 *result = ATA_INL(ctlr->r_res2, offset + reg); in ata_intel_sata_ahci_read()
866 ATA_INL(ctlr->r_res2, 0x04) | (0x01 << (ch->unit << 3))); in ata_intel_31244_ch_attach()
/freebsd/sys/dev/ata/
H A Data-all.h509 #define ATA_INL(res, offset) \ macro
546 ATA_INL(ch->r_io[idx].res, ch->r_io[idx].offset)