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Searched refs:ALU (Results 1 – 25 of 77) sorted by relevance

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/freebsd/contrib/llvm-project/llvm/lib/Target/Mips/
H A DMipsSchedule.td12 def ALU : FuncUnit;
388 def MipsGenericItineraries : ProcessorItineraries<[ALU, IMULDIV], [], [
389 InstrItinData<IIM16Alu , [InstrStage<1, [ALU]>]>,
390 InstrItinData<II_ADDI , [InstrStage<1, [ALU]>]>,
391 InstrItinData<II_ADDIU , [InstrStage<1, [ALU]>]>,
392 InstrItinData<II_ADDIUPC , [InstrStage<1, [ALU]>]>,
393 InstrItinData<II_ADD , [InstrStage<1, [ALU]>]>,
394 InstrItinData<II_ADDU , [InstrStage<1, [ALU]>]>,
395 InstrItinData<II_AUI , [InstrStage<1, [ALU]>]>,
396 InstrItinData<II_AND , [InstrStage<1, [ALU]>]>,
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/freebsd/contrib/llvm-project/llvm/lib/Target/PowerPC/
H A DP9InstrResources.td25 // - Four ALU (Fixed Point Arithmetic) units. One on each slice. P9_ALU_*
33 // Two cycle ALU vector operation that uses an entire superslice.
34 // Uses both ALU units (the even ALUE and odd ALUO units), two pipelines
86 // Restricted Dispatch ALU operation for 3 cycles. The operation runs on a
104 // Standard Dispatch ALU operation for 3 cycles. Only one slice used.
121 // Standard Dispatch ALU operation for 2 cycles. Only one slice used.
176 // Restricted Dispatch ALU operation for 2 cycles. The operation runs on a
205 // Three cycle ALU vector operation that uses an entire superslice.
206 // Uses both ALU units (the even ALUE and odd ALUO units), two pipelines
452 // 7 cycle Restricted DP operation and one 3 cycle ALU operation.
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H A DP10InstrResources.td21 // 22 Cycles Binary Floating Point operations, and 3 Cycles ALU operations, 2 input operands
41 // 26 Cycles Binary Floating Point operations, and 3 Cycles ALU operations, 1 input operands
62 // 27 Cycles Binary Floating Point operations, and 3 Cycles ALU operations, 2 input operands
77 // 36 Cycles Binary Floating Point operations, and 3 Cycles ALU operations, 1 input operands
257 // 7 Cycles Binary Floating Point operations, and 3 Cycles ALU operations, 2 input operands
269 // 7 Cycles Binary Floating Point operations, and 3 Cycles ALU operations, 1 input operands
296 // 7 Cycles Binary Floating Point operations, and 3 Cycles ALU operations, 3 input operands
474 // 20 Cycles Scalar Fixed-Point Divide operations, and 3 Cycles ALU operations, 2 input operands
497 // 25 Cycles Scalar Fixed-Point Divide operations, and 3 Cycles ALU operations, 2 input operands
528 // 41 Cycles Scalar Fixed-Point Divide operations, and 3 Cycles ALU operations, 2 input operands
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H A DPPCScheduleP9.td88 // Four ALU (Fixed Point Arithmetic) units in total. Two even, two Odd.
89 def ALU : ProcResource<4>;
91 //Even ALU pipelines
92 let Super = ALU;
95 //Odd ALU pipelines
96 let Super = ALU;
190 // ALU Units
191 // An ALU may take either 2 or 3 cycles to complete the operation.
192 // However, the ALU unit is only ever busy for 1 cycle at a time and may
194 def P9_ALU_2C : SchedWriteRes<[ALU]> {
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/freebsd/contrib/llvm-project/llvm/lib/Target/AMDGPU/
H A DR600Schedule.td10 // slots ALU.X, ALU.Y, ALU.Z, ALU.W, and TRANS. For cayman cards, the TRANS
H A DR600Processors.td19 "Older version of ALU instructions encoding"
/freebsd/contrib/llvm-project/llvm/lib/Target/RISCV/
H A DRISCVSchedSyntacoreSCR3.td36 multiclass SCR3_IntALU<ProcResourceKind ALU> {
37 def : WriteRes<WriteIALU, [ALU]>;
38 def : WriteRes<WriteIALU32, [ALU]>;
39 def : WriteRes<WriteShiftImm, [ALU]>;
40 def : WriteRes<WriteShiftImm32, [ALU]>;
41 def : WriteRes<WriteShiftReg, [ALU]>;
42 def : WriteRes<WriteShiftReg32, [ALU]>;
H A DRISCVSchedRocket.td33 def RocketUnitALU : ProcResource<1>; // Int ALU
38 def RocketUnitFPALU : ProcResource<1>; // FP ALU
H A DRISCVSchedule.td10 def WriteIALU : SchedWrite; // 32 or 64-bit integer ALU operations
11 def WriteIALU32 : SchedWrite; // 32-bit integer ALU operations on RV64I
133 def ReadIALU32 : SchedRead; // 32-bit integer ALU operations on RV64I
/freebsd/contrib/llvm-project/llvm/lib/Target/AArch64/
H A DAArch64Schedule.td24 def WriteI : SchedWrite; // ALU
25 def WriteISReg : SchedWrite; // ALU of Shifted-Reg
26 def WriteIEReg : SchedWrite; // ALU of Extended-Reg
27 def ReadI : SchedRead; // ALU
28 def ReadISReg : SchedRead; // ALU of Shifted-Reg
29 def ReadIEReg : SchedRead; // ALU of Extended-Reg
H A DAArch64SchedA55.td44 def CortexA55UnitALU : ProcResource<2> { let BufferSize = 0; } // Int ALU
51 // The FP DIV/SQRT instructions execute totally differently from the FP ALU
54 def CortexA55UnitFPALU : ProcResource<2> { let BufferSize = 0; } // FP ALU
67 def : WriteRes<WriteI, [CortexA55UnitALU]> { let Latency = 3; } // ALU
68 def : WriteRes<WriteISReg, [CortexA55UnitALU]> { let Latency = 3; } // ALU of Shifted-Reg
69 def : WriteRes<WriteIEReg, [CortexA55UnitALU]> { let Latency = 3; } // ALU of Extended-Reg
147 // FP ALU
181 // FP ALU specific new schedwrite definitions
215 // ALU - ALU inpu
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H A DAArch64SchedA53.td42 def A53UnitALU : ProcResource<2> { let BufferSize = 0; } // Int ALU
47 def A53UnitFPALU : ProcResource<1> { let BufferSize = 0; } // FP ALU
57 // ALU - Despite having a full latency of 4, most of the ALU instructions can
125 // FP ALU
157 // ALU - Most operands in the ALU pipes are not needed for two cycles. Shiftable
H A DAArch64SchedThunderX.td37 def THXT8XUnitALU : ProcResource<2> { let BufferSize = 0; } // Int ALU
42 def THXT8XUnitFPALU : ProcResource<1> { let BufferSize = 0; } // FP ALU
51 // ALU
152 // FP ALU
200 // ALU - Most operands in the ALU pipes are not needed for two cycles. Shiftable
H A DAArch64SchedTSV110.td37 def TSV110UnitALU : ProcResource<1>; // Int ALU
38 def TSV110UnitAB : ProcResource<2>; // Int ALU/BRU
55 // Integer ALU
56 // TODO: Use SchedVariant to select BRU for ALU ops that sets NZCV flags
135 // MicroOp Count/Types: #(ALU|AB|MDU|FSU1|FSU2|LdSt|ALUAB|F|FLdSt)
138 // 1 micro-ops to be issued down one ALU pipe, six MDU pipes and four LdSt pipes.
/freebsd/contrib/llvm-project/llvm/lib/Target/Lanai/
H A DLanaiSchedule.td54 def ALU : ProcResource<1> { let BufferSize = 0; }
68 def : WriteRes<WriteALU, [ALU]> { let Latency = 1; }
/freebsd/contrib/llvm-project/llvm/lib/Target/BPF/
H A DBPFInstrInfo.td285 // ALU instructions
310 multiclass ALU<BPFArithOp Opc, int off, string OpcodeStr, SDNode OpNode> {
335 defm ADD : ALU<BPF_ADD, 0, "+=", add>;
336 defm SUB : ALU<BPF_SUB, 0, "-=", sub>;
337 defm OR : ALU<BPF_OR, 0, "|=", or>;
338 defm AND : ALU<BPF_AND, 0, "&=", and>;
339 defm SLL : ALU<BPF_LSH, 0, "<<=", shl>;
340 defm SRL : ALU<BPF_RSH, 0, ">>=", srl>;
341 defm XOR : ALU<BPF_XOR, 0, "^=", xor>;
342 defm SRA : ALU<BPF_ARSH, 0, "s>>=", sra>;
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/freebsd/contrib/llvm-project/llvm/lib/Target/ARM/
H A DARMScheduleM7.td25 // The Cortex-M7 has two ALU, two LOAD, a STORE, a MAC, a BRANCH and a VFP
35 // for scheduling, so simple ALU operations executing in EX2 will have
58 // Basic ALU with shifts.
117 // ALU operations (32/64-bit). These go down the FP pipeline.
188 // Assume that these will go down the main ALU pipeline.
319 // Sched definitions for ALU
322 // Shifted ALU operands are read a cycle early.
H A DARMSchedule.td44 // def P01 : ProcResource<3>; // ALU unit (3 of it).
59 // Basic ALU operation.
63 // Basic ALU with shifts.
111 // ALU operations (32/64-bit)
H A DARMScheduleV6.td227 // Single-precision FP ALU
230 // Double-precision FP ALU
H A DARMScheduleM55.td106 def M55UnitALU : ProcResource<1> { let BufferSize = 0; } // Int ALU
123 // ALU //
131 // DX instructions are ALU instructions that take a single cycle. The
238 // No forwarding in the ALU normally
H A DARMScheduleA8.td19 def A8_NPipe : FuncUnit; // NEON ALU/MUL pipe
27 // Two fully-pipelined integer ALU pipelines
302 // Single-precision FP ALU
306 // Double-precision FP ALU
/freebsd/contrib/llvm-project/llvm/lib/Target/Hexagon/
H A DHexagonIntrinsicsV5.td222 // ALU32/ALU
225 // ALU32 / ALU / Logical Operations.
272 // XTYPE/ALU
281 // XTYPE / ALU / Logical-logical Words.
/freebsd/contrib/llvm-project/llvm/lib/Target/X86/
H A DX86Schedule.td134 defm WriteALU : X86SchedWritePair; // Simple integer ALU op.
135 defm WriteADC : X86SchedWritePair; // Integer ALU + flags op.
361 defm WriteVecALU : X86SchedWritePair<ReadAfterVecLd>; // Vector integer ALU op, no logicals.
362 defm WriteVecALUX : X86SchedWritePair<ReadAfterVecXLd>; // Vector integer ALU op, no logicals (XMM).
363 defm WriteVecALUY : X86SchedWritePair<ReadAfterVecYLd>; // Vector integer ALU op, no logicals (YMM).
364 defm WriteVecALUZ : X86SchedWritePair<ReadAfterVecYLd>; // Vector integer ALU op, no logicals (ZMM).
H A DX86ScheduleAtom.td35 def AtomPort0 : ProcResource<1>; // ALU: ALU0, shift/rotate, load/store
36 // SIMD/FP: SIMD ALU, Shuffle,SIMD/FP multiply, divide
37 def AtomPort1 : ProcResource<1>; // ALU: ALU1, bit processing, jump, and LEA
38 // SIMD/FP: SIMD ALU, FP Adder
203 // to '1' to tell the scheduler that the nop uses an ALU slot for a cycle.
H A DX86ScheduleZnver3.td89 // each one servicing one ALU pipeline and one or two other pipelines
97 // Each pipe has an ALU capable of general purpose integer operations.
133 // General ALU operations
528 defm : Zn3WriteResIntPair<WriteALU, [Zn3ALU0123], 1, [1], 1>; // Simple integer ALU op.
563 defm : Zn3WriteResIntPair<WriteADC, [Zn3ALU0123], 1, [4], 1>; // Integer ALU + flags op.
1033 defm : Zn3WriteResXMMPair<WriteVecALU, [Zn3FPVAdd0123], 1, [1], 1>; // Vector integer ALU op, no l…
1049 defm : Zn3WriteResXMMPair<WriteVecALUX, [Zn3FPVAdd0123], 1, [1], 1>; // Vector integer ALU op, no l…
1078 defm : Zn3WriteResYMMPair<WriteVecALUY, [Zn3FPVAdd0123], 1, [1], 1>; // Vector integer ALU op, no l…
1092 defm : X86WriteResPairUnsupported<WriteVecALUZ>; // Vector integer ALU op, no logicals (ZMM).

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