Lines Matching refs:ALU
44 def CortexA55UnitALU : ProcResource<2> { let BufferSize = 0; } // Int ALU
51 // The FP DIV/SQRT instructions execute totally differently from the FP ALU
54 def CortexA55UnitFPALU : ProcResource<2> { let BufferSize = 0; } // FP ALU
67 def : WriteRes<WriteI, [CortexA55UnitALU]> { let Latency = 3; } // ALU
68 def : WriteRes<WriteISReg, [CortexA55UnitALU]> { let Latency = 3; } // ALU of Shifted-Reg
69 def : WriteRes<WriteIEReg, [CortexA55UnitALU]> { let Latency = 3; } // ALU of Extended-Reg
147 // FP ALU
181 // FP ALU specific new schedwrite definitions
215 // ALU - ALU input operands are generally needed in EX1. An operand produced in
216 // in say EX2 can be forwarded for consumption to ALU in EX1, thereby
217 // allowing back-to-back ALU operations such as add. If an operand requires