| /freebsd/contrib/llvm-project/llvm/lib/Target/Lanai/ |
| H A D | LanaiAluCode.h | |
| H A D | LanaiISelDAGToDAG.cpp | 214 case ISD::ADDE: in isdToLanaiAluCode()
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| /freebsd/contrib/llvm-project/llvm/lib/Target/PowerPC/ |
| H A D | PPCBack2BackFusion.def | 15 ADDE,
504 ADDE,
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| H A D | PPCScheduleP7.td | 188 ADDE, ADDE8, ADDME, ADDME8, SUBFME, SUBFME8,
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| H A D | PPCISelLowering.h | 166 ADDE, enumerator
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| H A D | P10InstrResources.td | 973 ADDE, ADDE8,
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| H A D | PPCISelLowering.cpp | 1844 case PPCISD::ADDE: in getTargetNodeName()
12464 PPCISD::ADDE, DL, DAG.getVTList(SumType, MVT::i32), Zero, Zero, Flag); in ConvertCarryFlagToCarryValue()
12498 Opc = IsAdd ? PPCISD::ADDE : PPCISD::SUBE; in LowerADDSUBO_CARRY()
16658 if (LHS->getOpcode() == PPCISD::ADDE && in DAGCombineAddc()
17513 case PPCISD::ADDE: { in computeKnownBitsForTargetNode()
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| /freebsd/contrib/llvm-project/llvm/include/llvm/CodeGen/ |
| H A D | ISDOpcodes.h | 299 ADDE, enumerator
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| H A D | TargetLowering.h | 2985 case ISD::ADDE: in isCommutativeBinOp()
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| /freebsd/contrib/llvm-project/llvm/lib/Target/Mips/ |
| H A D | MipsSEISelDAGToDAG.cpp | 216 assert(Opc == ISD::ADDE && "ISD::ADDE not in a chain of ADDE nodes!"); in selectAddE()
720 case ISD::ADDE: { in trySelect()
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| /freebsd/contrib/llvm-project/llvm/lib/Target/ARM/ |
| H A D | ARMISelLowering.h | 111 ADDE, // Add using carry enumerator
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| H A D | ARMISelLowering.cpp | 1733 MAKE_CASE(ARMISD::ADDE) in getTargetNodeName()
5100 return DAG.getNode(ARMISD::ADDE, DL, DAG.getVTList(VT, MVT::i32), in ConvertCarryFlagToBooleanCarry()
9951 Result = DAG.getNode(ARMISD::ADDE, DL, VTs, Op.getOperand(0), in LowerUADDSUBO_CARRY()
12994 assert((AddeSubeNode->getOpcode() == ARMISD::ADDE || in AddCombineTo64bitMLAL()
13004 if ((AddeSubeNode->getOpcode() == ARMISD::ADDE && in AddCombineTo64bitMLAL()
13023 if (AddeSubeNode->getOpcode() == ARMISD::ADDE && in AddCombineTo64bitMLAL()
13202 (AddeNode->getOpcode() == ARMISD::ADDE) && in PerformUMLALCombine()
13223 if (LHS->getOpcode() == ARMISD::ADDE && in PerformAddcSubcCombine()
13263 unsigned Opcode = (N->getOpcode() == ARMISD::ADDE) ? ARMISD::SUBE in PerformAddeSubeCombine()
13264 : ARMISD::ADDE; in PerformAddeSubeCombine()
[all …]
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| /freebsd/contrib/llvm-project/llvm/lib/Target/ARC/ |
| H A D | ARCISelLowering.cpp | 126 setOperationAction(ISD::ADDE, MVT::i32, Legal); in ARCTargetLowering()
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| /freebsd/contrib/llvm-project/llvm/lib/CodeGen/SelectionDAG/ |
| H A D | SelectionDAGDumper.cpp | 357 case ISD::ADDE: return "adde"; in getOperationName()
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| H A D | LegalizeIntegerTypes.cpp | 240 case ISD::ADDE: in PromoteIntegerResult()
3064 case ISD::ADDE: in ExpandIntegerResult()
3622 Hi = DAG.getNode(ISD::ADDE, dl, VTList, HiOps); in ExpandIntRes_ADDSUB()
3731 Hi = DAG.getNode(ISD::ADDE, dl, VTList, HiOps); in ExpandIntRes_ADDSUBC()
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| /freebsd/contrib/llvm-project/llvm/lib/Target/M68k/ |
| H A D | M68kISelLowering.cpp | 111 setOperationAction(ISD::ADDE, VT, Custom); in M68kTargetLowering()
1400 case ISD::ADDE: in LowerOperation()
2626 case ISD::ADDE: in LowerADDC_ADDE_SUBC_SUBE()
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| /freebsd/contrib/llvm-project/llvm/lib/Target/AMDGPU/ |
| H A D | AMDGPUISelDAGToDAG.cpp | 630 case ISD::ADDE: in Select()
965 bool ConsumeCarry = (Opcode == ISD::ADDE || Opcode == ISD::SUBE); in SelectADD_SUB_I64()
968 bool IsAdd = Opcode == ISD::ADD || Opcode == ISD::ADDC || Opcode == ISD::ADDE; in SelectADD_SUB_I64()
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| H A D | R600ISelLowering.cpp | 192 setOperationAction({ISD::ADDC, ISD::SUBC, ISD::ADDE, ISD::SUBE}, VT, in R600TargetLowering()
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| /freebsd/contrib/llvm-project/llvm/lib/CodeGen/ |
| H A D | TargetLoweringBase.cpp | 833 setOperationAction({ISD::ADDC, ISD::ADDE, ISD::SUBC, ISD::SUBE}, VT, in initActions()
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| /freebsd/contrib/llvm-project/llvm/lib/Target/Sparc/ |
| H A D | SparcISelLowering.cpp | 1728 setOperationAction(ISD::ADDE, MVT::i32, Legal); in SparcTargetLowering()
1734 setOperationAction(ISD::ADDE, MVT::i64, Legal); in SparcTargetLowering()
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| H A D | SparcInstrInfo.td | 884 defm ADDE : F3_12<"addxcc", 0b011000, adde, IntRegs, i32, simm13Op>;
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| /freebsd/contrib/llvm-project/llvm/lib/Target/NVPTX/ |
| H A D | NVPTXISelLowering.cpp | 640 {ISD::ABS, ISD::ADD, ISD::ADDC, ISD::ADDE, in NVPTXTargetLowering()
818 setOperationAction(ISD::ADDE, MVT::i32, Legal); in NVPTXTargetLowering()
823 setOperationAction(ISD::ADDE, MVT::i64, Legal); in NVPTXTargetLowering()
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| /freebsd/contrib/llvm-project/llvm/lib/Target/AVR/ |
| H A D | AVRISelLowering.cpp | 73 setOperationAction(ISD::ADDE, VT, Legal); in AVRTargetLowering()
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| /freebsd/contrib/llvm-project/llvm/include/llvm/Target/ |
| H A D | TargetSelectionDAG.td | 448 def adde : SDNode<"ISD::ADDE" , SDTIntBinOp,
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| /freebsd/contrib/llvm-project/llvm/lib/Target/WebAssembly/ |
| H A D | WebAssemblyISelLowering.cpp | 161 ISD::SRL_PARTS, ISD::ADDC, ISD::ADDE, ISD::SUBC, ISD::SUBE}) { in WebAssemblyTargetLowering()
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