| /freebsd/contrib/llvm-project/llvm/lib/Target/Lanai/ |
| H A D | LanaiAluCode.h | |
| H A D | LanaiISelDAGToDAG.cpp | 223 case ISD::ADDE: in isdToLanaiAluCode()
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| /freebsd/contrib/llvm-project/llvm/lib/Target/PowerPC/ |
| H A D | PPCBack2BackFusion.def | 15 ADDE,
504 ADDE,
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| H A D | P10InstrResources.td | 971 ADDE, ADDE8,
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| H A D | PPCISelLowering.cpp | 254 setOperationAction(ISD::ADDE, VT, Legal); in PPCTargetLowering()
17901 return DAG.getNode(ISD::ADDE, DL, VTs, LHS, DAG.getConstant(0, DL, MVT::i64), in combineADDToADDZE()
17916 return DAG.getNode(ISD::ADDE, DL, VTs, LHS, DAG.getConstant(0, DL, MVT::i64), in combineADDToADDZE()
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| /freebsd/contrib/llvm-project/llvm/include/llvm/CodeGen/ |
| H A D | ISDOpcodes.h | 286 ADDE, enumerator
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| H A D | TargetLowering.h | 2901 case ISD::ADDE: in isCommutativeBinOp()
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| /freebsd/contrib/llvm-project/llvm/lib/Target/Mips/ |
| H A D | MipsSEISelDAGToDAG.cpp | 220 assert(Opc == ISD::ADDE && "ISD::ADDE not in a chain of ADDE nodes!"); in selectAddE()
774 case ISD::ADDE: { in trySelect()
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| H A D | MipsSEISelLowering.cpp | 106 setOperationAction(ISD::ADDE, MVT::i32, Legal); in MipsSETargetLowering()
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| /freebsd/contrib/llvm-project/llvm/lib/Target/Sparc/ |
| H A D | SparcISelLowering.cpp | 1735 setOperationAction(ISD::ADDE, MVT::i32, Custom); in SparcTargetLowering()
1741 setOperationAction(ISD::ADDE, MVT::i64, Custom); in SparcTargetLowering()
3131 case ISD::ADDC: hiOpc = ISD::ADDE; break; in LowerADDC_ADDE_SUBC_SUBE()
3132 case ISD::ADDE: hasChain = true; break; in LowerADDC_ADDE_SUBC_SUBE()
3287 case ISD::ADDE: in LowerOperation()
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| H A D | SparcInstrInfo.td | 836 defm ADDE : F3_12<"addxcc", 0b011000, adde, IntRegs, i32, simm13Op>;
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| /freebsd/contrib/llvm-project/llvm/lib/Target/ARM/ |
| H A D | ARMISelLowering.h | 109 ADDE, // Add using carry enumerator
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| H A D | ARMISelLowering.cpp | 1738 MAKE_CASE(ARMISD::ADDE) in getTargetNodeName()
5037 return DAG.getNode(ARMISD::ADDE, DL, DAG.getVTList(VT, MVT::i32), in ConvertCarryFlagToBooleanCarry()
9899 Result = DAG.getNode(ARMISD::ADDE, DL, VTs, Op.getOperand(0), in LowerUADDSUBO_CARRY()
12927 assert((AddeSubeNode->getOpcode() == ARMISD::ADDE || in AddCombineTo64bitMLAL()
12937 if ((AddeSubeNode->getOpcode() == ARMISD::ADDE && in AddCombineTo64bitMLAL()
12956 if (AddeSubeNode->getOpcode() == ARMISD::ADDE && in AddCombineTo64bitMLAL()
13135 (AddeNode->getOpcode() == ARMISD::ADDE) && in PerformUMLALCombine()
13156 if (LHS->getOpcode() == ARMISD::ADDE && in PerformAddcSubcCombine()
13196 unsigned Opcode = (N->getOpcode() == ARMISD::ADDE) ? ARMISD::SUBE in PerformAddeSubeCombine()
13197 : ARMISD::ADDE; in PerformAddeSubeCombine()
[all …]
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| /freebsd/contrib/llvm-project/llvm/lib/Target/ARC/ |
| H A D | ARCISelLowering.cpp | 125 setOperationAction(ISD::ADDE, MVT::i32, Legal); in ARCTargetLowering()
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| /freebsd/contrib/llvm-project/llvm/lib/CodeGen/SelectionDAG/ |
| H A D | SelectionDAGDumper.cpp | 340 case ISD::ADDE: return "adde"; in getOperationName()
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| H A D | LegalizeIntegerTypes.cpp | 220 case ISD::ADDE: in PromoteIntegerResult()
2881 case ISD::ADDE: in ExpandIntegerResult()
3425 Hi = DAG.getNode(ISD::ADDE, dl, VTList, HiOps); in ExpandIntRes_ADDSUB()
3533 Hi = DAG.getNode(ISD::ADDE, dl, VTList, HiOps); in ExpandIntRes_ADDSUBC()
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| H A D | SelectionDAG.cpp | 3934 case ISD::ADDE: { in computeKnownBits()
3939 if (Opcode == ISD::ADDE) in computeKnownBits()
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| /freebsd/contrib/llvm-project/llvm/lib/Target/AMDGPU/ |
| H A D | AMDGPUISelDAGToDAG.cpp | 518 case ISD::ADDE: in Select()
849 bool ConsumeCarry = (Opcode == ISD::ADDE || Opcode == ISD::SUBE); in SelectADD_SUB_I64()
852 bool IsAdd = Opcode == ISD::ADD || Opcode == ISD::ADDC || Opcode == ISD::ADDE; in SelectADD_SUB_I64()
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| H A D | R600ISelLowering.cpp | 188 setOperationAction({ISD::ADDC, ISD::SUBC, ISD::ADDE, ISD::SUBE}, VT, in R600TargetLowering()
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| /freebsd/contrib/llvm-project/llvm/lib/Target/M68k/ |
| H A D | M68kISelLowering.cpp | 109 setOperationAction(ISD::ADDE, VT, Custom); in M68kTargetLowering()
1398 case ISD::ADDE: in LowerOperation()
2625 case ISD::ADDE: in LowerADDC_ADDE_SUBC_SUBE()
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| /freebsd/contrib/llvm-project/llvm/lib/CodeGen/ |
| H A D | TargetLoweringBase.cpp | 742 setOperationAction({ISD::ADDC, ISD::ADDE, ISD::SUBC, ISD::SUBE}, VT, in initActions()
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| /freebsd/contrib/llvm-project/llvm/lib/Target/NVPTX/ |
| H A D | NVPTXISelLowering.cpp | 529 {ISD::ABS, ISD::ADD, ISD::ADDC, ISD::ADDE, in NVPTXTargetLowering()
708 setOperationAction(ISD::ADDE, MVT::i32, Legal); in NVPTXTargetLowering()
713 setOperationAction(ISD::ADDE, MVT::i64, Legal); in NVPTXTargetLowering()
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| /freebsd/contrib/llvm-project/llvm/lib/Target/AVR/ |
| H A D | AVRISelLowering.cpp | 74 setOperationAction(ISD::ADDE, VT, Legal); in AVRTargetLowering()
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| /freebsd/contrib/llvm-project/llvm/lib/Target/WebAssembly/ |
| H A D | WebAssemblyISelLowering.cpp | 158 ISD::SRL_PARTS, ISD::ADDC, ISD::ADDE, ISD::SUBC, ISD::SUBE}) { in WebAssemblyTargetLowering()
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| /freebsd/contrib/llvm-project/llvm/include/llvm/Target/ |
| H A D | TargetSelectionDAG.td | 432 def adde : SDNode<"ISD::ADDE" , SDTIntBinOp,
|