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/freebsd/sys/dev/mii/
H A Dmiidevs120 model AGERE ET1011 0x0001 ET1011 10/100/1000baseT PHY
121 model AGERE ET1011C 0x0004 ET1011C 10/100/1000baseT PHY
139 model xxATHEROS F1 0x0001 Atheros F1 10/100/1000 PHY
140 model xxATHEROS F2 0x0002 Atheros F2 10/100 PHY
141 model xxATHEROS AR8021 0x0004 Atheros AR8021 10/100/1000 PHY
142 model xxATHEROS F1_7 0x0007 Atheros F1 10/100/1000 PHY
145 model xxASIX AX88X9X 0x0031 Ax88x9x internal PHY
148 model xxBROADCOM 3C905B 0x0012 Broadcom 3c905B internal PHY
149 model xxBROADCOM 3C905C 0x0017 Broadcom 3c905C internal PHY
155 model xxBROADCOM BCM5365 0x0037 BCM5365 10/100 5-port PHY switch
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/freebsd/sys/contrib/device-tree/Bindings/phy/
H A Dphy-hisi-inno-usb2.txt1 Device tree bindings for HiSilicon INNO USB2 PHY
7 - reg: Should be the address space for PHY configuration register in peripheral
9 - clocks: The phandle and clock specifier pair for INNO USB2 PHY device
11 - resets: The phandle and reset specifier pair for INNO USB2 PHY device reset
16 The INNO USB2 PHY device should be a child node of peripheral controller that
17 contains the PHY configuration register, and each device supports up to 2 PHY
18 ports which are represented as child nodes of INNO USB2 PHY device.
20 Required properties for PHY port node:
21 - reg: The PHY por
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H A Dphy-bindings.txt2 information about PHY subsystem refer to Documentation/driver-api/phy/phy.rst
4 PHY device node
8 #phy-cells: Number of cells in a PHY specifier; The meaning of all those
9 cells is defined by the binding for the phy node. The PHY
11 PHY.
14 phy-supply: Phandle to a regulator that provides power to the PHY. This
15 regulator will be managed during the PHY power on/off sequence.
29 That node describes an IP block (PHY provider) that implements 2 different PHYs.
33 PHY user node
37 phys : the phandle for the PHY device (used by the PHY subsystem; not to be
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H A Dsamsung-phy.txt14 In case of exynos5433 compatible PHY:
21 the PHY specifier identifies the PHY and its meaning is as follows:
27 supports additional fifth PHY:
30 Samsung Exynos SoC series Display Port PHY
39 - #phy-cells : from the generic PHY bindings, must be 0;
41 Samsung S5P/Exynos SoC series USB PHY
60 PHY module
65 The first phandle argument in the PHY specifier identifies the PHY, its
91 Then the PHY can be used in other nodes such as:
98 Refer to DT bindings documentation of particular PHY consumer devices for more
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H A Dphy-mtk-ufs.txt1 MediaTek Universal Flash Storage (UFS) M-PHY binding
4 UFS M-PHY nodes are defined to describe on-chip UFS M-PHY hardware macro.
5 Each UFS M-PHY node should have its own node.
7 To bind UFS M-PHY with UFS host controller, the controller node should
8 contain a phandle reference to UFS M-PHY node.
10 Required properties for UFS M-PHY nodes:
14 - reg : Address and length of the UFS M-PHY register set.
21 "mp": M-PHY core control clock.
H A Dphy-stm32-usbphyc.txt1 STMicroelectronics STM32 USB HS PHY controller
3 The STM32 USBPHYC block contains a dual port High Speed UTMI+ PHY and a UTMI
4 switch. It controls PHY configuration and status, and the UTMI+ switch that
5 selects either OTG or HOST controller for the second PHY port. It also sets
11 |_ PHY port#1 _________________ HOST controller
14 |_ PHY port#2 ----| |________________
41 - phy-supply: phandle to the regulator providing 3V3 power to the PHY,
43 - vdda1v1-supply: phandle to the regulator providing 1V1 power to the PHY
44 - vdda1v8-supply: phandle to the regulator providing 1V8 power to the PHY
45 - #phy-cells: see phy-bindings.txt in the same directory, must be <0> for PHY
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H A Dbrcm,stingray-usb-phy.txt1 Broadcom Stingray USB PHY
5 - "brcm,sr-usb-combo-phy" is combo PHY has two PHYs, one SS and one HS.
6 - "brcm,sr-usb-hs-phy" is a single HS PHY.
7 - reg: offset and length of the PHY blocks registers
10 the PHY number of two PHYs. 0 for HS PHY and 1 for SS PHY.
13 Refer to phy/phy-bindings.txt for the generic PHY binding properties
H A Dphy-mvebu-utmi.txt1 MVEBU A3700 UTMI PHY
4 USB2 UTMI+ PHY controllers can be found on the following Marvell MVEBU SoCs:
10 different UTMI PHY.
15 * "marvell,a3700-utmi-host-phy" for the PHY connected to
17 * "marvell,a3700-utmi-otg-phy" for the PHY connected to
19 - reg: PHY IP register range.
22 controller and the PHY.
H A Dti-phy.txt1 TI PHY: DT DOCUMENTATION FOR PHYs in TI PLATFORMs
3 OMAP CONTROL PHY
11 e.g. USB3 PHY and SATA PHY on OMAP5.
14 e.g. PCIE PHY in DRA7x
15 "ti,control-phy-usb2-dra7" - if it has power down register like USB2 PHY on
17 "ti,control-phy-usb2-am437" - if it has power down register like USB2 PHY on
30 TI PIPE3 PHY
54 PHY). If "id" is not provided, it is set to default value of '1'.
62 - ctrl-module : phandle of the control module used by PHY drive
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H A Dnvidia,tegra20-usb-phy.txt1 Tegra SOC USB PHY
3 The device node for Tegra SOC USB PHY:
11 - The PHY's own register set.
13 - The register set of the PHY containing the UTMI pad control registers.
18 - reg: The clock needed to access the PHY's own registers. This is the
24 - ulpi-link: The clock Tegra provides to the ULPI PHY (usually pad DAP_MCLK2
31 - usb: The PHY's own reset signal.
32 - utmi-pads: The reset of the PHY containing the chip-wide UTMI pad control
36 - nvidia,phy-reset-gpio : The GPIO used to reset the PHY.
38 Required PHY timing params for utmi phy, for all chips:
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H A Dkeystone-usb-phy.txt1 TI Keystone USB PHY
9 The main purpose of this PHY driver is to enable the USB PHY reference clock
10 gate on the Keystone SOC for both the USB2 and USB3 PHY. Otherwise it is just
11 an NOP PHY driver. Hence this node is referenced as both the usb2 and usb3
H A Drockchip-usb-phy.txt1 ROCKCHIP USB2 PHY
16 Each PHY should be represented as a sub-node.
21 - reg: PHY configure reg address offset in GRF
22 "0x320" - for PHY attach to OTG controller
23 "0x334" - for PHY attach to HOST0 controller
24 "0x348" - for PHY attach to HOST1 controller
H A Dbrcm,ns2-drd-phy.txt1 BROADCOM NORTHSTAR2 USB2 (DUAL ROLE DEVICE) PHY
5 - reg: offset and length of the NS2 PHY related registers.
10 crmu-ctrl - for CRMU core vdd, PHY and PHY PLL reset
16 Refer to phy/phy-bindings.txt for the generic PHY binding properties
H A Dbrcm,sr-pcie-phy.txt1 Broadcom Stingray PCIe PHY
8 - #phy-cells: Must be 1, denotes the PHY index
11 PHY index goes from 0 to 7
13 For the internal PAXC based root complex, PHY index is always 8
34 /* users of the PCIe PHY */
H A Dphy-tegra194-p2u.txt3 Tegra194 has two PHY bricks namely HSIO (High Speed IO) and NVHS (NVIDIA High
6 interface and PHY of HSIO/NVHS bricks. Each P2U instance represents one PCIe
15 Required properties for PHY port node:
16 - #phy-cells: Defined by generic PHY bindings. Must be 0.
18 Refer to phy/phy-bindings.txt for the generic PHY binding properties.
H A Dphy-cadence-sierra.txt1 Cadence Sierra PHY
10 "sierra_reset" must control the reset line to the PHY.
11 "sierra_apb" must control the reset line to the APB PHY
13 - reg: register range for the PHY.
24 PHY registers will be configured by hardware. If not
29 Each group of PHY lanes with a single master lane should be represented as
34 - #phy-cells: Generic PHY binding; must be 0.
H A Dti-phy-gmii-sel.txt1 CPSW Port's Interface Mode Selection PHY Tree Bindings
31 CPSW Port's Interface Mode Selection PHY describes MII interface mode between
32 CPSW Port and Ethernet PHY which depends on Eth PHY and board configuration.
34 CPSW Port's Interface Mode Selection PHY device should defined as child device
36 PHY bindings (See phy/phy-bindings.txt).
H A Dphy-cpcap-usb.txt1 Motorola CPCAP PMIC USB PHY binding
7 interrupts: CPCAP PMIC interrupts used by the USB PHY
9 io-channels: IIO ADC channels used by the USB PHY
11 vusb-supply: Regulator for the PHY
14 pinctrl: Optional alternate pin modes for the PHY
/freebsd/sys/dev/mdio/
H A Dmdio_if.m32 * @param phy PHY address.
33 * @param reg The PHY register offset.
46 * @param phy PHY address.
47 * @param reg The PHY register offset.
60 * @param phy PHY address.
61 * @param reg The PHY register offset.
76 * @param phy PHY address.
77 * @param reg The PHY register offset.
93 * @param phy PHY address.
96 * @param reg The PHY register offset.
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/freebsd/sys/contrib/device-tree/Bindings/net/
H A Dmicrel.txt1 Micrel PHY properties.
21 See the respective PHY datasheet for the mode values.
29 Note that this option in only needed for certain PHY revisions with a
40 - micrel,fiber-mode: If present the PHY is configured to operate in fiber mode
43 by the FXEN boot strapping pin. It can't be determined from the PHY
44 registers whether the PHY is in fiber mode, so this boolean device tree
47 In fiber mode, auto-negotiation is disabled and the PHY can only work in
51 PHY is probed.
53 Some PHYs have a COMA mode input pin which puts the PHY into
/freebsd/tools/tools/ath/athstats/
H A Dathstats.c555 #define PHY(x) \ in ath_get_curstat() macro
635 case S_RX_PHY_UNDERRUN: PHY(HAL_PHYERR_UNDERRUN); in ath_get_curstat()
636 case S_RX_PHY_TIMING: PHY(HAL_PHYERR_TIMING); in ath_get_curstat()
637 case S_RX_PHY_PARITY: PHY(HAL_PHYERR_PARITY); in ath_get_curstat()
638 case S_RX_PHY_RATE: PHY(HAL_PHYERR_RATE); in ath_get_curstat()
639 case S_RX_PHY_LENGTH: PHY(HAL_PHYERR_LENGTH); in ath_get_curstat()
640 case S_RX_PHY_RADAR: PHY(HAL_PHYERR_RADAR); in ath_get_curstat()
641 case S_RX_PHY_SERVICE: PHY(HAL_PHYERR_SERVICE); in ath_get_curstat()
642 case S_RX_PHY_TOR: PHY(HAL_PHYERR_TOR); in ath_get_curstat()
643 case S_RX_PHY_OFDM_TIMING: PHY(HAL_PHYERR_OFDM_TIMING); in ath_get_curstat()
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/freebsd/sys/contrib/device-tree/Bindings/ufs/
H A Dufs-qcom.txt1 * Qualcomm Technologies Inc Universal Flash Storage (UFS) PHY
3 UFSPHY nodes are defined to describe on-chip UFS PHY hardware macro.
4 Each UFS PHY node should have its own node.
6 To bind UFS PHY with UFS host controller, the controller node should
7 contain a phandle reference to UFS PHY node.
15 - reg : should contain PHY register address space (mandatory),
19 - vdda-phy-supply : phandle to main PHY supply for analog domain
20 - vdda-pll-supply : phandle to PHY PLL and Power-Gen block power supply
32 - resets : specifies the PHY reset in the UFS controller
/freebsd/sys/contrib/device-tree/Bindings/usb/
H A Dusb-nop-xceiv.txt1 USB NOP PHY
8 - clocks: phandle to the PHY clock. Use as per Documentation/devicetree
14 - clock-frequency: the clock frequency (in Hz) that the PHY clock must
17 - vcc-supply: phandle to the regulator that provides power to the PHY.
40 hsusb1_phy is a NOP USB PHY device that gets its clock from an oscillator
41 and expects that clock to be configured to 19.2MHz by the NOP PHY driver.
42 hsusb1_vcc_regulator provides power to the PHY and GPIO 7 controls RESET.
H A Dmsm-hsusb.txt8 - usb-phy: phandle for the PHY device
18 USB PHY with optional OTG:
22 "qcom,usb-otg-ci" for chipsets with ChipIdea 45nm PHY
23 "qcom,usb-otg-snps" for chipsets with Synopsys 28nm PHY
31 "phy" USB PHY reference clock
45 "phy" USB PHY controller reset
49 1 - PHY control
59 - qcom,phy-init-sequence: PHY configuration sequence values. This is related to Device
67 0 - PHY one, default
68 1 - Second PHY
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/freebsd/sys/contrib/device-tree/Bindings/mmc/
H A Dmarvell,xenon-sdhci.txt7 clock and PHY.
31 PHY PAD Voltage Control register.
47 To select eMMC 5.1 PHY, set:
49 eMMC 5.1 PHY is the default choice if this property is not provided.
50 To select eMMC 5.0 PHY, set:
54 Please note that this property only presents the type of PHY.
60 Set PHY ZNR value.
61 Only available for eMMC PHY.
66 Set PHY ZPR value.
67 Only available for eMMC PHY.
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