xref: /linux/arch/arm64/boot/dts/allwinner/sun50i-h6.dtsi (revision ec71f661a572a770d7c861cd52a50cbbb0e1a8d1)
1// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
2// Copyright (C) 2017 Icenowy Zheng <icenowy@aosc.io>
3
4#include <dt-bindings/interrupt-controller/arm-gic.h>
5#include <dt-bindings/clock/sun50i-h6-ccu.h>
6#include <dt-bindings/clock/sun50i-h6-r-ccu.h>
7#include <dt-bindings/clock/sun6i-rtc.h>
8#include <dt-bindings/clock/sun8i-de2.h>
9#include <dt-bindings/clock/sun8i-tcon-top.h>
10#include <dt-bindings/reset/sun50i-h6-ccu.h>
11#include <dt-bindings/reset/sun50i-h6-r-ccu.h>
12#include <dt-bindings/reset/sun8i-de2.h>
13#include <dt-bindings/thermal/thermal.h>
14
15/ {
16	interrupt-parent = <&gic>;
17	#address-cells = <1>;
18	#size-cells = <1>;
19
20	cpus {
21		#address-cells = <1>;
22		#size-cells = <0>;
23
24		cpu0: cpu@0 {
25			compatible = "arm,cortex-a53";
26			device_type = "cpu";
27			reg = <0>;
28			enable-method = "psci";
29			clocks = <&ccu CLK_CPUX>;
30			#cooling-cells = <2>;
31			i-cache-size = <0x8000>;
32			i-cache-line-size = <64>;
33			i-cache-sets = <256>;
34			d-cache-size = <0x8000>;
35			d-cache-line-size = <64>;
36			d-cache-sets = <128>;
37			next-level-cache = <&l2_cache>;
38		};
39
40		cpu1: cpu@1 {
41			compatible = "arm,cortex-a53";
42			device_type = "cpu";
43			reg = <1>;
44			enable-method = "psci";
45			clocks = <&ccu CLK_CPUX>;
46			#cooling-cells = <2>;
47			i-cache-size = <0x8000>;
48			i-cache-line-size = <64>;
49			i-cache-sets = <256>;
50			d-cache-size = <0x8000>;
51			d-cache-line-size = <64>;
52			d-cache-sets = <128>;
53			next-level-cache = <&l2_cache>;
54		};
55
56		cpu2: cpu@2 {
57			compatible = "arm,cortex-a53";
58			device_type = "cpu";
59			reg = <2>;
60			enable-method = "psci";
61			clocks = <&ccu CLK_CPUX>;
62			#cooling-cells = <2>;
63			i-cache-size = <0x8000>;
64			i-cache-line-size = <64>;
65			i-cache-sets = <256>;
66			d-cache-size = <0x8000>;
67			d-cache-line-size = <64>;
68			d-cache-sets = <128>;
69			next-level-cache = <&l2_cache>;
70		};
71
72		cpu3: cpu@3 {
73			compatible = "arm,cortex-a53";
74			device_type = "cpu";
75			reg = <3>;
76			enable-method = "psci";
77			clocks = <&ccu CLK_CPUX>;
78			#cooling-cells = <2>;
79			i-cache-size = <0x8000>;
80			i-cache-line-size = <64>;
81			i-cache-sets = <256>;
82			d-cache-size = <0x8000>;
83			d-cache-line-size = <64>;
84			d-cache-sets = <128>;
85			next-level-cache = <&l2_cache>;
86		};
87
88		l2_cache: l2-cache {
89			compatible = "cache";
90			cache-level = <2>;
91			cache-unified;
92			cache-size = <0x80000>;
93			cache-line-size = <64>;
94			cache-sets = <512>;
95		};
96	};
97
98	de: display-engine {
99		compatible = "allwinner,sun50i-h6-display-engine";
100		allwinner,pipelines = <&mixer0>;
101		status = "disabled";
102	};
103
104	osc24M: osc24M-clk {
105		#clock-cells = <0>;
106		compatible = "fixed-clock";
107		clock-frequency = <24000000>;
108		clock-output-names = "osc24M";
109	};
110
111	pmu {
112		compatible = "arm,cortex-a53-pmu";
113		interrupts = <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>,
114			     <GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>,
115			     <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>,
116			     <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>;
117		interrupt-affinity = <&cpu0>, <&cpu1>, <&cpu2>, <&cpu3>;
118	};
119
120	psci {
121		compatible = "arm,psci-0.2";
122		method = "smc";
123	};
124
125	timer {
126		compatible = "arm,armv8-timer";
127		arm,no-tick-in-suspend;
128		interrupts = <GIC_PPI 13
129			(GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>,
130			     <GIC_PPI 14
131			(GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>,
132			     <GIC_PPI 11
133			(GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>,
134			     <GIC_PPI 10
135			(GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
136	};
137
138	soc {
139		compatible = "simple-bus";
140		#address-cells = <1>;
141		#size-cells = <1>;
142		ranges;
143
144		bus@1000000 {
145			compatible = "allwinner,sun50i-h6-de3",
146				     "allwinner,sun50i-a64-de2";
147			reg = <0x1000000 0x400000>;
148			allwinner,sram = <&de2_sram 1>;
149			#address-cells = <1>;
150			#size-cells = <1>;
151			ranges = <0 0x1000000 0x400000>;
152
153			display_clocks: clock@0 {
154				compatible = "allwinner,sun50i-h6-de3-clk";
155				reg = <0x0 0x10000>;
156				clocks = <&ccu CLK_BUS_DE>,
157					 <&ccu CLK_DE>;
158				clock-names = "bus",
159					      "mod";
160				resets = <&ccu RST_BUS_DE>;
161				#clock-cells = <1>;
162				#reset-cells = <1>;
163			};
164
165			mixer0: mixer@100000 {
166				compatible = "allwinner,sun50i-h6-de3-mixer-0";
167				reg = <0x100000 0x100000>;
168				clocks = <&display_clocks CLK_BUS_MIXER0>,
169					 <&display_clocks CLK_MIXER0>;
170				clock-names = "bus",
171					      "mod";
172				resets = <&display_clocks RST_MIXER0>;
173				iommus = <&iommu 0>;
174
175				ports {
176					#address-cells = <1>;
177					#size-cells = <0>;
178
179					mixer0_out: port@1 {
180						reg = <1>;
181
182						mixer0_out_tcon_top_mixer0: endpoint {
183							remote-endpoint = <&tcon_top_mixer0_in_mixer0>;
184						};
185					};
186				};
187			};
188		};
189
190		video-codec-g2@1c00000 {
191			compatible = "allwinner,sun50i-h6-vpu-g2";
192			reg = <0x01c00000 0x1000>;
193			interrupts = <GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH>;
194			clocks = <&ccu CLK_BUS_VP9>, <&ccu CLK_VP9>;
195			clock-names = "bus", "mod";
196			resets = <&ccu RST_BUS_VP9>;
197			iommus = <&iommu 5>;
198		};
199
200		video-codec@1c0e000 {
201			compatible = "allwinner,sun50i-h6-video-engine";
202			reg = <0x01c0e000 0x2000>;
203			clocks = <&ccu CLK_BUS_VE>, <&ccu CLK_VE>,
204				 <&ccu CLK_MBUS_VE>;
205			clock-names = "ahb", "mod", "ram";
206			resets = <&ccu RST_BUS_VE>;
207			interrupts = <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>;
208			allwinner,sram = <&ve_sram 1>;
209			iommus = <&iommu 3>;
210		};
211
212		gpu: gpu@1800000 {
213			compatible = "allwinner,sun50i-h6-mali",
214				     "arm,mali-t720";
215			reg = <0x01800000 0x4000>;
216			interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>,
217				     <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>,
218				     <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>;
219			interrupt-names = "job", "mmu", "gpu";
220			clocks = <&ccu CLK_GPU>, <&ccu CLK_BUS_GPU>;
221			clock-names = "core", "bus";
222			resets = <&ccu RST_BUS_GPU>;
223			#cooling-cells = <2>;
224			status = "disabled";
225		};
226
227		crypto: crypto@1904000 {
228			compatible = "allwinner,sun50i-h6-crypto";
229			reg = <0x01904000 0x1000>;
230			interrupts = <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>;
231			clocks = <&ccu CLK_BUS_CE>, <&ccu CLK_CE>, <&ccu CLK_MBUS_CE>;
232			clock-names = "bus", "mod", "ram";
233			resets = <&ccu RST_BUS_CE>;
234		};
235
236		syscon: syscon@3000000 {
237			compatible = "allwinner,sun50i-h6-system-control",
238				     "allwinner,sun50i-a64-system-control";
239			reg = <0x03000000 0x1000>;
240			#address-cells = <1>;
241			#size-cells = <1>;
242			ranges;
243
244			sram_c: sram@28000 {
245				compatible = "mmio-sram";
246				reg = <0x00028000 0x1e000>;
247				#address-cells = <1>;
248				#size-cells = <1>;
249				ranges = <0 0x00028000 0x1e000>;
250
251				de2_sram: sram-section@0 {
252					compatible = "allwinner,sun50i-h6-sram-c",
253						     "allwinner,sun50i-a64-sram-c";
254					reg = <0x0000 0x1e000>;
255				};
256			};
257
258			sram_c1: sram@1a00000 {
259				compatible = "mmio-sram";
260				reg = <0x01a00000 0x200000>;
261				#address-cells = <1>;
262				#size-cells = <1>;
263				ranges = <0 0x01a00000 0x200000>;
264
265				ve_sram: sram-section@0 {
266					compatible = "allwinner,sun50i-h6-sram-c1",
267						     "allwinner,sun4i-a10-sram-c1";
268					reg = <0x000000 0x200000>;
269				};
270			};
271		};
272
273		ccu: clock@3001000 {
274			compatible = "allwinner,sun50i-h6-ccu";
275			reg = <0x03001000 0x1000>;
276			clocks = <&osc24M>, <&rtc CLK_OSC32K>, <&rtc CLK_IOSC>;
277			clock-names = "hosc", "losc", "iosc";
278			#clock-cells = <1>;
279			#reset-cells = <1>;
280		};
281
282		dma: dma-controller@3002000 {
283			compatible = "allwinner,sun50i-h6-dma";
284			reg = <0x03002000 0x1000>;
285			interrupts = <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>;
286			clocks = <&ccu CLK_BUS_DMA>, <&ccu CLK_MBUS_DMA>;
287			clock-names = "bus", "mbus";
288			dma-channels = <16>;
289			dma-requests = <46>;
290			resets = <&ccu RST_BUS_DMA>;
291			#dma-cells = <1>;
292		};
293
294		msgbox: mailbox@3003000 {
295			compatible = "allwinner,sun50i-h6-msgbox",
296				     "allwinner,sun6i-a31-msgbox";
297			reg = <0x03003000 0x1000>;
298			clocks = <&ccu CLK_BUS_MSGBOX>;
299			resets = <&ccu RST_BUS_MSGBOX>;
300			interrupts = <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>;
301			#mbox-cells = <1>;
302		};
303
304		sid: efuse@3006000 {
305			compatible = "allwinner,sun50i-h6-sid";
306			reg = <0x03006000 0x400>;
307			#address-cells = <1>;
308			#size-cells = <1>;
309
310			ths_calibration: thermal-sensor-calibration@14 {
311				reg = <0x14 0x8>;
312			};
313
314			cpu_speed_grade: cpu-speed-grade@1c {
315				reg = <0x1c 0x4>;
316			};
317		};
318
319		timer@3009000 {
320			compatible = "allwinner,sun50i-h6-timer",
321				     "allwinner,sun8i-a23-timer";
322			reg = <0x03009000 0xa0>;
323			interrupts = <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>,
324				     <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>;
325			clocks = <&osc24M>;
326		};
327
328		watchdog: watchdog@30090a0 {
329			compatible = "allwinner,sun50i-h6-wdt",
330				     "allwinner,sun6i-a31-wdt";
331			reg = <0x030090a0 0x20>;
332			interrupts = <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>;
333			clocks = <&osc24M>;
334			/* Broken on some H6 boards */
335			status = "disabled";
336		};
337
338		pwm: pwm@300a000 {
339			compatible = "allwinner,sun50i-h6-pwm";
340			reg = <0x0300a000 0x400>;
341			clocks = <&osc24M>, <&ccu CLK_BUS_PWM>;
342			clock-names = "mod", "bus";
343			resets = <&ccu RST_BUS_PWM>;
344			#pwm-cells = <3>;
345			status = "disabled";
346		};
347
348		pio: pinctrl@300b000 {
349			compatible = "allwinner,sun50i-h6-pinctrl";
350			reg = <0x0300b000 0x400>;
351			interrupt-parent = <&r_intc>;
352			interrupts = <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>,
353				     <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>,
354				     <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>,
355				     <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>;
356			clocks = <&ccu CLK_APB1>, <&osc24M>, <&rtc CLK_OSC32K>;
357			clock-names = "apb", "hosc", "losc";
358			gpio-controller;
359			#gpio-cells = <3>;
360			interrupt-controller;
361			#interrupt-cells = <3>;
362
363			ext_rgmii_pins: rgmii-pins {
364				pins = "PD0", "PD1", "PD2", "PD3", "PD4",
365				       "PD5", "PD7", "PD8", "PD9", "PD10",
366				       "PD11", "PD12", "PD13", "PD19", "PD20";
367				function = "emac";
368				drive-strength = <40>;
369			};
370
371			hdmi_pins: hdmi-pins {
372				pins = "PH8", "PH9", "PH10";
373				function = "hdmi";
374			};
375
376			i2c0_pins: i2c0-pins {
377				pins = "PD25", "PD26";
378				function = "i2c0";
379			};
380
381			i2c1_pins: i2c1-pins {
382				pins = "PH5", "PH6";
383				function = "i2c1";
384			};
385
386			i2c2_pins: i2c2-pins {
387				pins = "PD23", "PD24";
388				function = "i2c2";
389			};
390
391			mmc0_pins: mmc0-pins {
392				pins = "PF0", "PF1", "PF2", "PF3",
393				       "PF4", "PF5";
394				function = "mmc0";
395				drive-strength = <30>;
396				bias-pull-up;
397			};
398
399			/omit-if-no-ref/
400			mmc1_pins: mmc1-pins {
401				pins = "PG0", "PG1", "PG2", "PG3",
402				       "PG4", "PG5";
403				function = "mmc1";
404				drive-strength = <30>;
405				bias-pull-up;
406			};
407
408			mmc2_pins: mmc2-pins {
409				pins = "PC1", "PC4", "PC5", "PC6",
410				       "PC7", "PC8", "PC9", "PC10",
411				       "PC11", "PC12", "PC13", "PC14";
412				function = "mmc2";
413				drive-strength = <30>;
414				bias-pull-up;
415			};
416
417			/omit-if-no-ref/
418			spi0_pins: spi0-pins {
419				pins = "PC0", "PC2", "PC3";
420				function = "spi0";
421			};
422
423			/* pin shared with MMC2-CMD (eMMC) */
424			/omit-if-no-ref/
425			spi0_cs_pin: spi0-cs-pin {
426				pins = "PC5";
427				function = "spi0";
428			};
429
430			/omit-if-no-ref/
431			spi1_pins: spi1-pins {
432				pins = "PH4", "PH5", "PH6";
433				function = "spi1";
434			};
435
436			/omit-if-no-ref/
437			spi1_cs_pin: spi1-cs-pin {
438				pins = "PH3";
439				function = "spi1";
440			};
441
442			/omit-if-no-ref/
443			spdif_tx_pin: spdif-tx-pin {
444				pins = "PH7";
445				function = "spdif";
446			};
447
448			uart0_ph_pins: uart0-ph-pins {
449				pins = "PH0", "PH1";
450				function = "uart0";
451			};
452
453			uart1_pins: uart1-pins {
454				pins = "PG6", "PG7";
455				function = "uart1";
456			};
457
458			uart1_rts_cts_pins: uart1-rts-cts-pins {
459				pins = "PG8", "PG9";
460				function = "uart1";
461			};
462		};
463
464		gic: interrupt-controller@3021000 {
465			compatible = "arm,gic-400";
466			reg = <0x03021000 0x1000>,
467			      <0x03022000 0x2000>,
468			      <0x03024000 0x2000>,
469			      <0x03026000 0x2000>;
470			interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
471			interrupt-controller;
472			#interrupt-cells = <3>;
473		};
474
475		iommu: iommu@30f0000 {
476			compatible = "allwinner,sun50i-h6-iommu";
477			reg = <0x030f0000 0x10000>;
478			interrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>;
479			clocks = <&ccu CLK_BUS_IOMMU>;
480			resets = <&ccu RST_BUS_IOMMU>;
481			#iommu-cells = <1>;
482		};
483
484		mmc0: mmc@4020000 {
485			compatible = "allwinner,sun50i-h6-mmc",
486				     "allwinner,sun50i-a64-mmc";
487			reg = <0x04020000 0x1000>;
488			clocks = <&ccu CLK_BUS_MMC0>, <&ccu CLK_MMC0>;
489			clock-names = "ahb", "mmc";
490			resets = <&ccu RST_BUS_MMC0>;
491			reset-names = "ahb";
492			interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>;
493			pinctrl-names = "default";
494			pinctrl-0 = <&mmc0_pins>;
495			max-frequency = <150000000>;
496			status = "disabled";
497			#address-cells = <1>;
498			#size-cells = <0>;
499		};
500
501		mmc1: mmc@4021000 {
502			compatible = "allwinner,sun50i-h6-mmc",
503				     "allwinner,sun50i-a64-mmc";
504			reg = <0x04021000 0x1000>;
505			clocks = <&ccu CLK_BUS_MMC1>, <&ccu CLK_MMC1>;
506			clock-names = "ahb", "mmc";
507			resets = <&ccu RST_BUS_MMC1>;
508			reset-names = "ahb";
509			interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
510			pinctrl-names = "default";
511			pinctrl-0 = <&mmc1_pins>;
512			max-frequency = <150000000>;
513			status = "disabled";
514			#address-cells = <1>;
515			#size-cells = <0>;
516		};
517
518		mmc2: mmc@4022000 {
519			compatible = "allwinner,sun50i-h6-emmc",
520				     "allwinner,sun50i-a64-emmc";
521			reg = <0x04022000 0x1000>;
522			clocks = <&ccu CLK_BUS_MMC2>, <&ccu CLK_MMC2>;
523			clock-names = "ahb", "mmc";
524			resets = <&ccu RST_BUS_MMC2>;
525			reset-names = "ahb";
526			interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
527			pinctrl-names = "default";
528			pinctrl-0 = <&mmc2_pins>;
529			max-frequency = <150000000>;
530			status = "disabled";
531			#address-cells = <1>;
532			#size-cells = <0>;
533		};
534
535		uart0: serial@5000000 {
536			compatible = "snps,dw-apb-uart";
537			reg = <0x05000000 0x400>;
538			interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>;
539			reg-shift = <2>;
540			reg-io-width = <4>;
541			clocks = <&ccu CLK_BUS_UART0>;
542			resets = <&ccu RST_BUS_UART0>;
543			status = "disabled";
544		};
545
546		uart1: serial@5000400 {
547			compatible = "snps,dw-apb-uart";
548			reg = <0x05000400 0x400>;
549			interrupts = <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>;
550			reg-shift = <2>;
551			reg-io-width = <4>;
552			clocks = <&ccu CLK_BUS_UART1>;
553			resets = <&ccu RST_BUS_UART1>;
554			status = "disabled";
555		};
556
557		uart2: serial@5000800 {
558			compatible = "snps,dw-apb-uart";
559			reg = <0x05000800 0x400>;
560			interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>;
561			reg-shift = <2>;
562			reg-io-width = <4>;
563			clocks = <&ccu CLK_BUS_UART2>;
564			resets = <&ccu RST_BUS_UART2>;
565			status = "disabled";
566		};
567
568		uart3: serial@5000c00 {
569			compatible = "snps,dw-apb-uart";
570			reg = <0x05000c00 0x400>;
571			interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>;
572			reg-shift = <2>;
573			reg-io-width = <4>;
574			clocks = <&ccu CLK_BUS_UART3>;
575			resets = <&ccu RST_BUS_UART3>;
576			status = "disabled";
577		};
578
579		i2c0: i2c@5002000 {
580			compatible = "allwinner,sun50i-h6-i2c",
581				     "allwinner,sun6i-a31-i2c";
582			reg = <0x05002000 0x400>;
583			interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>;
584			clocks = <&ccu CLK_BUS_I2C0>;
585			resets = <&ccu RST_BUS_I2C0>;
586			pinctrl-names = "default";
587			pinctrl-0 = <&i2c0_pins>;
588			status = "disabled";
589			#address-cells = <1>;
590			#size-cells = <0>;
591		};
592
593		i2c1: i2c@5002400 {
594			compatible = "allwinner,sun50i-h6-i2c",
595				     "allwinner,sun6i-a31-i2c";
596			reg = <0x05002400 0x400>;
597			interrupts = <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>;
598			clocks = <&ccu CLK_BUS_I2C1>;
599			resets = <&ccu RST_BUS_I2C1>;
600			pinctrl-names = "default";
601			pinctrl-0 = <&i2c1_pins>;
602			status = "disabled";
603			#address-cells = <1>;
604			#size-cells = <0>;
605		};
606
607		i2c2: i2c@5002800 {
608			compatible = "allwinner,sun50i-h6-i2c",
609				     "allwinner,sun6i-a31-i2c";
610			reg = <0x05002800 0x400>;
611			interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>;
612			clocks = <&ccu CLK_BUS_I2C2>;
613			resets = <&ccu RST_BUS_I2C2>;
614			pinctrl-names = "default";
615			pinctrl-0 = <&i2c2_pins>;
616			status = "disabled";
617			#address-cells = <1>;
618			#size-cells = <0>;
619		};
620
621		spi0: spi@5010000 {
622			compatible = "allwinner,sun50i-h6-spi",
623				     "allwinner,sun8i-h3-spi";
624			reg = <0x05010000 0x1000>;
625			interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
626			clocks = <&ccu CLK_BUS_SPI0>, <&ccu CLK_SPI0>;
627			clock-names = "ahb", "mod";
628			dmas = <&dma 22>, <&dma 22>;
629			dma-names = "rx", "tx";
630			resets = <&ccu RST_BUS_SPI0>;
631			status = "disabled";
632			#address-cells = <1>;
633			#size-cells = <0>;
634		};
635
636		spi1: spi@5011000 {
637			compatible = "allwinner,sun50i-h6-spi",
638				     "allwinner,sun8i-h3-spi";
639			reg = <0x05011000 0x1000>;
640			interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
641			clocks = <&ccu CLK_BUS_SPI1>, <&ccu CLK_SPI1>;
642			clock-names = "ahb", "mod";
643			dmas = <&dma 23>, <&dma 23>;
644			dma-names = "rx", "tx";
645			resets = <&ccu RST_BUS_SPI1>;
646			status = "disabled";
647			#address-cells = <1>;
648			#size-cells = <0>;
649		};
650
651		emac: ethernet@5020000 {
652			compatible = "allwinner,sun50i-h6-emac",
653				     "allwinner,sun50i-a64-emac";
654			syscon = <&syscon>;
655			reg = <0x05020000 0x10000>;
656			interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;
657			interrupt-names = "macirq";
658			resets = <&ccu RST_BUS_EMAC>;
659			reset-names = "stmmaceth";
660			clocks = <&ccu CLK_BUS_EMAC>;
661			clock-names = "stmmaceth";
662			status = "disabled";
663
664			mdio: mdio {
665				compatible = "snps,dwmac-mdio";
666				#address-cells = <1>;
667				#size-cells = <0>;
668			};
669		};
670
671		i2s1: i2s@5091000 {
672			#sound-dai-cells = <0>;
673			compatible = "allwinner,sun50i-h6-i2s";
674			reg = <0x05091000 0x1000>;
675			interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>;
676			clocks = <&ccu CLK_BUS_I2S1>, <&ccu CLK_I2S1>;
677			clock-names = "apb", "mod";
678			dmas = <&dma 4>, <&dma 4>;
679			resets = <&ccu RST_BUS_I2S1>;
680			dma-names = "rx", "tx";
681			status = "disabled";
682		};
683
684		spdif: spdif@5093000 {
685			#sound-dai-cells = <0>;
686			compatible = "allwinner,sun50i-h6-spdif";
687			reg = <0x05093000 0x400>;
688			interrupts = <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>;
689			clocks = <&ccu CLK_BUS_SPDIF>, <&ccu CLK_SPDIF>;
690			clock-names = "apb", "spdif";
691			resets = <&ccu RST_BUS_SPDIF>;
692			dmas = <&dma 2>, <&dma 2>;
693			dma-names = "rx", "tx";
694			status = "disabled";
695		};
696
697		usb2otg: usb@5100000 {
698			compatible = "allwinner,sun50i-h6-musb",
699				     "allwinner,sun8i-a33-musb";
700			reg = <0x05100000 0x0400>;
701			clocks = <&ccu CLK_BUS_OTG>;
702			resets = <&ccu RST_BUS_OTG>;
703			interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>;
704			interrupt-names = "mc";
705			phys = <&usb2phy 0>;
706			phy-names = "usb";
707			extcon = <&usb2phy 0>;
708			status = "disabled";
709		};
710
711		usb2phy: phy@5100400 {
712			compatible = "allwinner,sun50i-h6-usb-phy";
713			reg = <0x05100400 0x24>,
714			      <0x05101800 0x4>,
715			      <0x05311800 0x4>;
716			reg-names = "phy_ctrl",
717				    "pmu0",
718				    "pmu3";
719			clocks = <&ccu CLK_USB_PHY0>,
720				 <&ccu CLK_USB_PHY3>;
721			clock-names = "usb0_phy",
722				      "usb3_phy";
723			resets = <&ccu RST_USB_PHY0>,
724				 <&ccu RST_USB_PHY3>;
725			reset-names = "usb0_reset",
726				      "usb3_reset";
727			status = "disabled";
728			#phy-cells = <1>;
729		};
730
731		ehci0: usb@5101000 {
732			compatible = "allwinner,sun50i-h6-ehci", "generic-ehci";
733			reg = <0x05101000 0x100>;
734			interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>;
735			clocks = <&ccu CLK_BUS_OHCI0>,
736				 <&ccu CLK_BUS_EHCI0>,
737				 <&ccu CLK_USB_OHCI0>;
738			resets = <&ccu RST_BUS_OHCI0>,
739				 <&ccu RST_BUS_EHCI0>;
740			phys = <&usb2phy 0>;
741			phy-names = "usb";
742			status = "disabled";
743		};
744
745		ohci0: usb@5101400 {
746			compatible = "allwinner,sun50i-h6-ohci", "generic-ohci";
747			reg = <0x05101400 0x100>;
748			interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>;
749			clocks = <&ccu CLK_BUS_OHCI0>,
750				 <&ccu CLK_USB_OHCI0>;
751			resets = <&ccu RST_BUS_OHCI0>;
752			phys = <&usb2phy 0>;
753			phy-names = "usb";
754			status = "disabled";
755		};
756
757		dwc3: usb@5200000 {
758			compatible = "snps,dwc3";
759			reg = <0x05200000 0x10000>;
760			interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>;
761			clocks = <&ccu CLK_BUS_XHCI>,
762				 <&ccu CLK_BUS_XHCI>,
763				 <&rtc CLK_OSC32K>;
764			clock-names = "ref", "bus_early", "suspend";
765			resets = <&ccu RST_BUS_XHCI>;
766			/*
767			 * The datasheet of the chip doesn't declare the
768			 * peripheral function, and there's no boards known
769			 * to have a USB Type-B port routed to the port.
770			 * In addition, no one has tested the peripheral
771			 * function yet.
772			 * So set the dr_mode to "host" in the DTSI file.
773			 */
774			dr_mode = "host";
775			phys = <&usb3phy>;
776			phy-names = "usb3-phy";
777			status = "disabled";
778		};
779
780		usb3phy: phy@5210000 {
781			compatible = "allwinner,sun50i-h6-usb3-phy";
782			reg = <0x5210000 0x10000>;
783			clocks = <&ccu CLK_USB_PHY1>;
784			resets = <&ccu RST_USB_PHY1>;
785			#phy-cells = <0>;
786			status = "disabled";
787		};
788
789		ehci3: usb@5311000 {
790			compatible = "allwinner,sun50i-h6-ehci", "generic-ehci";
791			reg = <0x05311000 0x100>;
792			interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>;
793			clocks = <&ccu CLK_BUS_OHCI3>,
794				 <&ccu CLK_BUS_EHCI3>,
795				 <&ccu CLK_USB_OHCI3>;
796			resets = <&ccu RST_BUS_OHCI3>,
797				 <&ccu RST_BUS_EHCI3>;
798			phys = <&usb2phy 3>;
799			phy-names = "usb";
800			status = "disabled";
801		};
802
803		ohci3: usb@5311400 {
804			compatible = "allwinner,sun50i-h6-ohci", "generic-ohci";
805			reg = <0x05311400 0x100>;
806			interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>;
807			clocks = <&ccu CLK_BUS_OHCI3>,
808				 <&ccu CLK_USB_OHCI3>;
809			resets = <&ccu RST_BUS_OHCI3>;
810			phys = <&usb2phy 3>;
811			phy-names = "usb";
812			status = "disabled";
813		};
814
815		hdmi: hdmi@6000000 {
816			compatible = "allwinner,sun50i-h6-dw-hdmi";
817			reg = <0x06000000 0x10000>;
818			reg-io-width = <1>;
819			interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>;
820			clocks = <&ccu CLK_BUS_HDMI>, <&ccu CLK_HDMI_SLOW>,
821				 <&ccu CLK_HDMI>, <&ccu CLK_HDMI_CEC>,
822				 <&ccu CLK_HDCP>, <&ccu CLK_BUS_HDCP>;
823			clock-names = "iahb", "isfr", "tmds", "cec", "hdcp",
824				      "hdcp-bus";
825			resets = <&ccu RST_BUS_HDMI_SUB>, <&ccu RST_BUS_HDCP>;
826			reset-names = "ctrl", "hdcp";
827			phys = <&hdmi_phy>;
828			phy-names = "phy";
829			pinctrl-names = "default";
830			pinctrl-0 = <&hdmi_pins>;
831			status = "disabled";
832
833			ports {
834				#address-cells = <1>;
835				#size-cells = <0>;
836
837				hdmi_in: port@0 {
838					reg = <0>;
839
840					hdmi_in_tcon_top: endpoint {
841						remote-endpoint = <&tcon_top_hdmi_out_hdmi>;
842					};
843				};
844
845				hdmi_out: port@1 {
846					reg = <1>;
847				};
848			};
849		};
850
851		hdmi_phy: hdmi-phy@6010000 {
852			compatible = "allwinner,sun50i-h6-hdmi-phy";
853			reg = <0x06010000 0x10000>;
854			clocks = <&ccu CLK_BUS_HDMI>, <&ccu CLK_HDMI_SLOW>;
855			clock-names = "bus", "mod";
856			resets = <&ccu RST_BUS_HDMI>;
857			reset-names = "phy";
858			#phy-cells = <0>;
859		};
860
861		tcon_top: tcon-top@6510000 {
862			compatible = "allwinner,sun50i-h6-tcon-top";
863			reg = <0x06510000 0x1000>;
864			clocks = <&ccu CLK_BUS_TCON_TOP>,
865				 <&ccu CLK_TCON_TV0>;
866			clock-names = "bus",
867				      "tcon-tv0";
868			clock-output-names = "tcon-top-tv0";
869			resets = <&ccu RST_BUS_TCON_TOP>;
870			#clock-cells = <1>;
871
872			ports {
873				#address-cells = <1>;
874				#size-cells = <0>;
875
876				tcon_top_mixer0_in: port@0 {
877					#address-cells = <1>;
878					#size-cells = <0>;
879					reg = <0>;
880
881					tcon_top_mixer0_in_mixer0: endpoint@0 {
882						reg = <0>;
883						remote-endpoint = <&mixer0_out_tcon_top_mixer0>;
884					};
885				};
886
887				tcon_top_mixer0_out: port@1 {
888					#address-cells = <1>;
889					#size-cells = <0>;
890					reg = <1>;
891
892					tcon_top_mixer0_out_tcon_tv: endpoint@2 {
893						reg = <2>;
894						remote-endpoint = <&tcon_tv_in_tcon_top_mixer0>;
895					};
896				};
897
898				tcon_top_hdmi_in: port@4 {
899					#address-cells = <1>;
900					#size-cells = <0>;
901					reg = <4>;
902
903					tcon_top_hdmi_in_tcon_tv: endpoint@0 {
904						reg = <0>;
905						remote-endpoint = <&tcon_tv_out_tcon_top>;
906					};
907				};
908
909				tcon_top_hdmi_out: port@5 {
910					reg = <5>;
911
912					tcon_top_hdmi_out_hdmi: endpoint {
913						remote-endpoint = <&hdmi_in_tcon_top>;
914					};
915				};
916			};
917		};
918
919		tcon_tv: lcd-controller@6515000 {
920			compatible = "allwinner,sun50i-h6-tcon-tv",
921				     "allwinner,sun8i-r40-tcon-tv";
922			reg = <0x06515000 0x1000>;
923			interrupts = <GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH>;
924			clocks = <&ccu CLK_BUS_TCON_TV0>,
925				 <&tcon_top CLK_TCON_TOP_TV0>;
926			clock-names = "ahb",
927				      "tcon-ch1";
928			resets = <&ccu RST_BUS_TCON_TV0>;
929			reset-names = "lcd";
930
931			ports {
932				#address-cells = <1>;
933				#size-cells = <0>;
934
935				tcon_tv_in: port@0 {
936					reg = <0>;
937
938					tcon_tv_in_tcon_top_mixer0: endpoint {
939						remote-endpoint = <&tcon_top_mixer0_out_tcon_tv>;
940					};
941				};
942
943				tcon_tv_out: port@1 {
944					#address-cells = <1>;
945					#size-cells = <0>;
946					reg = <1>;
947
948					tcon_tv_out_tcon_top: endpoint@1 {
949						reg = <1>;
950						remote-endpoint = <&tcon_top_hdmi_in_tcon_tv>;
951					};
952				};
953			};
954		};
955
956		rtc: rtc@7000000 {
957			compatible = "allwinner,sun50i-h6-rtc";
958			reg = <0x07000000 0x400>;
959			interrupt-parent = <&r_intc>;
960			interrupts = <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>,
961				     <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>;
962			clock-output-names = "osc32k", "osc32k-out", "iosc";
963			#clock-cells = <1>;
964		};
965
966		r_ccu: clock@7010000 {
967			compatible = "allwinner,sun50i-h6-r-ccu";
968			reg = <0x07010000 0x400>;
969			clocks = <&osc24M>, <&rtc CLK_OSC32K>, <&rtc CLK_IOSC>,
970				 <&ccu CLK_PLL_PERIPH0>;
971			clock-names = "hosc", "losc", "iosc", "pll-periph";
972			#clock-cells = <1>;
973			#reset-cells = <1>;
974		};
975
976		r_watchdog: watchdog@7020400 {
977			compatible = "allwinner,sun50i-h6-wdt",
978				     "allwinner,sun6i-a31-wdt";
979			reg = <0x07020400 0x20>;
980			interrupts = <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>;
981			clocks = <&osc24M>;
982		};
983
984		r_intc: interrupt-controller@7021000 {
985			compatible = "allwinner,sun50i-h6-r-intc";
986			interrupt-controller;
987			#interrupt-cells = <3>;
988			reg = <0x07021000 0x400>;
989			interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>;
990		};
991
992		r_pio: pinctrl@7022000 {
993			compatible = "allwinner,sun50i-h6-r-pinctrl";
994			reg = <0x07022000 0x400>;
995			interrupt-parent = <&r_intc>;
996			interrupts = <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>,
997				     <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>;
998			clocks = <&r_ccu CLK_R_APB1>, <&osc24M>,
999				 <&rtc CLK_OSC32K>;
1000			clock-names = "apb", "hosc", "losc";
1001			gpio-controller;
1002			#gpio-cells = <3>;
1003			interrupt-controller;
1004			#interrupt-cells = <3>;
1005
1006			r_i2c_pins: r-i2c-pins {
1007				pins = "PL0", "PL1";
1008				function = "s_i2c";
1009			};
1010
1011			r_ir_rx_pin: r-ir-rx-pin {
1012				pins = "PL9";
1013				function = "s_cir_rx";
1014			};
1015
1016			r_rsb_pins: r-rsb-pins {
1017				pins = "PL0", "PL1";
1018				function = "s_rsb";
1019			};
1020		};
1021
1022		r_ir: ir@7040000 {
1023				compatible = "allwinner,sun50i-h6-ir",
1024					     "allwinner,sun6i-a31-ir";
1025				reg = <0x07040000 0x400>;
1026				interrupts = <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>;
1027				clocks = <&r_ccu CLK_R_APB1_IR>,
1028					 <&r_ccu CLK_IR>;
1029				clock-names = "apb", "ir";
1030				resets = <&r_ccu RST_R_APB1_IR>;
1031				pinctrl-names = "default";
1032				pinctrl-0 = <&r_ir_rx_pin>;
1033				status = "disabled";
1034		};
1035
1036		r_i2c: i2c@7081400 {
1037			compatible = "allwinner,sun50i-h6-i2c",
1038				     "allwinner,sun6i-a31-i2c";
1039			reg = <0x07081400 0x400>;
1040			interrupts = <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>;
1041			clocks = <&r_ccu CLK_R_APB2_I2C>;
1042			resets = <&r_ccu RST_R_APB2_I2C>;
1043			pinctrl-names = "default";
1044			pinctrl-0 = <&r_i2c_pins>;
1045			status = "disabled";
1046			#address-cells = <1>;
1047			#size-cells = <0>;
1048		};
1049
1050		r_rsb: rsb@7083000 {
1051			compatible = "allwinner,sun8i-a23-rsb";
1052			reg = <0x07083000 0x400>;
1053			interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>;
1054			clocks = <&r_ccu CLK_R_APB2_RSB>;
1055			clock-frequency = <3000000>;
1056			resets = <&r_ccu RST_R_APB2_RSB>;
1057			pinctrl-names = "default";
1058			pinctrl-0 = <&r_rsb_pins>;
1059			status = "disabled";
1060			#address-cells = <1>;
1061			#size-cells = <0>;
1062		};
1063
1064		ths: thermal-sensor@5070400 {
1065			compatible = "allwinner,sun50i-h6-ths";
1066			reg = <0x05070400 0x100>;
1067			interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>;
1068			clocks = <&ccu CLK_BUS_THS>;
1069			clock-names = "bus";
1070			resets = <&ccu RST_BUS_THS>;
1071			nvmem-cells = <&ths_calibration>;
1072			nvmem-cell-names = "calibration";
1073			#thermal-sensor-cells = <1>;
1074		};
1075	};
1076
1077	thermal-zones {
1078		cpu-thermal {
1079			polling-delay-passive = <0>;
1080			polling-delay = <0>;
1081			thermal-sensors = <&ths 0>;
1082
1083			trips {
1084				cpu_alert: cpu-alert {
1085					temperature = <85000>;
1086					hysteresis = <2000>;
1087					type = "passive";
1088				};
1089
1090				cpu-crit {
1091					temperature = <100000>;
1092					hysteresis = <0>;
1093					type = "critical";
1094				};
1095			};
1096
1097			cooling-maps {
1098				map0 {
1099					trip = <&cpu_alert>;
1100					cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
1101							 <&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
1102							 <&cpu2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
1103							 <&cpu3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
1104				};
1105			};
1106		};
1107
1108		gpu-thermal {
1109			polling-delay-passive = <1000>;
1110			polling-delay = <2000>;
1111			thermal-sensors = <&ths 1>;
1112
1113			trips {
1114				gpu_alert0: gpu-alert-0 {
1115					temperature = <95000>;
1116					hysteresis = <2000>;
1117					type = "passive";
1118				};
1119
1120				gpu_alert1: gpu-alert-1 {
1121					temperature = <100000>;
1122					hysteresis = <2000>;
1123					type = "passive";
1124				};
1125
1126				gpu_alert2: gpu-alert-2 {
1127					temperature = <105000>;
1128					hysteresis = <2000>;
1129					type = "passive";
1130				};
1131
1132				gpu-crit {
1133					temperature = <115000>;
1134					hysteresis = <0>;
1135					type = "critical";
1136				};
1137			};
1138
1139			cooling-maps {
1140				// Forbid the GPU to go over 756MHz
1141				map0 {
1142					trip = <&gpu_alert0>;
1143					cooling-device = <&gpu 1 THERMAL_NO_LIMIT>;
1144				};
1145
1146				// Forbid the GPU to go over 624MHz
1147				map1 {
1148					trip = <&gpu_alert1>;
1149					cooling-device = <&gpu 2 THERMAL_NO_LIMIT>;
1150				};
1151
1152				// Forbid the GPU to go over 576MHz
1153				map2 {
1154					trip = <&gpu_alert2>;
1155					cooling-device = <&gpu 3 THERMAL_NO_LIMIT>;
1156				};
1157			};
1158		};
1159	};
1160};
1161