1// SPDX-License-Identifier: GPL-2.0 2/* 3 * SDM845 SoC device tree source 4 * 5 * Copyright (c) 2018, The Linux Foundation. All rights reserved. 6 */ 7 8#include <dt-bindings/clock/qcom,camcc-sdm845.h> 9#include <dt-bindings/clock/qcom,dispcc-sdm845.h> 10#include <dt-bindings/clock/qcom,dsi-phy-28nm.h> 11#include <dt-bindings/clock/qcom,gcc-sdm845.h> 12#include <dt-bindings/clock/qcom,gpucc-sdm845.h> 13#include <dt-bindings/clock/qcom,lpass-sdm845.h> 14#include <dt-bindings/clock/qcom,rpmh.h> 15#include <dt-bindings/clock/qcom,videocc-sdm845.h> 16#include <dt-bindings/dma/qcom-gpi.h> 17#include <dt-bindings/firmware/qcom,scm.h> 18#include <dt-bindings/gpio/gpio.h> 19#include <dt-bindings/interconnect/qcom,icc.h> 20#include <dt-bindings/interconnect/qcom,osm-l3.h> 21#include <dt-bindings/interconnect/qcom,sdm845.h> 22#include <dt-bindings/interrupt-controller/arm-gic.h> 23#include <dt-bindings/phy/phy-qcom-qmp.h> 24#include <dt-bindings/phy/phy-qcom-qusb2.h> 25#include <dt-bindings/power/qcom-rpmpd.h> 26#include <dt-bindings/reset/qcom,sdm845-aoss.h> 27#include <dt-bindings/reset/qcom,sdm845-pdc.h> 28#include <dt-bindings/soc/qcom,apr.h> 29#include <dt-bindings/soc/qcom,rpmh-rsc.h> 30#include <dt-bindings/clock/qcom,gcc-sdm845.h> 31#include <dt-bindings/thermal/thermal.h> 32 33/ { 34 interrupt-parent = <&intc>; 35 36 #address-cells = <2>; 37 #size-cells = <2>; 38 39 aliases { 40 i2c0 = &i2c0; 41 i2c1 = &i2c1; 42 i2c2 = &i2c2; 43 i2c3 = &i2c3; 44 i2c4 = &i2c4; 45 i2c5 = &i2c5; 46 i2c6 = &i2c6; 47 i2c7 = &i2c7; 48 i2c8 = &i2c8; 49 i2c9 = &i2c9; 50 i2c10 = &i2c10; 51 i2c11 = &i2c11; 52 i2c12 = &i2c12; 53 i2c13 = &i2c13; 54 i2c14 = &i2c14; 55 i2c15 = &i2c15; 56 spi0 = &spi0; 57 spi1 = &spi1; 58 spi2 = &spi2; 59 spi3 = &spi3; 60 spi4 = &spi4; 61 spi5 = &spi5; 62 spi6 = &spi6; 63 spi7 = &spi7; 64 spi8 = &spi8; 65 spi9 = &spi9; 66 spi10 = &spi10; 67 spi11 = &spi11; 68 spi12 = &spi12; 69 spi13 = &spi13; 70 spi14 = &spi14; 71 spi15 = &spi15; 72 }; 73 74 chosen { }; 75 76 clocks { 77 xo_board: xo-board { 78 compatible = "fixed-clock"; 79 #clock-cells = <0>; 80 clock-frequency = <38400000>; 81 clock-output-names = "xo_board"; 82 }; 83 84 sleep_clk: sleep-clk { 85 compatible = "fixed-clock"; 86 #clock-cells = <0>; 87 clock-frequency = <32764>; 88 }; 89 }; 90 91 cpus: cpus { 92 #address-cells = <2>; 93 #size-cells = <0>; 94 95 cpu0: cpu@0 { 96 device_type = "cpu"; 97 compatible = "qcom,kryo385"; 98 reg = <0x0 0x0>; 99 clocks = <&cpufreq_hw 0>; 100 enable-method = "psci"; 101 capacity-dmips-mhz = <611>; 102 dynamic-power-coefficient = <154>; 103 qcom,freq-domain = <&cpufreq_hw 0>; 104 operating-points-v2 = <&cpu0_opp_table>; 105 interconnects = <&gladiator_noc MASTER_APPSS_PROC 3 &mem_noc SLAVE_EBI1 3>, 106 <&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>; 107 power-domains = <&cpu_pd0>; 108 power-domain-names = "psci"; 109 #cooling-cells = <2>; 110 next-level-cache = <&l2_0>; 111 l2_0: l2-cache { 112 compatible = "cache"; 113 cache-level = <2>; 114 cache-unified; 115 next-level-cache = <&l3_0>; 116 l3_0: l3-cache { 117 compatible = "cache"; 118 cache-level = <3>; 119 cache-unified; 120 }; 121 }; 122 }; 123 124 cpu1: cpu@100 { 125 device_type = "cpu"; 126 compatible = "qcom,kryo385"; 127 reg = <0x0 0x100>; 128 clocks = <&cpufreq_hw 0>; 129 enable-method = "psci"; 130 capacity-dmips-mhz = <611>; 131 dynamic-power-coefficient = <154>; 132 qcom,freq-domain = <&cpufreq_hw 0>; 133 operating-points-v2 = <&cpu0_opp_table>; 134 interconnects = <&gladiator_noc MASTER_APPSS_PROC 3 &mem_noc SLAVE_EBI1 3>, 135 <&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>; 136 power-domains = <&cpu_pd1>; 137 power-domain-names = "psci"; 138 #cooling-cells = <2>; 139 next-level-cache = <&l2_100>; 140 l2_100: l2-cache { 141 compatible = "cache"; 142 cache-level = <2>; 143 cache-unified; 144 next-level-cache = <&l3_0>; 145 }; 146 }; 147 148 cpu2: cpu@200 { 149 device_type = "cpu"; 150 compatible = "qcom,kryo385"; 151 reg = <0x0 0x200>; 152 clocks = <&cpufreq_hw 0>; 153 enable-method = "psci"; 154 capacity-dmips-mhz = <611>; 155 dynamic-power-coefficient = <154>; 156 qcom,freq-domain = <&cpufreq_hw 0>; 157 operating-points-v2 = <&cpu0_opp_table>; 158 interconnects = <&gladiator_noc MASTER_APPSS_PROC 3 &mem_noc SLAVE_EBI1 3>, 159 <&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>; 160 power-domains = <&cpu_pd2>; 161 power-domain-names = "psci"; 162 #cooling-cells = <2>; 163 next-level-cache = <&l2_200>; 164 l2_200: l2-cache { 165 compatible = "cache"; 166 cache-level = <2>; 167 cache-unified; 168 next-level-cache = <&l3_0>; 169 }; 170 }; 171 172 cpu3: cpu@300 { 173 device_type = "cpu"; 174 compatible = "qcom,kryo385"; 175 reg = <0x0 0x300>; 176 clocks = <&cpufreq_hw 0>; 177 enable-method = "psci"; 178 capacity-dmips-mhz = <611>; 179 dynamic-power-coefficient = <154>; 180 qcom,freq-domain = <&cpufreq_hw 0>; 181 operating-points-v2 = <&cpu0_opp_table>; 182 interconnects = <&gladiator_noc MASTER_APPSS_PROC 3 &mem_noc SLAVE_EBI1 3>, 183 <&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>; 184 #cooling-cells = <2>; 185 power-domains = <&cpu_pd3>; 186 power-domain-names = "psci"; 187 next-level-cache = <&l2_300>; 188 l2_300: l2-cache { 189 compatible = "cache"; 190 cache-level = <2>; 191 cache-unified; 192 next-level-cache = <&l3_0>; 193 }; 194 }; 195 196 cpu4: cpu@400 { 197 device_type = "cpu"; 198 compatible = "qcom,kryo385"; 199 reg = <0x0 0x400>; 200 clocks = <&cpufreq_hw 1>; 201 enable-method = "psci"; 202 capacity-dmips-mhz = <1024>; 203 dynamic-power-coefficient = <442>; 204 qcom,freq-domain = <&cpufreq_hw 1>; 205 operating-points-v2 = <&cpu4_opp_table>; 206 interconnects = <&gladiator_noc MASTER_APPSS_PROC 3 &mem_noc SLAVE_EBI1 3>, 207 <&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>; 208 power-domains = <&cpu_pd4>; 209 power-domain-names = "psci"; 210 #cooling-cells = <2>; 211 next-level-cache = <&l2_400>; 212 l2_400: l2-cache { 213 compatible = "cache"; 214 cache-level = <2>; 215 cache-unified; 216 next-level-cache = <&l3_0>; 217 }; 218 }; 219 220 cpu5: cpu@500 { 221 device_type = "cpu"; 222 compatible = "qcom,kryo385"; 223 reg = <0x0 0x500>; 224 clocks = <&cpufreq_hw 1>; 225 enable-method = "psci"; 226 capacity-dmips-mhz = <1024>; 227 dynamic-power-coefficient = <442>; 228 qcom,freq-domain = <&cpufreq_hw 1>; 229 operating-points-v2 = <&cpu4_opp_table>; 230 interconnects = <&gladiator_noc MASTER_APPSS_PROC 3 &mem_noc SLAVE_EBI1 3>, 231 <&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>; 232 power-domains = <&cpu_pd5>; 233 power-domain-names = "psci"; 234 #cooling-cells = <2>; 235 next-level-cache = <&l2_500>; 236 l2_500: l2-cache { 237 compatible = "cache"; 238 cache-level = <2>; 239 cache-unified; 240 next-level-cache = <&l3_0>; 241 }; 242 }; 243 244 cpu6: cpu@600 { 245 device_type = "cpu"; 246 compatible = "qcom,kryo385"; 247 reg = <0x0 0x600>; 248 clocks = <&cpufreq_hw 1>; 249 enable-method = "psci"; 250 capacity-dmips-mhz = <1024>; 251 dynamic-power-coefficient = <442>; 252 qcom,freq-domain = <&cpufreq_hw 1>; 253 operating-points-v2 = <&cpu4_opp_table>; 254 interconnects = <&gladiator_noc MASTER_APPSS_PROC 3 &mem_noc SLAVE_EBI1 3>, 255 <&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>; 256 power-domains = <&cpu_pd6>; 257 power-domain-names = "psci"; 258 #cooling-cells = <2>; 259 next-level-cache = <&l2_600>; 260 l2_600: l2-cache { 261 compatible = "cache"; 262 cache-level = <2>; 263 cache-unified; 264 next-level-cache = <&l3_0>; 265 }; 266 }; 267 268 cpu7: cpu@700 { 269 device_type = "cpu"; 270 compatible = "qcom,kryo385"; 271 reg = <0x0 0x700>; 272 clocks = <&cpufreq_hw 1>; 273 enable-method = "psci"; 274 capacity-dmips-mhz = <1024>; 275 dynamic-power-coefficient = <442>; 276 qcom,freq-domain = <&cpufreq_hw 1>; 277 operating-points-v2 = <&cpu4_opp_table>; 278 interconnects = <&gladiator_noc MASTER_APPSS_PROC 3 &mem_noc SLAVE_EBI1 3>, 279 <&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>; 280 power-domains = <&cpu_pd7>; 281 power-domain-names = "psci"; 282 #cooling-cells = <2>; 283 next-level-cache = <&l2_700>; 284 l2_700: l2-cache { 285 compatible = "cache"; 286 cache-level = <2>; 287 cache-unified; 288 next-level-cache = <&l3_0>; 289 }; 290 }; 291 292 cpu-map { 293 cluster0 { 294 core0 { 295 cpu = <&cpu0>; 296 }; 297 298 core1 { 299 cpu = <&cpu1>; 300 }; 301 302 core2 { 303 cpu = <&cpu2>; 304 }; 305 306 core3 { 307 cpu = <&cpu3>; 308 }; 309 310 core4 { 311 cpu = <&cpu4>; 312 }; 313 314 core5 { 315 cpu = <&cpu5>; 316 }; 317 318 core6 { 319 cpu = <&cpu6>; 320 }; 321 322 core7 { 323 cpu = <&cpu7>; 324 }; 325 }; 326 }; 327 328 cpu_idle_states: idle-states { 329 entry-method = "psci"; 330 331 little_cpu_sleep_0: cpu-sleep-0-0 { 332 compatible = "arm,idle-state"; 333 idle-state-name = "little-rail-power-collapse"; 334 arm,psci-suspend-param = <0x40000004>; 335 entry-latency-us = <350>; 336 exit-latency-us = <461>; 337 min-residency-us = <1890>; 338 local-timer-stop; 339 }; 340 341 big_cpu_sleep_0: cpu-sleep-1-0 { 342 compatible = "arm,idle-state"; 343 idle-state-name = "big-rail-power-collapse"; 344 arm,psci-suspend-param = <0x40000004>; 345 entry-latency-us = <264>; 346 exit-latency-us = <621>; 347 min-residency-us = <952>; 348 local-timer-stop; 349 }; 350 }; 351 352 domain-idle-states { 353 cluster_sleep_0: cluster-sleep-0 { 354 compatible = "domain-idle-state"; 355 arm,psci-suspend-param = <0x4100c244>; 356 entry-latency-us = <3263>; 357 exit-latency-us = <6562>; 358 min-residency-us = <9987>; 359 }; 360 }; 361 }; 362 363 firmware { 364 scm { 365 compatible = "qcom,scm-sdm845", "qcom,scm"; 366 }; 367 }; 368 369 memory@80000000 { 370 device_type = "memory"; 371 /* We expect the bootloader to fill in the size */ 372 reg = <0 0x80000000 0 0>; 373 }; 374 375 cpu0_opp_table: opp-table-cpu0 { 376 compatible = "operating-points-v2"; 377 opp-shared; 378 379 cpu0_opp1: opp-300000000 { 380 opp-hz = /bits/ 64 <300000000>; 381 opp-peak-kBps = <800000 4800000>; 382 }; 383 384 cpu0_opp2: opp-403200000 { 385 opp-hz = /bits/ 64 <403200000>; 386 opp-peak-kBps = <800000 4800000>; 387 }; 388 389 cpu0_opp3: opp-480000000 { 390 opp-hz = /bits/ 64 <480000000>; 391 opp-peak-kBps = <800000 6451200>; 392 }; 393 394 cpu0_opp4: opp-576000000 { 395 opp-hz = /bits/ 64 <576000000>; 396 opp-peak-kBps = <800000 6451200>; 397 }; 398 399 cpu0_opp5: opp-652800000 { 400 opp-hz = /bits/ 64 <652800000>; 401 opp-peak-kBps = <800000 7680000>; 402 }; 403 404 cpu0_opp6: opp-748800000 { 405 opp-hz = /bits/ 64 <748800000>; 406 opp-peak-kBps = <1804000 9216000>; 407 }; 408 409 cpu0_opp7: opp-825600000 { 410 opp-hz = /bits/ 64 <825600000>; 411 opp-peak-kBps = <1804000 9216000>; 412 }; 413 414 cpu0_opp8: opp-902400000 { 415 opp-hz = /bits/ 64 <902400000>; 416 opp-peak-kBps = <1804000 10444800>; 417 }; 418 419 cpu0_opp9: opp-979200000 { 420 opp-hz = /bits/ 64 <979200000>; 421 opp-peak-kBps = <1804000 11980800>; 422 }; 423 424 cpu0_opp10: opp-1056000000 { 425 opp-hz = /bits/ 64 <1056000000>; 426 opp-peak-kBps = <1804000 11980800>; 427 }; 428 429 cpu0_opp11: opp-1132800000 { 430 opp-hz = /bits/ 64 <1132800000>; 431 opp-peak-kBps = <2188000 13516800>; 432 }; 433 434 cpu0_opp12: opp-1228800000 { 435 opp-hz = /bits/ 64 <1228800000>; 436 opp-peak-kBps = <2188000 15052800>; 437 }; 438 439 cpu0_opp13: opp-1324800000 { 440 opp-hz = /bits/ 64 <1324800000>; 441 opp-peak-kBps = <2188000 16588800>; 442 }; 443 444 cpu0_opp14: opp-1420800000 { 445 opp-hz = /bits/ 64 <1420800000>; 446 opp-peak-kBps = <3072000 18124800>; 447 }; 448 449 cpu0_opp15: opp-1516800000 { 450 opp-hz = /bits/ 64 <1516800000>; 451 opp-peak-kBps = <3072000 19353600>; 452 }; 453 454 cpu0_opp16: opp-1612800000 { 455 opp-hz = /bits/ 64 <1612800000>; 456 opp-peak-kBps = <4068000 19353600>; 457 }; 458 459 cpu0_opp17: opp-1689600000 { 460 opp-hz = /bits/ 64 <1689600000>; 461 opp-peak-kBps = <4068000 20889600>; 462 }; 463 464 cpu0_opp18: opp-1766400000 { 465 opp-hz = /bits/ 64 <1766400000>; 466 opp-peak-kBps = <4068000 22425600>; 467 }; 468 }; 469 470 cpu4_opp_table: opp-table-cpu4 { 471 compatible = "operating-points-v2"; 472 opp-shared; 473 474 cpu4_opp1: opp-300000000 { 475 opp-hz = /bits/ 64 <300000000>; 476 opp-peak-kBps = <800000 4800000>; 477 }; 478 479 cpu4_opp2: opp-403200000 { 480 opp-hz = /bits/ 64 <403200000>; 481 opp-peak-kBps = <800000 4800000>; 482 }; 483 484 cpu4_opp3: opp-480000000 { 485 opp-hz = /bits/ 64 <480000000>; 486 opp-peak-kBps = <1804000 4800000>; 487 }; 488 489 cpu4_opp4: opp-576000000 { 490 opp-hz = /bits/ 64 <576000000>; 491 opp-peak-kBps = <1804000 4800000>; 492 }; 493 494 cpu4_opp5: opp-652800000 { 495 opp-hz = /bits/ 64 <652800000>; 496 opp-peak-kBps = <1804000 4800000>; 497 }; 498 499 cpu4_opp6: opp-748800000 { 500 opp-hz = /bits/ 64 <748800000>; 501 opp-peak-kBps = <1804000 4800000>; 502 }; 503 504 cpu4_opp7: opp-825600000 { 505 opp-hz = /bits/ 64 <825600000>; 506 opp-peak-kBps = <2188000 9216000>; 507 }; 508 509 cpu4_opp8: opp-902400000 { 510 opp-hz = /bits/ 64 <902400000>; 511 opp-peak-kBps = <2188000 9216000>; 512 }; 513 514 cpu4_opp9: opp-979200000 { 515 opp-hz = /bits/ 64 <979200000>; 516 opp-peak-kBps = <2188000 9216000>; 517 }; 518 519 cpu4_opp10: opp-1056000000 { 520 opp-hz = /bits/ 64 <1056000000>; 521 opp-peak-kBps = <3072000 9216000>; 522 }; 523 524 cpu4_opp11: opp-1132800000 { 525 opp-hz = /bits/ 64 <1132800000>; 526 opp-peak-kBps = <3072000 11980800>; 527 }; 528 529 cpu4_opp12: opp-1209600000 { 530 opp-hz = /bits/ 64 <1209600000>; 531 opp-peak-kBps = <4068000 11980800>; 532 }; 533 534 cpu4_opp13: opp-1286400000 { 535 opp-hz = /bits/ 64 <1286400000>; 536 opp-peak-kBps = <4068000 11980800>; 537 }; 538 539 cpu4_opp14: opp-1363200000 { 540 opp-hz = /bits/ 64 <1363200000>; 541 opp-peak-kBps = <4068000 15052800>; 542 }; 543 544 cpu4_opp15: opp-1459200000 { 545 opp-hz = /bits/ 64 <1459200000>; 546 opp-peak-kBps = <4068000 15052800>; 547 }; 548 549 cpu4_opp16: opp-1536000000 { 550 opp-hz = /bits/ 64 <1536000000>; 551 opp-peak-kBps = <5412000 15052800>; 552 }; 553 554 cpu4_opp17: opp-1612800000 { 555 opp-hz = /bits/ 64 <1612800000>; 556 opp-peak-kBps = <5412000 15052800>; 557 }; 558 559 cpu4_opp18: opp-1689600000 { 560 opp-hz = /bits/ 64 <1689600000>; 561 opp-peak-kBps = <5412000 19353600>; 562 }; 563 564 cpu4_opp19: opp-1766400000 { 565 opp-hz = /bits/ 64 <1766400000>; 566 opp-peak-kBps = <6220000 19353600>; 567 }; 568 569 cpu4_opp20: opp-1843200000 { 570 opp-hz = /bits/ 64 <1843200000>; 571 opp-peak-kBps = <6220000 19353600>; 572 }; 573 574 cpu4_opp21: opp-1920000000 { 575 opp-hz = /bits/ 64 <1920000000>; 576 opp-peak-kBps = <7216000 19353600>; 577 }; 578 579 cpu4_opp22: opp-1996800000 { 580 opp-hz = /bits/ 64 <1996800000>; 581 opp-peak-kBps = <7216000 20889600>; 582 }; 583 584 cpu4_opp23: opp-2092800000 { 585 opp-hz = /bits/ 64 <2092800000>; 586 opp-peak-kBps = <7216000 20889600>; 587 }; 588 589 cpu4_opp24: opp-2169600000 { 590 opp-hz = /bits/ 64 <2169600000>; 591 opp-peak-kBps = <7216000 20889600>; 592 }; 593 594 cpu4_opp25: opp-2246400000 { 595 opp-hz = /bits/ 64 <2246400000>; 596 opp-peak-kBps = <7216000 20889600>; 597 }; 598 599 cpu4_opp26: opp-2323200000 { 600 opp-hz = /bits/ 64 <2323200000>; 601 opp-peak-kBps = <7216000 20889600>; 602 }; 603 604 cpu4_opp27: opp-2400000000 { 605 opp-hz = /bits/ 64 <2400000000>; 606 opp-peak-kBps = <7216000 22425600>; 607 }; 608 609 cpu4_opp28: opp-2476800000 { 610 opp-hz = /bits/ 64 <2476800000>; 611 opp-peak-kBps = <7216000 22425600>; 612 }; 613 614 cpu4_opp29: opp-2553600000 { 615 opp-hz = /bits/ 64 <2553600000>; 616 opp-peak-kBps = <7216000 22425600>; 617 }; 618 619 cpu4_opp30: opp-2649600000 { 620 opp-hz = /bits/ 64 <2649600000>; 621 opp-peak-kBps = <7216000 22425600>; 622 }; 623 624 cpu4_opp31: opp-2745600000 { 625 opp-hz = /bits/ 64 <2745600000>; 626 opp-peak-kBps = <7216000 25497600>; 627 }; 628 629 cpu4_opp32: opp-2803200000 { 630 opp-hz = /bits/ 64 <2803200000>; 631 opp-peak-kBps = <7216000 25497600>; 632 }; 633 }; 634 635 dsi_opp_table: opp-table-dsi { 636 compatible = "operating-points-v2"; 637 638 opp-19200000 { 639 opp-hz = /bits/ 64 <19200000>; 640 required-opps = <&rpmhpd_opp_min_svs>; 641 }; 642 643 opp-180000000 { 644 opp-hz = /bits/ 64 <180000000>; 645 required-opps = <&rpmhpd_opp_low_svs>; 646 }; 647 648 opp-275000000 { 649 opp-hz = /bits/ 64 <275000000>; 650 required-opps = <&rpmhpd_opp_svs>; 651 }; 652 653 opp-328580000 { 654 opp-hz = /bits/ 64 <328580000>; 655 required-opps = <&rpmhpd_opp_svs_l1>; 656 }; 657 658 opp-358000000 { 659 opp-hz = /bits/ 64 <358000000>; 660 required-opps = <&rpmhpd_opp_nom>; 661 }; 662 }; 663 664 qspi_opp_table: opp-table-qspi { 665 compatible = "operating-points-v2"; 666 667 opp-19200000 { 668 opp-hz = /bits/ 64 <19200000>; 669 required-opps = <&rpmhpd_opp_min_svs>; 670 }; 671 672 opp-100000000 { 673 opp-hz = /bits/ 64 <100000000>; 674 required-opps = <&rpmhpd_opp_low_svs>; 675 }; 676 677 opp-150000000 { 678 opp-hz = /bits/ 64 <150000000>; 679 required-opps = <&rpmhpd_opp_svs>; 680 }; 681 682 opp-300000000 { 683 opp-hz = /bits/ 64 <300000000>; 684 required-opps = <&rpmhpd_opp_nom>; 685 }; 686 }; 687 688 qup_opp_table: opp-table-qup { 689 compatible = "operating-points-v2"; 690 691 opp-50000000 { 692 opp-hz = /bits/ 64 <50000000>; 693 required-opps = <&rpmhpd_opp_min_svs>; 694 }; 695 696 opp-75000000 { 697 opp-hz = /bits/ 64 <75000000>; 698 required-opps = <&rpmhpd_opp_low_svs>; 699 }; 700 701 opp-100000000 { 702 opp-hz = /bits/ 64 <100000000>; 703 required-opps = <&rpmhpd_opp_svs>; 704 }; 705 706 opp-128000000 { 707 opp-hz = /bits/ 64 <128000000>; 708 required-opps = <&rpmhpd_opp_nom>; 709 }; 710 }; 711 712 pmu { 713 compatible = "arm,armv8-pmuv3"; 714 interrupts = <GIC_PPI 5 IRQ_TYPE_LEVEL_HIGH>; 715 }; 716 717 psci: psci { 718 compatible = "arm,psci-1.0"; 719 method = "smc"; 720 721 cpu_pd0: power-domain-cpu0 { 722 #power-domain-cells = <0>; 723 power-domains = <&cluster_pd>; 724 domain-idle-states = <&little_cpu_sleep_0>; 725 }; 726 727 cpu_pd1: power-domain-cpu1 { 728 #power-domain-cells = <0>; 729 power-domains = <&cluster_pd>; 730 domain-idle-states = <&little_cpu_sleep_0>; 731 }; 732 733 cpu_pd2: power-domain-cpu2 { 734 #power-domain-cells = <0>; 735 power-domains = <&cluster_pd>; 736 domain-idle-states = <&little_cpu_sleep_0>; 737 }; 738 739 cpu_pd3: power-domain-cpu3 { 740 #power-domain-cells = <0>; 741 power-domains = <&cluster_pd>; 742 domain-idle-states = <&little_cpu_sleep_0>; 743 }; 744 745 cpu_pd4: power-domain-cpu4 { 746 #power-domain-cells = <0>; 747 power-domains = <&cluster_pd>; 748 domain-idle-states = <&big_cpu_sleep_0>; 749 }; 750 751 cpu_pd5: power-domain-cpu5 { 752 #power-domain-cells = <0>; 753 power-domains = <&cluster_pd>; 754 domain-idle-states = <&big_cpu_sleep_0>; 755 }; 756 757 cpu_pd6: power-domain-cpu6 { 758 #power-domain-cells = <0>; 759 power-domains = <&cluster_pd>; 760 domain-idle-states = <&big_cpu_sleep_0>; 761 }; 762 763 cpu_pd7: power-domain-cpu7 { 764 #power-domain-cells = <0>; 765 power-domains = <&cluster_pd>; 766 domain-idle-states = <&big_cpu_sleep_0>; 767 }; 768 769 cluster_pd: power-domain-cluster { 770 #power-domain-cells = <0>; 771 domain-idle-states = <&cluster_sleep_0>; 772 }; 773 }; 774 775 reserved-memory { 776 #address-cells = <2>; 777 #size-cells = <2>; 778 ranges; 779 780 hyp_mem: hyp-mem@85700000 { 781 reg = <0 0x85700000 0 0x600000>; 782 no-map; 783 }; 784 785 xbl_mem: xbl-mem@85e00000 { 786 reg = <0 0x85e00000 0 0x100000>; 787 no-map; 788 }; 789 790 aop_mem: aop-mem@85fc0000 { 791 reg = <0 0x85fc0000 0 0x20000>; 792 no-map; 793 }; 794 795 aop_cmd_db_mem: aop-cmd-db-mem@85fe0000 { 796 compatible = "qcom,cmd-db"; 797 reg = <0x0 0x85fe0000 0 0x20000>; 798 no-map; 799 }; 800 801 smem@86000000 { 802 compatible = "qcom,smem"; 803 reg = <0x0 0x86000000 0 0x200000>; 804 no-map; 805 hwlocks = <&tcsr_mutex 3>; 806 }; 807 808 tz_mem: tz@86200000 { 809 reg = <0 0x86200000 0 0x2d00000>; 810 no-map; 811 }; 812 813 rmtfs_mem: rmtfs@88f00000 { 814 compatible = "qcom,rmtfs-mem"; 815 reg = <0 0x88f00000 0 0x200000>; 816 no-map; 817 818 qcom,client-id = <1>; 819 qcom,vmid = <QCOM_SCM_VMID_MSS_MSA>; 820 }; 821 822 qseecom_mem: qseecom@8ab00000 { 823 reg = <0 0x8ab00000 0 0x1400000>; 824 no-map; 825 }; 826 827 camera_mem: camera-mem@8bf00000 { 828 reg = <0 0x8bf00000 0 0x500000>; 829 no-map; 830 }; 831 832 ipa_fw_mem: ipa-fw@8c400000 { 833 reg = <0 0x8c400000 0 0x10000>; 834 no-map; 835 }; 836 837 ipa_gsi_mem: ipa-gsi@8c410000 { 838 reg = <0 0x8c410000 0 0x5000>; 839 no-map; 840 }; 841 842 gpu_mem: gpu@8c415000 { 843 reg = <0 0x8c415000 0 0x2000>; 844 no-map; 845 }; 846 847 adsp_mem: adsp@8c500000 { 848 reg = <0 0x8c500000 0 0x1a00000>; 849 no-map; 850 }; 851 852 wlan_msa_mem: wlan-msa@8df00000 { 853 reg = <0 0x8df00000 0 0x100000>; 854 no-map; 855 }; 856 857 mpss_region: mpss@8e000000 { 858 reg = <0 0x8e000000 0 0x7800000>; 859 no-map; 860 }; 861 862 venus_mem: venus@95800000 { 863 reg = <0 0x95800000 0 0x500000>; 864 no-map; 865 }; 866 867 cdsp_mem: cdsp@95d00000 { 868 reg = <0 0x95d00000 0 0x800000>; 869 no-map; 870 }; 871 872 mba_region: mba@96500000 { 873 reg = <0 0x96500000 0 0x200000>; 874 no-map; 875 }; 876 877 slpi_mem: slpi@96700000 { 878 reg = <0 0x96700000 0 0x1400000>; 879 no-map; 880 }; 881 882 spss_mem: spss@97b00000 { 883 reg = <0 0x97b00000 0 0x100000>; 884 no-map; 885 }; 886 887 mdata_mem: mpss-metadata { 888 alloc-ranges = <0 0xa0000000 0 0x20000000>; 889 size = <0 0x4000>; 890 no-map; 891 }; 892 893 fastrpc_mem: fastrpc { 894 compatible = "shared-dma-pool"; 895 alloc-ranges = <0x0 0x00000000 0x0 0xffffffff>; 896 alignment = <0x0 0x400000>; 897 size = <0x0 0x1000000>; 898 reusable; 899 }; 900 }; 901 902 adsp_pas: remoteproc-adsp { 903 compatible = "qcom,sdm845-adsp-pas"; 904 905 interrupts-extended = <&intc GIC_SPI 162 IRQ_TYPE_EDGE_RISING>, 906 <&adsp_smp2p_in 0 IRQ_TYPE_EDGE_RISING>, 907 <&adsp_smp2p_in 1 IRQ_TYPE_EDGE_RISING>, 908 <&adsp_smp2p_in 2 IRQ_TYPE_EDGE_RISING>, 909 <&adsp_smp2p_in 3 IRQ_TYPE_EDGE_RISING>; 910 interrupt-names = "wdog", "fatal", "ready", 911 "handover", "stop-ack"; 912 913 clocks = <&rpmhcc RPMH_CXO_CLK>; 914 clock-names = "xo"; 915 916 memory-region = <&adsp_mem>; 917 918 qcom,qmp = <&aoss_qmp>; 919 920 qcom,smem-states = <&adsp_smp2p_out 0>; 921 qcom,smem-state-names = "stop"; 922 923 status = "disabled"; 924 925 glink-edge { 926 interrupts = <GIC_SPI 156 IRQ_TYPE_EDGE_RISING>; 927 label = "lpass"; 928 qcom,remote-pid = <2>; 929 mboxes = <&apss_shared 8>; 930 931 apr { 932 compatible = "qcom,apr-v2"; 933 qcom,glink-channels = "apr_audio_svc"; 934 qcom,domain = <APR_DOMAIN_ADSP>; 935 #address-cells = <1>; 936 #size-cells = <0>; 937 qcom,intents = <512 20>; 938 939 service@3 { 940 reg = <APR_SVC_ADSP_CORE>; 941 compatible = "qcom,q6core"; 942 qcom,protection-domain = "avs/audio", "msm/adsp/audio_pd"; 943 }; 944 945 q6afe: service@4 { 946 compatible = "qcom,q6afe"; 947 reg = <APR_SVC_AFE>; 948 qcom,protection-domain = "avs/audio", "msm/adsp/audio_pd"; 949 q6afedai: dais { 950 compatible = "qcom,q6afe-dais"; 951 #address-cells = <1>; 952 #size-cells = <0>; 953 #sound-dai-cells = <1>; 954 }; 955 }; 956 957 q6asm: service@7 { 958 compatible = "qcom,q6asm"; 959 reg = <APR_SVC_ASM>; 960 qcom,protection-domain = "avs/audio", "msm/adsp/audio_pd"; 961 q6asmdai: dais { 962 compatible = "qcom,q6asm-dais"; 963 #address-cells = <1>; 964 #size-cells = <0>; 965 #sound-dai-cells = <1>; 966 iommus = <&apps_smmu 0x1821 0x0>; 967 }; 968 }; 969 970 q6adm: service@8 { 971 compatible = "qcom,q6adm"; 972 reg = <APR_SVC_ADM>; 973 qcom,protection-domain = "avs/audio", "msm/adsp/audio_pd"; 974 q6routing: routing { 975 compatible = "qcom,q6adm-routing"; 976 #sound-dai-cells = <0>; 977 }; 978 }; 979 }; 980 981 fastrpc { 982 compatible = "qcom,fastrpc"; 983 qcom,glink-channels = "fastrpcglink-apps-dsp"; 984 label = "adsp"; 985 qcom,non-secure-domain; 986 #address-cells = <1>; 987 #size-cells = <0>; 988 989 compute-cb@3 { 990 compatible = "qcom,fastrpc-compute-cb"; 991 reg = <3>; 992 iommus = <&apps_smmu 0x1823 0x0>; 993 }; 994 995 compute-cb@4 { 996 compatible = "qcom,fastrpc-compute-cb"; 997 reg = <4>; 998 iommus = <&apps_smmu 0x1824 0x0>; 999 }; 1000 }; 1001 }; 1002 }; 1003 1004 cdsp_pas: remoteproc-cdsp { 1005 compatible = "qcom,sdm845-cdsp-pas"; 1006 1007 interrupts-extended = <&intc GIC_SPI 578 IRQ_TYPE_EDGE_RISING>, 1008 <&cdsp_smp2p_in 0 IRQ_TYPE_EDGE_RISING>, 1009 <&cdsp_smp2p_in 1 IRQ_TYPE_EDGE_RISING>, 1010 <&cdsp_smp2p_in 2 IRQ_TYPE_EDGE_RISING>, 1011 <&cdsp_smp2p_in 3 IRQ_TYPE_EDGE_RISING>; 1012 interrupt-names = "wdog", "fatal", "ready", 1013 "handover", "stop-ack"; 1014 1015 clocks = <&rpmhcc RPMH_CXO_CLK>; 1016 clock-names = "xo"; 1017 1018 memory-region = <&cdsp_mem>; 1019 1020 qcom,qmp = <&aoss_qmp>; 1021 1022 qcom,smem-states = <&cdsp_smp2p_out 0>; 1023 qcom,smem-state-names = "stop"; 1024 1025 status = "disabled"; 1026 1027 glink-edge { 1028 interrupts = <GIC_SPI 574 IRQ_TYPE_EDGE_RISING>; 1029 label = "turing"; 1030 qcom,remote-pid = <5>; 1031 mboxes = <&apss_shared 4>; 1032 fastrpc { 1033 compatible = "qcom,fastrpc"; 1034 qcom,glink-channels = "fastrpcglink-apps-dsp"; 1035 label = "cdsp"; 1036 qcom,non-secure-domain; 1037 #address-cells = <1>; 1038 #size-cells = <0>; 1039 1040 compute-cb@1 { 1041 compatible = "qcom,fastrpc-compute-cb"; 1042 reg = <1>; 1043 iommus = <&apps_smmu 0x1401 0x30>; 1044 }; 1045 1046 compute-cb@2 { 1047 compatible = "qcom,fastrpc-compute-cb"; 1048 reg = <2>; 1049 iommus = <&apps_smmu 0x1402 0x30>; 1050 }; 1051 1052 compute-cb@3 { 1053 compatible = "qcom,fastrpc-compute-cb"; 1054 reg = <3>; 1055 iommus = <&apps_smmu 0x1403 0x30>; 1056 }; 1057 1058 compute-cb@4 { 1059 compatible = "qcom,fastrpc-compute-cb"; 1060 reg = <4>; 1061 iommus = <&apps_smmu 0x1404 0x30>; 1062 }; 1063 1064 compute-cb@5 { 1065 compatible = "qcom,fastrpc-compute-cb"; 1066 reg = <5>; 1067 iommus = <&apps_smmu 0x1405 0x30>; 1068 }; 1069 1070 compute-cb@6 { 1071 compatible = "qcom,fastrpc-compute-cb"; 1072 reg = <6>; 1073 iommus = <&apps_smmu 0x1406 0x30>; 1074 }; 1075 1076 compute-cb@7 { 1077 compatible = "qcom,fastrpc-compute-cb"; 1078 reg = <7>; 1079 iommus = <&apps_smmu 0x1407 0x30>; 1080 }; 1081 1082 compute-cb@8 { 1083 compatible = "qcom,fastrpc-compute-cb"; 1084 reg = <8>; 1085 iommus = <&apps_smmu 0x1408 0x30>; 1086 }; 1087 }; 1088 }; 1089 }; 1090 1091 smp2p-cdsp { 1092 compatible = "qcom,smp2p"; 1093 qcom,smem = <94>, <432>; 1094 1095 interrupts = <GIC_SPI 576 IRQ_TYPE_EDGE_RISING>; 1096 1097 mboxes = <&apss_shared 6>; 1098 1099 qcom,local-pid = <0>; 1100 qcom,remote-pid = <5>; 1101 1102 cdsp_smp2p_out: master-kernel { 1103 qcom,entry-name = "master-kernel"; 1104 #qcom,smem-state-cells = <1>; 1105 }; 1106 1107 cdsp_smp2p_in: slave-kernel { 1108 qcom,entry-name = "slave-kernel"; 1109 1110 interrupt-controller; 1111 #interrupt-cells = <2>; 1112 }; 1113 }; 1114 1115 smp2p-lpass { 1116 compatible = "qcom,smp2p"; 1117 qcom,smem = <443>, <429>; 1118 1119 interrupts = <GIC_SPI 158 IRQ_TYPE_EDGE_RISING>; 1120 1121 mboxes = <&apss_shared 10>; 1122 1123 qcom,local-pid = <0>; 1124 qcom,remote-pid = <2>; 1125 1126 adsp_smp2p_out: master-kernel { 1127 qcom,entry-name = "master-kernel"; 1128 #qcom,smem-state-cells = <1>; 1129 }; 1130 1131 adsp_smp2p_in: slave-kernel { 1132 qcom,entry-name = "slave-kernel"; 1133 1134 interrupt-controller; 1135 #interrupt-cells = <2>; 1136 }; 1137 }; 1138 1139 smp2p-mpss { 1140 compatible = "qcom,smp2p"; 1141 qcom,smem = <435>, <428>; 1142 interrupts = <GIC_SPI 451 IRQ_TYPE_EDGE_RISING>; 1143 mboxes = <&apss_shared 14>; 1144 qcom,local-pid = <0>; 1145 qcom,remote-pid = <1>; 1146 1147 modem_smp2p_out: master-kernel { 1148 qcom,entry-name = "master-kernel"; 1149 #qcom,smem-state-cells = <1>; 1150 }; 1151 1152 modem_smp2p_in: slave-kernel { 1153 qcom,entry-name = "slave-kernel"; 1154 interrupt-controller; 1155 #interrupt-cells = <2>; 1156 }; 1157 1158 ipa_smp2p_out: ipa-ap-to-modem { 1159 qcom,entry-name = "ipa"; 1160 #qcom,smem-state-cells = <1>; 1161 }; 1162 1163 ipa_smp2p_in: ipa-modem-to-ap { 1164 qcom,entry-name = "ipa"; 1165 interrupt-controller; 1166 #interrupt-cells = <2>; 1167 }; 1168 }; 1169 1170 smp2p-slpi { 1171 compatible = "qcom,smp2p"; 1172 qcom,smem = <481>, <430>; 1173 interrupts = <GIC_SPI 172 IRQ_TYPE_EDGE_RISING>; 1174 mboxes = <&apss_shared 26>; 1175 qcom,local-pid = <0>; 1176 qcom,remote-pid = <3>; 1177 1178 slpi_smp2p_out: master-kernel { 1179 qcom,entry-name = "master-kernel"; 1180 #qcom,smem-state-cells = <1>; 1181 }; 1182 1183 slpi_smp2p_in: slave-kernel { 1184 qcom,entry-name = "slave-kernel"; 1185 interrupt-controller; 1186 #interrupt-cells = <2>; 1187 }; 1188 }; 1189 1190 soc: soc@0 { 1191 #address-cells = <2>; 1192 #size-cells = <2>; 1193 ranges = <0 0 0 0 0x10 0>; 1194 dma-ranges = <0 0 0 0 0x10 0>; 1195 compatible = "simple-bus"; 1196 1197 gcc: clock-controller@100000 { 1198 compatible = "qcom,gcc-sdm845"; 1199 reg = <0 0x00100000 0 0x1f0000>; 1200 clocks = <&rpmhcc RPMH_CXO_CLK>, 1201 <&rpmhcc RPMH_CXO_CLK_A>, 1202 <&sleep_clk>, 1203 <&pcie0_phy>, 1204 <&pcie1_phy>; 1205 clock-names = "bi_tcxo", 1206 "bi_tcxo_ao", 1207 "sleep_clk", 1208 "pcie_0_pipe_clk", 1209 "pcie_1_pipe_clk"; 1210 #clock-cells = <1>; 1211 #reset-cells = <1>; 1212 #power-domain-cells = <1>; 1213 power-domains = <&rpmhpd SDM845_CX>; 1214 }; 1215 1216 qfprom@784000 { 1217 compatible = "qcom,sdm845-qfprom", "qcom,qfprom"; 1218 reg = <0 0x00784000 0 0x8ff>; 1219 #address-cells = <1>; 1220 #size-cells = <1>; 1221 1222 qusb2p_hstx_trim: hstx-trim-primary@1eb { 1223 reg = <0x1eb 0x1>; 1224 bits = <1 4>; 1225 }; 1226 1227 qusb2s_hstx_trim: hstx-trim-secondary@1eb { 1228 reg = <0x1eb 0x2>; 1229 bits = <6 4>; 1230 }; 1231 }; 1232 1233 rng: rng@793000 { 1234 compatible = "qcom,prng-ee"; 1235 reg = <0 0x00793000 0 0x1000>; 1236 clocks = <&gcc GCC_PRNG_AHB_CLK>; 1237 clock-names = "core"; 1238 }; 1239 1240 gpi_dma0: dma-controller@800000 { 1241 #dma-cells = <3>; 1242 compatible = "qcom,sdm845-gpi-dma"; 1243 reg = <0 0x00800000 0 0x60000>; 1244 interrupts = <GIC_SPI 244 IRQ_TYPE_LEVEL_HIGH>, 1245 <GIC_SPI 245 IRQ_TYPE_LEVEL_HIGH>, 1246 <GIC_SPI 246 IRQ_TYPE_LEVEL_HIGH>, 1247 <GIC_SPI 247 IRQ_TYPE_LEVEL_HIGH>, 1248 <GIC_SPI 248 IRQ_TYPE_LEVEL_HIGH>, 1249 <GIC_SPI 249 IRQ_TYPE_LEVEL_HIGH>, 1250 <GIC_SPI 250 IRQ_TYPE_LEVEL_HIGH>, 1251 <GIC_SPI 251 IRQ_TYPE_LEVEL_HIGH>, 1252 <GIC_SPI 252 IRQ_TYPE_LEVEL_HIGH>, 1253 <GIC_SPI 253 IRQ_TYPE_LEVEL_HIGH>, 1254 <GIC_SPI 254 IRQ_TYPE_LEVEL_HIGH>, 1255 <GIC_SPI 255 IRQ_TYPE_LEVEL_HIGH>, 1256 <GIC_SPI 256 IRQ_TYPE_LEVEL_HIGH>; 1257 dma-channels = <13>; 1258 dma-channel-mask = <0xfa>; 1259 iommus = <&apps_smmu 0x0016 0x0>; 1260 status = "disabled"; 1261 }; 1262 1263 qupv3_id_0: geniqup@8c0000 { 1264 compatible = "qcom,geni-se-qup"; 1265 reg = <0 0x008c0000 0 0x6000>; 1266 clock-names = "m-ahb", "s-ahb"; 1267 clocks = <&gcc GCC_QUPV3_WRAP_0_M_AHB_CLK>, 1268 <&gcc GCC_QUPV3_WRAP_0_S_AHB_CLK>; 1269 iommus = <&apps_smmu 0x3 0x0>; 1270 #address-cells = <2>; 1271 #size-cells = <2>; 1272 ranges; 1273 interconnects = <&aggre1_noc MASTER_QUP_1 0 &config_noc SLAVE_BLSP_1 0>; 1274 interconnect-names = "qup-core"; 1275 status = "disabled"; 1276 1277 i2c0: i2c@880000 { 1278 compatible = "qcom,geni-i2c"; 1279 reg = <0 0x00880000 0 0x4000>; 1280 clock-names = "se"; 1281 clocks = <&gcc GCC_QUPV3_WRAP0_S0_CLK>; 1282 pinctrl-names = "default"; 1283 pinctrl-0 = <&qup_i2c0_default>; 1284 interrupts = <GIC_SPI 601 IRQ_TYPE_LEVEL_HIGH>; 1285 #address-cells = <1>; 1286 #size-cells = <0>; 1287 power-domains = <&rpmhpd SDM845_CX>; 1288 operating-points-v2 = <&qup_opp_table>; 1289 interconnects = <&aggre1_noc MASTER_QUP_1 0 &config_noc SLAVE_BLSP_1 0>, 1290 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_1 0>, 1291 <&aggre1_noc MASTER_QUP_1 0 &mem_noc SLAVE_EBI1 0>; 1292 interconnect-names = "qup-core", "qup-config", "qup-memory"; 1293 dmas = <&gpi_dma0 0 0 QCOM_GPI_I2C>, 1294 <&gpi_dma0 1 0 QCOM_GPI_I2C>; 1295 dma-names = "tx", "rx"; 1296 status = "disabled"; 1297 }; 1298 1299 spi0: spi@880000 { 1300 compatible = "qcom,geni-spi"; 1301 reg = <0 0x00880000 0 0x4000>; 1302 clock-names = "se"; 1303 clocks = <&gcc GCC_QUPV3_WRAP0_S0_CLK>; 1304 pinctrl-names = "default"; 1305 pinctrl-0 = <&qup_spi0_default>; 1306 interrupts = <GIC_SPI 601 IRQ_TYPE_LEVEL_HIGH>; 1307 #address-cells = <1>; 1308 #size-cells = <0>; 1309 interconnects = <&aggre1_noc MASTER_QUP_1 0 &config_noc SLAVE_BLSP_1 0>, 1310 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_1 0>; 1311 interconnect-names = "qup-core", "qup-config"; 1312 dmas = <&gpi_dma0 0 0 QCOM_GPI_SPI>, 1313 <&gpi_dma0 1 0 QCOM_GPI_SPI>; 1314 dma-names = "tx", "rx"; 1315 status = "disabled"; 1316 }; 1317 1318 uart0: serial@880000 { 1319 compatible = "qcom,geni-uart"; 1320 reg = <0 0x00880000 0 0x4000>; 1321 clock-names = "se"; 1322 clocks = <&gcc GCC_QUPV3_WRAP0_S0_CLK>; 1323 pinctrl-names = "default"; 1324 pinctrl-0 = <&qup_uart0_default>; 1325 interrupts = <GIC_SPI 601 IRQ_TYPE_LEVEL_HIGH>; 1326 power-domains = <&rpmhpd SDM845_CX>; 1327 operating-points-v2 = <&qup_opp_table>; 1328 interconnects = <&aggre1_noc MASTER_QUP_1 0 &config_noc SLAVE_BLSP_1 0>, 1329 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_1 0>; 1330 interconnect-names = "qup-core", "qup-config"; 1331 status = "disabled"; 1332 }; 1333 1334 i2c1: i2c@884000 { 1335 compatible = "qcom,geni-i2c"; 1336 reg = <0 0x00884000 0 0x4000>; 1337 clock-names = "se"; 1338 clocks = <&gcc GCC_QUPV3_WRAP0_S1_CLK>; 1339 pinctrl-names = "default"; 1340 pinctrl-0 = <&qup_i2c1_default>; 1341 interrupts = <GIC_SPI 602 IRQ_TYPE_LEVEL_HIGH>; 1342 #address-cells = <1>; 1343 #size-cells = <0>; 1344 power-domains = <&rpmhpd SDM845_CX>; 1345 operating-points-v2 = <&qup_opp_table>; 1346 interconnects = <&aggre1_noc MASTER_QUP_1 0 &config_noc SLAVE_BLSP_1 0>, 1347 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_1 0>, 1348 <&aggre1_noc MASTER_QUP_1 0 &mem_noc SLAVE_EBI1 0>; 1349 interconnect-names = "qup-core", "qup-config", "qup-memory"; 1350 dmas = <&gpi_dma0 0 1 QCOM_GPI_I2C>, 1351 <&gpi_dma0 1 1 QCOM_GPI_I2C>; 1352 dma-names = "tx", "rx"; 1353 status = "disabled"; 1354 }; 1355 1356 spi1: spi@884000 { 1357 compatible = "qcom,geni-spi"; 1358 reg = <0 0x00884000 0 0x4000>; 1359 clock-names = "se"; 1360 clocks = <&gcc GCC_QUPV3_WRAP0_S1_CLK>; 1361 pinctrl-names = "default"; 1362 pinctrl-0 = <&qup_spi1_default>; 1363 interrupts = <GIC_SPI 602 IRQ_TYPE_LEVEL_HIGH>; 1364 #address-cells = <1>; 1365 #size-cells = <0>; 1366 interconnects = <&aggre1_noc MASTER_QUP_1 0 &config_noc SLAVE_BLSP_1 0>, 1367 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_1 0>; 1368 interconnect-names = "qup-core", "qup-config"; 1369 dmas = <&gpi_dma0 0 1 QCOM_GPI_SPI>, 1370 <&gpi_dma0 1 1 QCOM_GPI_SPI>; 1371 dma-names = "tx", "rx"; 1372 status = "disabled"; 1373 }; 1374 1375 uart1: serial@884000 { 1376 compatible = "qcom,geni-uart"; 1377 reg = <0 0x00884000 0 0x4000>; 1378 clock-names = "se"; 1379 clocks = <&gcc GCC_QUPV3_WRAP0_S1_CLK>; 1380 pinctrl-names = "default"; 1381 pinctrl-0 = <&qup_uart1_default>; 1382 interrupts = <GIC_SPI 602 IRQ_TYPE_LEVEL_HIGH>; 1383 power-domains = <&rpmhpd SDM845_CX>; 1384 operating-points-v2 = <&qup_opp_table>; 1385 interconnects = <&aggre1_noc MASTER_QUP_1 0 &config_noc SLAVE_BLSP_1 0>, 1386 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_1 0>; 1387 interconnect-names = "qup-core", "qup-config"; 1388 status = "disabled"; 1389 }; 1390 1391 i2c2: i2c@888000 { 1392 compatible = "qcom,geni-i2c"; 1393 reg = <0 0x00888000 0 0x4000>; 1394 clock-names = "se"; 1395 clocks = <&gcc GCC_QUPV3_WRAP0_S2_CLK>; 1396 pinctrl-names = "default"; 1397 pinctrl-0 = <&qup_i2c2_default>; 1398 interrupts = <GIC_SPI 603 IRQ_TYPE_LEVEL_HIGH>; 1399 #address-cells = <1>; 1400 #size-cells = <0>; 1401 power-domains = <&rpmhpd SDM845_CX>; 1402 operating-points-v2 = <&qup_opp_table>; 1403 interconnects = <&aggre1_noc MASTER_QUP_1 0 &config_noc SLAVE_BLSP_1 0>, 1404 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_1 0>, 1405 <&aggre1_noc MASTER_QUP_1 0 &mem_noc SLAVE_EBI1 0>; 1406 interconnect-names = "qup-core", "qup-config", "qup-memory"; 1407 dmas = <&gpi_dma0 0 2 QCOM_GPI_I2C>, 1408 <&gpi_dma0 1 2 QCOM_GPI_I2C>; 1409 dma-names = "tx", "rx"; 1410 status = "disabled"; 1411 }; 1412 1413 spi2: spi@888000 { 1414 compatible = "qcom,geni-spi"; 1415 reg = <0 0x00888000 0 0x4000>; 1416 clock-names = "se"; 1417 clocks = <&gcc GCC_QUPV3_WRAP0_S2_CLK>; 1418 pinctrl-names = "default"; 1419 pinctrl-0 = <&qup_spi2_default>; 1420 interrupts = <GIC_SPI 603 IRQ_TYPE_LEVEL_HIGH>; 1421 #address-cells = <1>; 1422 #size-cells = <0>; 1423 interconnects = <&aggre1_noc MASTER_QUP_1 0 &config_noc SLAVE_BLSP_1 0>, 1424 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_1 0>; 1425 interconnect-names = "qup-core", "qup-config"; 1426 dmas = <&gpi_dma0 0 2 QCOM_GPI_SPI>, 1427 <&gpi_dma0 1 2 QCOM_GPI_SPI>; 1428 dma-names = "tx", "rx"; 1429 status = "disabled"; 1430 }; 1431 1432 uart2: serial@888000 { 1433 compatible = "qcom,geni-uart"; 1434 reg = <0 0x00888000 0 0x4000>; 1435 clock-names = "se"; 1436 clocks = <&gcc GCC_QUPV3_WRAP0_S2_CLK>; 1437 pinctrl-names = "default"; 1438 pinctrl-0 = <&qup_uart2_default>; 1439 interrupts = <GIC_SPI 603 IRQ_TYPE_LEVEL_HIGH>; 1440 power-domains = <&rpmhpd SDM845_CX>; 1441 operating-points-v2 = <&qup_opp_table>; 1442 interconnects = <&aggre1_noc MASTER_QUP_1 0 &config_noc SLAVE_BLSP_1 0>, 1443 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_1 0>; 1444 interconnect-names = "qup-core", "qup-config"; 1445 status = "disabled"; 1446 }; 1447 1448 i2c3: i2c@88c000 { 1449 compatible = "qcom,geni-i2c"; 1450 reg = <0 0x0088c000 0 0x4000>; 1451 clock-names = "se"; 1452 clocks = <&gcc GCC_QUPV3_WRAP0_S3_CLK>; 1453 pinctrl-names = "default"; 1454 pinctrl-0 = <&qup_i2c3_default>; 1455 interrupts = <GIC_SPI 604 IRQ_TYPE_LEVEL_HIGH>; 1456 #address-cells = <1>; 1457 #size-cells = <0>; 1458 power-domains = <&rpmhpd SDM845_CX>; 1459 operating-points-v2 = <&qup_opp_table>; 1460 interconnects = <&aggre1_noc MASTER_QUP_1 0 &config_noc SLAVE_BLSP_1 0>, 1461 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_1 0>, 1462 <&aggre1_noc MASTER_QUP_1 0 &mem_noc SLAVE_EBI1 0>; 1463 interconnect-names = "qup-core", "qup-config", "qup-memory"; 1464 dmas = <&gpi_dma0 0 3 QCOM_GPI_I2C>, 1465 <&gpi_dma0 1 3 QCOM_GPI_I2C>; 1466 dma-names = "tx", "rx"; 1467 status = "disabled"; 1468 }; 1469 1470 spi3: spi@88c000 { 1471 compatible = "qcom,geni-spi"; 1472 reg = <0 0x0088c000 0 0x4000>; 1473 clock-names = "se"; 1474 clocks = <&gcc GCC_QUPV3_WRAP0_S3_CLK>; 1475 pinctrl-names = "default"; 1476 pinctrl-0 = <&qup_spi3_default>; 1477 interrupts = <GIC_SPI 604 IRQ_TYPE_LEVEL_HIGH>; 1478 #address-cells = <1>; 1479 #size-cells = <0>; 1480 interconnects = <&aggre1_noc MASTER_QUP_1 0 &config_noc SLAVE_BLSP_1 0>, 1481 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_1 0>; 1482 interconnect-names = "qup-core", "qup-config"; 1483 dmas = <&gpi_dma0 0 3 QCOM_GPI_SPI>, 1484 <&gpi_dma0 1 3 QCOM_GPI_SPI>; 1485 dma-names = "tx", "rx"; 1486 status = "disabled"; 1487 }; 1488 1489 uart3: serial@88c000 { 1490 compatible = "qcom,geni-uart"; 1491 reg = <0 0x0088c000 0 0x4000>; 1492 clock-names = "se"; 1493 clocks = <&gcc GCC_QUPV3_WRAP0_S3_CLK>; 1494 pinctrl-names = "default"; 1495 pinctrl-0 = <&qup_uart3_default>; 1496 interrupts = <GIC_SPI 604 IRQ_TYPE_LEVEL_HIGH>; 1497 power-domains = <&rpmhpd SDM845_CX>; 1498 operating-points-v2 = <&qup_opp_table>; 1499 interconnects = <&aggre1_noc MASTER_QUP_1 0 &config_noc SLAVE_BLSP_1 0>, 1500 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_1 0>; 1501 interconnect-names = "qup-core", "qup-config"; 1502 status = "disabled"; 1503 }; 1504 1505 i2c4: i2c@890000 { 1506 compatible = "qcom,geni-i2c"; 1507 reg = <0 0x00890000 0 0x4000>; 1508 clock-names = "se"; 1509 clocks = <&gcc GCC_QUPV3_WRAP0_S4_CLK>; 1510 pinctrl-names = "default"; 1511 pinctrl-0 = <&qup_i2c4_default>; 1512 interrupts = <GIC_SPI 605 IRQ_TYPE_LEVEL_HIGH>; 1513 #address-cells = <1>; 1514 #size-cells = <0>; 1515 power-domains = <&rpmhpd SDM845_CX>; 1516 operating-points-v2 = <&qup_opp_table>; 1517 interconnects = <&aggre1_noc MASTER_QUP_1 0 &config_noc SLAVE_BLSP_1 0>, 1518 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_1 0>, 1519 <&aggre1_noc MASTER_QUP_1 0 &mem_noc SLAVE_EBI1 0>; 1520 interconnect-names = "qup-core", "qup-config", "qup-memory"; 1521 dmas = <&gpi_dma0 0 4 QCOM_GPI_I2C>, 1522 <&gpi_dma0 1 4 QCOM_GPI_I2C>; 1523 dma-names = "tx", "rx"; 1524 status = "disabled"; 1525 }; 1526 1527 spi4: spi@890000 { 1528 compatible = "qcom,geni-spi"; 1529 reg = <0 0x00890000 0 0x4000>; 1530 clock-names = "se"; 1531 clocks = <&gcc GCC_QUPV3_WRAP0_S4_CLK>; 1532 pinctrl-names = "default"; 1533 pinctrl-0 = <&qup_spi4_default>; 1534 interrupts = <GIC_SPI 605 IRQ_TYPE_LEVEL_HIGH>; 1535 #address-cells = <1>; 1536 #size-cells = <0>; 1537 interconnects = <&aggre1_noc MASTER_QUP_1 0 &config_noc SLAVE_BLSP_1 0>, 1538 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_1 0>; 1539 interconnect-names = "qup-core", "qup-config"; 1540 dmas = <&gpi_dma0 0 4 QCOM_GPI_SPI>, 1541 <&gpi_dma0 1 4 QCOM_GPI_SPI>; 1542 dma-names = "tx", "rx"; 1543 status = "disabled"; 1544 }; 1545 1546 uart4: serial@890000 { 1547 compatible = "qcom,geni-uart"; 1548 reg = <0 0x00890000 0 0x4000>; 1549 clock-names = "se"; 1550 clocks = <&gcc GCC_QUPV3_WRAP0_S4_CLK>; 1551 pinctrl-names = "default"; 1552 pinctrl-0 = <&qup_uart4_default>; 1553 interrupts = <GIC_SPI 605 IRQ_TYPE_LEVEL_HIGH>; 1554 power-domains = <&rpmhpd SDM845_CX>; 1555 operating-points-v2 = <&qup_opp_table>; 1556 interconnects = <&aggre1_noc MASTER_QUP_1 0 &config_noc SLAVE_BLSP_1 0>, 1557 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_1 0>; 1558 interconnect-names = "qup-core", "qup-config"; 1559 status = "disabled"; 1560 }; 1561 1562 i2c5: i2c@894000 { 1563 compatible = "qcom,geni-i2c"; 1564 reg = <0 0x00894000 0 0x4000>; 1565 clock-names = "se"; 1566 clocks = <&gcc GCC_QUPV3_WRAP0_S5_CLK>; 1567 pinctrl-names = "default"; 1568 pinctrl-0 = <&qup_i2c5_default>; 1569 interrupts = <GIC_SPI 606 IRQ_TYPE_LEVEL_HIGH>; 1570 #address-cells = <1>; 1571 #size-cells = <0>; 1572 power-domains = <&rpmhpd SDM845_CX>; 1573 operating-points-v2 = <&qup_opp_table>; 1574 interconnects = <&aggre1_noc MASTER_QUP_1 0 &config_noc SLAVE_BLSP_1 0>, 1575 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_1 0>, 1576 <&aggre1_noc MASTER_QUP_1 0 &mem_noc SLAVE_EBI1 0>; 1577 interconnect-names = "qup-core", "qup-config", "qup-memory"; 1578 dmas = <&gpi_dma0 0 5 QCOM_GPI_I2C>, 1579 <&gpi_dma0 1 5 QCOM_GPI_I2C>; 1580 dma-names = "tx", "rx"; 1581 status = "disabled"; 1582 }; 1583 1584 spi5: spi@894000 { 1585 compatible = "qcom,geni-spi"; 1586 reg = <0 0x00894000 0 0x4000>; 1587 clock-names = "se"; 1588 clocks = <&gcc GCC_QUPV3_WRAP0_S5_CLK>; 1589 pinctrl-names = "default"; 1590 pinctrl-0 = <&qup_spi5_default>; 1591 interrupts = <GIC_SPI 606 IRQ_TYPE_LEVEL_HIGH>; 1592 #address-cells = <1>; 1593 #size-cells = <0>; 1594 interconnects = <&aggre1_noc MASTER_QUP_1 0 &config_noc SLAVE_BLSP_1 0>, 1595 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_1 0>; 1596 interconnect-names = "qup-core", "qup-config"; 1597 dmas = <&gpi_dma0 0 5 QCOM_GPI_SPI>, 1598 <&gpi_dma0 1 5 QCOM_GPI_SPI>; 1599 dma-names = "tx", "rx"; 1600 status = "disabled"; 1601 }; 1602 1603 uart5: serial@894000 { 1604 compatible = "qcom,geni-uart"; 1605 reg = <0 0x00894000 0 0x4000>; 1606 clock-names = "se"; 1607 clocks = <&gcc GCC_QUPV3_WRAP0_S5_CLK>; 1608 pinctrl-names = "default"; 1609 pinctrl-0 = <&qup_uart5_default>; 1610 interrupts = <GIC_SPI 606 IRQ_TYPE_LEVEL_HIGH>; 1611 power-domains = <&rpmhpd SDM845_CX>; 1612 operating-points-v2 = <&qup_opp_table>; 1613 interconnects = <&aggre1_noc MASTER_QUP_1 0 &config_noc SLAVE_BLSP_1 0>, 1614 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_1 0>; 1615 interconnect-names = "qup-core", "qup-config"; 1616 status = "disabled"; 1617 }; 1618 1619 i2c6: i2c@898000 { 1620 compatible = "qcom,geni-i2c"; 1621 reg = <0 0x00898000 0 0x4000>; 1622 clock-names = "se"; 1623 clocks = <&gcc GCC_QUPV3_WRAP0_S6_CLK>; 1624 pinctrl-names = "default"; 1625 pinctrl-0 = <&qup_i2c6_default>; 1626 interrupts = <GIC_SPI 607 IRQ_TYPE_LEVEL_HIGH>; 1627 #address-cells = <1>; 1628 #size-cells = <0>; 1629 power-domains = <&rpmhpd SDM845_CX>; 1630 operating-points-v2 = <&qup_opp_table>; 1631 interconnects = <&aggre1_noc MASTER_QUP_1 0 &config_noc SLAVE_BLSP_1 0>, 1632 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_1 0>, 1633 <&aggre1_noc MASTER_QUP_1 0 &mem_noc SLAVE_EBI1 0>; 1634 interconnect-names = "qup-core", "qup-config", "qup-memory"; 1635 dmas = <&gpi_dma0 0 6 QCOM_GPI_I2C>, 1636 <&gpi_dma0 1 6 QCOM_GPI_I2C>; 1637 dma-names = "tx", "rx"; 1638 status = "disabled"; 1639 }; 1640 1641 spi6: spi@898000 { 1642 compatible = "qcom,geni-spi"; 1643 reg = <0 0x00898000 0 0x4000>; 1644 clock-names = "se"; 1645 clocks = <&gcc GCC_QUPV3_WRAP0_S6_CLK>; 1646 pinctrl-names = "default"; 1647 pinctrl-0 = <&qup_spi6_default>; 1648 interrupts = <GIC_SPI 607 IRQ_TYPE_LEVEL_HIGH>; 1649 #address-cells = <1>; 1650 #size-cells = <0>; 1651 interconnects = <&aggre1_noc MASTER_QUP_1 0 &config_noc SLAVE_BLSP_1 0>, 1652 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_1 0>; 1653 interconnect-names = "qup-core", "qup-config"; 1654 dmas = <&gpi_dma0 0 6 QCOM_GPI_SPI>, 1655 <&gpi_dma0 1 6 QCOM_GPI_SPI>; 1656 dma-names = "tx", "rx"; 1657 status = "disabled"; 1658 }; 1659 1660 uart6: serial@898000 { 1661 compatible = "qcom,geni-uart"; 1662 reg = <0 0x00898000 0 0x4000>; 1663 clock-names = "se"; 1664 clocks = <&gcc GCC_QUPV3_WRAP0_S6_CLK>; 1665 pinctrl-names = "default"; 1666 pinctrl-0 = <&qup_uart6_default>; 1667 interrupts = <GIC_SPI 607 IRQ_TYPE_LEVEL_HIGH>; 1668 power-domains = <&rpmhpd SDM845_CX>; 1669 operating-points-v2 = <&qup_opp_table>; 1670 interconnects = <&aggre1_noc MASTER_QUP_1 0 &config_noc SLAVE_BLSP_1 0>, 1671 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_1 0>; 1672 interconnect-names = "qup-core", "qup-config"; 1673 status = "disabled"; 1674 }; 1675 1676 i2c7: i2c@89c000 { 1677 compatible = "qcom,geni-i2c"; 1678 reg = <0 0x0089c000 0 0x4000>; 1679 clock-names = "se"; 1680 clocks = <&gcc GCC_QUPV3_WRAP0_S7_CLK>; 1681 pinctrl-names = "default"; 1682 pinctrl-0 = <&qup_i2c7_default>; 1683 interrupts = <GIC_SPI 608 IRQ_TYPE_LEVEL_HIGH>; 1684 #address-cells = <1>; 1685 #size-cells = <0>; 1686 power-domains = <&rpmhpd SDM845_CX>; 1687 operating-points-v2 = <&qup_opp_table>; 1688 status = "disabled"; 1689 }; 1690 1691 spi7: spi@89c000 { 1692 compatible = "qcom,geni-spi"; 1693 reg = <0 0x0089c000 0 0x4000>; 1694 clock-names = "se"; 1695 clocks = <&gcc GCC_QUPV3_WRAP0_S7_CLK>; 1696 pinctrl-names = "default"; 1697 pinctrl-0 = <&qup_spi7_default>; 1698 interrupts = <GIC_SPI 608 IRQ_TYPE_LEVEL_HIGH>; 1699 #address-cells = <1>; 1700 #size-cells = <0>; 1701 interconnects = <&aggre1_noc MASTER_QUP_1 0 &config_noc SLAVE_BLSP_1 0>, 1702 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_1 0>; 1703 interconnect-names = "qup-core", "qup-config"; 1704 dmas = <&gpi_dma0 0 7 QCOM_GPI_SPI>, 1705 <&gpi_dma0 1 7 QCOM_GPI_SPI>; 1706 dma-names = "tx", "rx"; 1707 status = "disabled"; 1708 }; 1709 1710 uart7: serial@89c000 { 1711 compatible = "qcom,geni-uart"; 1712 reg = <0 0x0089c000 0 0x4000>; 1713 clock-names = "se"; 1714 clocks = <&gcc GCC_QUPV3_WRAP0_S7_CLK>; 1715 pinctrl-names = "default"; 1716 pinctrl-0 = <&qup_uart7_default>; 1717 interrupts = <GIC_SPI 608 IRQ_TYPE_LEVEL_HIGH>; 1718 power-domains = <&rpmhpd SDM845_CX>; 1719 operating-points-v2 = <&qup_opp_table>; 1720 interconnects = <&aggre1_noc MASTER_QUP_1 0 &config_noc SLAVE_BLSP_1 0>, 1721 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_1 0>; 1722 interconnect-names = "qup-core", "qup-config"; 1723 status = "disabled"; 1724 }; 1725 }; 1726 1727 gpi_dma1: dma-controller@a00000 { 1728 #dma-cells = <3>; 1729 compatible = "qcom,sdm845-gpi-dma"; 1730 reg = <0 0x00a00000 0 0x60000>; 1731 interrupts = <GIC_SPI 279 IRQ_TYPE_LEVEL_HIGH>, 1732 <GIC_SPI 280 IRQ_TYPE_LEVEL_HIGH>, 1733 <GIC_SPI 281 IRQ_TYPE_LEVEL_HIGH>, 1734 <GIC_SPI 282 IRQ_TYPE_LEVEL_HIGH>, 1735 <GIC_SPI 283 IRQ_TYPE_LEVEL_HIGH>, 1736 <GIC_SPI 284 IRQ_TYPE_LEVEL_HIGH>, 1737 <GIC_SPI 293 IRQ_TYPE_LEVEL_HIGH>, 1738 <GIC_SPI 294 IRQ_TYPE_LEVEL_HIGH>, 1739 <GIC_SPI 295 IRQ_TYPE_LEVEL_HIGH>, 1740 <GIC_SPI 296 IRQ_TYPE_LEVEL_HIGH>, 1741 <GIC_SPI 297 IRQ_TYPE_LEVEL_HIGH>, 1742 <GIC_SPI 298 IRQ_TYPE_LEVEL_HIGH>, 1743 <GIC_SPI 299 IRQ_TYPE_LEVEL_HIGH>; 1744 dma-channels = <13>; 1745 dma-channel-mask = <0xfa>; 1746 iommus = <&apps_smmu 0x06d6 0x0>; 1747 status = "disabled"; 1748 }; 1749 1750 qupv3_id_1: geniqup@ac0000 { 1751 compatible = "qcom,geni-se-qup"; 1752 reg = <0 0x00ac0000 0 0x6000>; 1753 clock-names = "m-ahb", "s-ahb"; 1754 clocks = <&gcc GCC_QUPV3_WRAP_1_M_AHB_CLK>, 1755 <&gcc GCC_QUPV3_WRAP_1_S_AHB_CLK>; 1756 iommus = <&apps_smmu 0x6c3 0x0>; 1757 #address-cells = <2>; 1758 #size-cells = <2>; 1759 ranges; 1760 interconnects = <&aggre2_noc MASTER_QUP_2 0 &config_noc SLAVE_BLSP_2 0>; 1761 interconnect-names = "qup-core"; 1762 status = "disabled"; 1763 1764 i2c8: i2c@a80000 { 1765 compatible = "qcom,geni-i2c"; 1766 reg = <0 0x00a80000 0 0x4000>; 1767 clock-names = "se"; 1768 clocks = <&gcc GCC_QUPV3_WRAP1_S0_CLK>; 1769 pinctrl-names = "default"; 1770 pinctrl-0 = <&qup_i2c8_default>; 1771 interrupts = <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>; 1772 #address-cells = <1>; 1773 #size-cells = <0>; 1774 power-domains = <&rpmhpd SDM845_CX>; 1775 operating-points-v2 = <&qup_opp_table>; 1776 interconnects = <&aggre2_noc MASTER_QUP_2 0 &config_noc SLAVE_BLSP_2 0>, 1777 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_2 0>, 1778 <&aggre2_noc MASTER_QUP_2 0 &mem_noc SLAVE_EBI1 0>; 1779 interconnect-names = "qup-core", "qup-config", "qup-memory"; 1780 dmas = <&gpi_dma1 0 0 QCOM_GPI_I2C>, 1781 <&gpi_dma1 1 0 QCOM_GPI_I2C>; 1782 dma-names = "tx", "rx"; 1783 status = "disabled"; 1784 }; 1785 1786 spi8: spi@a80000 { 1787 compatible = "qcom,geni-spi"; 1788 reg = <0 0x00a80000 0 0x4000>; 1789 clock-names = "se"; 1790 clocks = <&gcc GCC_QUPV3_WRAP1_S0_CLK>; 1791 pinctrl-names = "default"; 1792 pinctrl-0 = <&qup_spi8_default>; 1793 interrupts = <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>; 1794 #address-cells = <1>; 1795 #size-cells = <0>; 1796 interconnects = <&aggre2_noc MASTER_QUP_2 0 &config_noc SLAVE_BLSP_2 0>, 1797 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_2 0>; 1798 interconnect-names = "qup-core", "qup-config"; 1799 dmas = <&gpi_dma1 0 0 QCOM_GPI_SPI>, 1800 <&gpi_dma1 1 0 QCOM_GPI_SPI>; 1801 dma-names = "tx", "rx"; 1802 status = "disabled"; 1803 }; 1804 1805 uart8: serial@a80000 { 1806 compatible = "qcom,geni-uart"; 1807 reg = <0 0x00a80000 0 0x4000>; 1808 clock-names = "se"; 1809 clocks = <&gcc GCC_QUPV3_WRAP1_S0_CLK>; 1810 pinctrl-names = "default"; 1811 pinctrl-0 = <&qup_uart8_default>; 1812 interrupts = <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>; 1813 power-domains = <&rpmhpd SDM845_CX>; 1814 operating-points-v2 = <&qup_opp_table>; 1815 interconnects = <&aggre2_noc MASTER_QUP_2 0 &config_noc SLAVE_BLSP_2 0>, 1816 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_2 0>; 1817 interconnect-names = "qup-core", "qup-config"; 1818 status = "disabled"; 1819 }; 1820 1821 i2c9: i2c@a84000 { 1822 compatible = "qcom,geni-i2c"; 1823 reg = <0 0x00a84000 0 0x4000>; 1824 clock-names = "se"; 1825 clocks = <&gcc GCC_QUPV3_WRAP1_S1_CLK>; 1826 pinctrl-names = "default"; 1827 pinctrl-0 = <&qup_i2c9_default>; 1828 interrupts = <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>; 1829 #address-cells = <1>; 1830 #size-cells = <0>; 1831 power-domains = <&rpmhpd SDM845_CX>; 1832 operating-points-v2 = <&qup_opp_table>; 1833 interconnects = <&aggre2_noc MASTER_QUP_2 0 &config_noc SLAVE_BLSP_2 0>, 1834 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_2 0>, 1835 <&aggre2_noc MASTER_QUP_2 0 &mem_noc SLAVE_EBI1 0>; 1836 interconnect-names = "qup-core", "qup-config", "qup-memory"; 1837 dmas = <&gpi_dma1 0 1 QCOM_GPI_I2C>, 1838 <&gpi_dma1 1 1 QCOM_GPI_I2C>; 1839 dma-names = "tx", "rx"; 1840 status = "disabled"; 1841 }; 1842 1843 spi9: spi@a84000 { 1844 compatible = "qcom,geni-spi"; 1845 reg = <0 0x00a84000 0 0x4000>; 1846 clock-names = "se"; 1847 clocks = <&gcc GCC_QUPV3_WRAP1_S1_CLK>; 1848 pinctrl-names = "default"; 1849 pinctrl-0 = <&qup_spi9_default>; 1850 interrupts = <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>; 1851 #address-cells = <1>; 1852 #size-cells = <0>; 1853 interconnects = <&aggre2_noc MASTER_QUP_2 0 &config_noc SLAVE_BLSP_2 0>, 1854 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_2 0>; 1855 interconnect-names = "qup-core", "qup-config"; 1856 dmas = <&gpi_dma1 0 1 QCOM_GPI_SPI>, 1857 <&gpi_dma1 1 1 QCOM_GPI_SPI>; 1858 dma-names = "tx", "rx"; 1859 status = "disabled"; 1860 }; 1861 1862 uart9: serial@a84000 { 1863 compatible = "qcom,geni-debug-uart"; 1864 reg = <0 0x00a84000 0 0x4000>; 1865 clock-names = "se"; 1866 clocks = <&gcc GCC_QUPV3_WRAP1_S1_CLK>; 1867 pinctrl-names = "default"; 1868 pinctrl-0 = <&qup_uart9_default>; 1869 interrupts = <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>; 1870 power-domains = <&rpmhpd SDM845_CX>; 1871 operating-points-v2 = <&qup_opp_table>; 1872 interconnects = <&aggre2_noc MASTER_QUP_2 0 &config_noc SLAVE_BLSP_2 0>, 1873 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_2 0>; 1874 interconnect-names = "qup-core", "qup-config"; 1875 status = "disabled"; 1876 }; 1877 1878 i2c10: i2c@a88000 { 1879 compatible = "qcom,geni-i2c"; 1880 reg = <0 0x00a88000 0 0x4000>; 1881 clock-names = "se"; 1882 clocks = <&gcc GCC_QUPV3_WRAP1_S2_CLK>; 1883 pinctrl-names = "default"; 1884 pinctrl-0 = <&qup_i2c10_default>; 1885 interrupts = <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>; 1886 #address-cells = <1>; 1887 #size-cells = <0>; 1888 power-domains = <&rpmhpd SDM845_CX>; 1889 operating-points-v2 = <&qup_opp_table>; 1890 interconnects = <&aggre2_noc MASTER_QUP_2 0 &config_noc SLAVE_BLSP_2 0>, 1891 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_2 0>, 1892 <&aggre2_noc MASTER_QUP_2 0 &mem_noc SLAVE_EBI1 0>; 1893 interconnect-names = "qup-core", "qup-config", "qup-memory"; 1894 dmas = <&gpi_dma1 0 2 QCOM_GPI_I2C>, 1895 <&gpi_dma1 1 2 QCOM_GPI_I2C>; 1896 dma-names = "tx", "rx"; 1897 status = "disabled"; 1898 }; 1899 1900 spi10: spi@a88000 { 1901 compatible = "qcom,geni-spi"; 1902 reg = <0 0x00a88000 0 0x4000>; 1903 clock-names = "se"; 1904 clocks = <&gcc GCC_QUPV3_WRAP1_S2_CLK>; 1905 pinctrl-names = "default"; 1906 pinctrl-0 = <&qup_spi10_default>; 1907 interrupts = <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>; 1908 #address-cells = <1>; 1909 #size-cells = <0>; 1910 interconnects = <&aggre2_noc MASTER_QUP_2 0 &config_noc SLAVE_BLSP_2 0>, 1911 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_2 0>; 1912 interconnect-names = "qup-core", "qup-config"; 1913 dmas = <&gpi_dma1 0 2 QCOM_GPI_SPI>, 1914 <&gpi_dma1 1 2 QCOM_GPI_SPI>; 1915 dma-names = "tx", "rx"; 1916 status = "disabled"; 1917 }; 1918 1919 uart10: serial@a88000 { 1920 compatible = "qcom,geni-uart"; 1921 reg = <0 0x00a88000 0 0x4000>; 1922 clock-names = "se"; 1923 clocks = <&gcc GCC_QUPV3_WRAP1_S2_CLK>; 1924 pinctrl-names = "default"; 1925 pinctrl-0 = <&qup_uart10_default>; 1926 interrupts = <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>; 1927 power-domains = <&rpmhpd SDM845_CX>; 1928 operating-points-v2 = <&qup_opp_table>; 1929 interconnects = <&aggre2_noc MASTER_QUP_2 0 &config_noc SLAVE_BLSP_2 0>, 1930 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_2 0>; 1931 interconnect-names = "qup-core", "qup-config"; 1932 status = "disabled"; 1933 }; 1934 1935 i2c11: i2c@a8c000 { 1936 compatible = "qcom,geni-i2c"; 1937 reg = <0 0x00a8c000 0 0x4000>; 1938 clock-names = "se"; 1939 clocks = <&gcc GCC_QUPV3_WRAP1_S3_CLK>; 1940 pinctrl-names = "default"; 1941 pinctrl-0 = <&qup_i2c11_default>; 1942 interrupts = <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>; 1943 #address-cells = <1>; 1944 #size-cells = <0>; 1945 power-domains = <&rpmhpd SDM845_CX>; 1946 operating-points-v2 = <&qup_opp_table>; 1947 interconnects = <&aggre2_noc MASTER_QUP_2 0 &config_noc SLAVE_BLSP_2 0>, 1948 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_2 0>, 1949 <&aggre2_noc MASTER_QUP_2 0 &mem_noc SLAVE_EBI1 0>; 1950 interconnect-names = "qup-core", "qup-config", "qup-memory"; 1951 dmas = <&gpi_dma1 0 3 QCOM_GPI_I2C>, 1952 <&gpi_dma1 1 3 QCOM_GPI_I2C>; 1953 dma-names = "tx", "rx"; 1954 status = "disabled"; 1955 }; 1956 1957 spi11: spi@a8c000 { 1958 compatible = "qcom,geni-spi"; 1959 reg = <0 0x00a8c000 0 0x4000>; 1960 clock-names = "se"; 1961 clocks = <&gcc GCC_QUPV3_WRAP1_S3_CLK>; 1962 pinctrl-names = "default"; 1963 pinctrl-0 = <&qup_spi11_default>; 1964 interrupts = <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>; 1965 #address-cells = <1>; 1966 #size-cells = <0>; 1967 interconnects = <&aggre2_noc MASTER_QUP_2 0 &config_noc SLAVE_BLSP_2 0>, 1968 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_2 0>; 1969 interconnect-names = "qup-core", "qup-config"; 1970 dmas = <&gpi_dma1 0 3 QCOM_GPI_SPI>, 1971 <&gpi_dma1 1 3 QCOM_GPI_SPI>; 1972 dma-names = "tx", "rx"; 1973 status = "disabled"; 1974 }; 1975 1976 uart11: serial@a8c000 { 1977 compatible = "qcom,geni-uart"; 1978 reg = <0 0x00a8c000 0 0x4000>; 1979 clock-names = "se"; 1980 clocks = <&gcc GCC_QUPV3_WRAP1_S3_CLK>; 1981 pinctrl-names = "default"; 1982 pinctrl-0 = <&qup_uart11_default>; 1983 interrupts = <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>; 1984 power-domains = <&rpmhpd SDM845_CX>; 1985 operating-points-v2 = <&qup_opp_table>; 1986 interconnects = <&aggre2_noc MASTER_QUP_2 0 &config_noc SLAVE_BLSP_2 0>, 1987 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_2 0>; 1988 interconnect-names = "qup-core", "qup-config"; 1989 status = "disabled"; 1990 }; 1991 1992 i2c12: i2c@a90000 { 1993 compatible = "qcom,geni-i2c"; 1994 reg = <0 0x00a90000 0 0x4000>; 1995 clock-names = "se"; 1996 clocks = <&gcc GCC_QUPV3_WRAP1_S4_CLK>; 1997 pinctrl-names = "default"; 1998 pinctrl-0 = <&qup_i2c12_default>; 1999 interrupts = <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>; 2000 #address-cells = <1>; 2001 #size-cells = <0>; 2002 power-domains = <&rpmhpd SDM845_CX>; 2003 operating-points-v2 = <&qup_opp_table>; 2004 interconnects = <&aggre2_noc MASTER_QUP_2 0 &config_noc SLAVE_BLSP_2 0>, 2005 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_2 0>, 2006 <&aggre2_noc MASTER_QUP_2 0 &mem_noc SLAVE_EBI1 0>; 2007 interconnect-names = "qup-core", "qup-config", "qup-memory"; 2008 dmas = <&gpi_dma1 0 4 QCOM_GPI_I2C>, 2009 <&gpi_dma1 1 4 QCOM_GPI_I2C>; 2010 dma-names = "tx", "rx"; 2011 status = "disabled"; 2012 }; 2013 2014 spi12: spi@a90000 { 2015 compatible = "qcom,geni-spi"; 2016 reg = <0 0x00a90000 0 0x4000>; 2017 clock-names = "se"; 2018 clocks = <&gcc GCC_QUPV3_WRAP1_S4_CLK>; 2019 pinctrl-names = "default"; 2020 pinctrl-0 = <&qup_spi12_default>; 2021 interrupts = <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>; 2022 #address-cells = <1>; 2023 #size-cells = <0>; 2024 interconnects = <&aggre2_noc MASTER_QUP_2 0 &config_noc SLAVE_BLSP_2 0>, 2025 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_2 0>; 2026 interconnect-names = "qup-core", "qup-config"; 2027 dmas = <&gpi_dma1 0 4 QCOM_GPI_SPI>, 2028 <&gpi_dma1 1 4 QCOM_GPI_SPI>; 2029 dma-names = "tx", "rx"; 2030 status = "disabled"; 2031 }; 2032 2033 uart12: serial@a90000 { 2034 compatible = "qcom,geni-uart"; 2035 reg = <0 0x00a90000 0 0x4000>; 2036 clock-names = "se"; 2037 clocks = <&gcc GCC_QUPV3_WRAP1_S4_CLK>; 2038 pinctrl-names = "default"; 2039 pinctrl-0 = <&qup_uart12_default>; 2040 interrupts = <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>; 2041 power-domains = <&rpmhpd SDM845_CX>; 2042 operating-points-v2 = <&qup_opp_table>; 2043 interconnects = <&aggre2_noc MASTER_QUP_2 0 &config_noc SLAVE_BLSP_2 0>, 2044 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_2 0>; 2045 interconnect-names = "qup-core", "qup-config"; 2046 status = "disabled"; 2047 }; 2048 2049 i2c13: i2c@a94000 { 2050 compatible = "qcom,geni-i2c"; 2051 reg = <0 0x00a94000 0 0x4000>; 2052 clock-names = "se"; 2053 clocks = <&gcc GCC_QUPV3_WRAP1_S5_CLK>; 2054 pinctrl-names = "default"; 2055 pinctrl-0 = <&qup_i2c13_default>; 2056 interrupts = <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>; 2057 #address-cells = <1>; 2058 #size-cells = <0>; 2059 power-domains = <&rpmhpd SDM845_CX>; 2060 operating-points-v2 = <&qup_opp_table>; 2061 interconnects = <&aggre2_noc MASTER_QUP_2 0 &config_noc SLAVE_BLSP_2 0>, 2062 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_2 0>, 2063 <&aggre2_noc MASTER_QUP_2 0 &mem_noc SLAVE_EBI1 0>; 2064 interconnect-names = "qup-core", "qup-config", "qup-memory"; 2065 dmas = <&gpi_dma1 0 5 QCOM_GPI_I2C>, 2066 <&gpi_dma1 1 5 QCOM_GPI_I2C>; 2067 dma-names = "tx", "rx"; 2068 status = "disabled"; 2069 }; 2070 2071 spi13: spi@a94000 { 2072 compatible = "qcom,geni-spi"; 2073 reg = <0 0x00a94000 0 0x4000>; 2074 clock-names = "se"; 2075 clocks = <&gcc GCC_QUPV3_WRAP1_S5_CLK>; 2076 pinctrl-names = "default"; 2077 pinctrl-0 = <&qup_spi13_default>; 2078 interrupts = <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>; 2079 #address-cells = <1>; 2080 #size-cells = <0>; 2081 interconnects = <&aggre2_noc MASTER_QUP_2 0 &config_noc SLAVE_BLSP_2 0>, 2082 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_2 0>; 2083 interconnect-names = "qup-core", "qup-config"; 2084 dmas = <&gpi_dma1 0 5 QCOM_GPI_SPI>, 2085 <&gpi_dma1 1 5 QCOM_GPI_SPI>; 2086 dma-names = "tx", "rx"; 2087 status = "disabled"; 2088 }; 2089 2090 uart13: serial@a94000 { 2091 compatible = "qcom,geni-uart"; 2092 reg = <0 0x00a94000 0 0x4000>; 2093 clock-names = "se"; 2094 clocks = <&gcc GCC_QUPV3_WRAP1_S5_CLK>; 2095 pinctrl-names = "default"; 2096 pinctrl-0 = <&qup_uart13_default>; 2097 interrupts = <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>; 2098 power-domains = <&rpmhpd SDM845_CX>; 2099 operating-points-v2 = <&qup_opp_table>; 2100 interconnects = <&aggre2_noc MASTER_QUP_2 0 &config_noc SLAVE_BLSP_2 0>, 2101 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_2 0>; 2102 interconnect-names = "qup-core", "qup-config"; 2103 status = "disabled"; 2104 }; 2105 2106 i2c14: i2c@a98000 { 2107 compatible = "qcom,geni-i2c"; 2108 reg = <0 0x00a98000 0 0x4000>; 2109 clock-names = "se"; 2110 clocks = <&gcc GCC_QUPV3_WRAP1_S6_CLK>; 2111 pinctrl-names = "default"; 2112 pinctrl-0 = <&qup_i2c14_default>; 2113 interrupts = <GIC_SPI 359 IRQ_TYPE_LEVEL_HIGH>; 2114 #address-cells = <1>; 2115 #size-cells = <0>; 2116 power-domains = <&rpmhpd SDM845_CX>; 2117 operating-points-v2 = <&qup_opp_table>; 2118 interconnects = <&aggre2_noc MASTER_QUP_2 0 &config_noc SLAVE_BLSP_2 0>, 2119 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_2 0>, 2120 <&aggre2_noc MASTER_QUP_2 0 &mem_noc SLAVE_EBI1 0>; 2121 interconnect-names = "qup-core", "qup-config", "qup-memory"; 2122 dmas = <&gpi_dma1 0 6 QCOM_GPI_I2C>, 2123 <&gpi_dma1 1 6 QCOM_GPI_I2C>; 2124 dma-names = "tx", "rx"; 2125 status = "disabled"; 2126 }; 2127 2128 spi14: spi@a98000 { 2129 compatible = "qcom,geni-spi"; 2130 reg = <0 0x00a98000 0 0x4000>; 2131 clock-names = "se"; 2132 clocks = <&gcc GCC_QUPV3_WRAP1_S6_CLK>; 2133 pinctrl-names = "default"; 2134 pinctrl-0 = <&qup_spi14_default>; 2135 interrupts = <GIC_SPI 359 IRQ_TYPE_LEVEL_HIGH>; 2136 #address-cells = <1>; 2137 #size-cells = <0>; 2138 interconnects = <&aggre2_noc MASTER_QUP_2 0 &config_noc SLAVE_BLSP_2 0>, 2139 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_2 0>; 2140 interconnect-names = "qup-core", "qup-config"; 2141 dmas = <&gpi_dma1 0 6 QCOM_GPI_SPI>, 2142 <&gpi_dma1 1 6 QCOM_GPI_SPI>; 2143 dma-names = "tx", "rx"; 2144 status = "disabled"; 2145 }; 2146 2147 uart14: serial@a98000 { 2148 compatible = "qcom,geni-uart"; 2149 reg = <0 0x00a98000 0 0x4000>; 2150 clock-names = "se"; 2151 clocks = <&gcc GCC_QUPV3_WRAP1_S6_CLK>; 2152 pinctrl-names = "default"; 2153 pinctrl-0 = <&qup_uart14_default>; 2154 interrupts = <GIC_SPI 359 IRQ_TYPE_LEVEL_HIGH>; 2155 power-domains = <&rpmhpd SDM845_CX>; 2156 operating-points-v2 = <&qup_opp_table>; 2157 interconnects = <&aggre2_noc MASTER_QUP_2 0 &config_noc SLAVE_BLSP_2 0>, 2158 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_2 0>; 2159 interconnect-names = "qup-core", "qup-config"; 2160 status = "disabled"; 2161 }; 2162 2163 i2c15: i2c@a9c000 { 2164 compatible = "qcom,geni-i2c"; 2165 reg = <0 0x00a9c000 0 0x4000>; 2166 clock-names = "se"; 2167 clocks = <&gcc GCC_QUPV3_WRAP1_S7_CLK>; 2168 pinctrl-names = "default"; 2169 pinctrl-0 = <&qup_i2c15_default>; 2170 interrupts = <GIC_SPI 360 IRQ_TYPE_LEVEL_HIGH>; 2171 #address-cells = <1>; 2172 #size-cells = <0>; 2173 power-domains = <&rpmhpd SDM845_CX>; 2174 operating-points-v2 = <&qup_opp_table>; 2175 status = "disabled"; 2176 interconnects = <&aggre2_noc MASTER_QUP_2 0 &config_noc SLAVE_BLSP_2 0>, 2177 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_2 0>, 2178 <&aggre2_noc MASTER_QUP_2 0 &mem_noc SLAVE_EBI1 0>; 2179 interconnect-names = "qup-core", "qup-config", "qup-memory"; 2180 dmas = <&gpi_dma1 0 7 QCOM_GPI_I2C>, 2181 <&gpi_dma1 1 7 QCOM_GPI_I2C>; 2182 dma-names = "tx", "rx"; 2183 }; 2184 2185 spi15: spi@a9c000 { 2186 compatible = "qcom,geni-spi"; 2187 reg = <0 0x00a9c000 0 0x4000>; 2188 clock-names = "se"; 2189 clocks = <&gcc GCC_QUPV3_WRAP1_S7_CLK>; 2190 pinctrl-names = "default"; 2191 pinctrl-0 = <&qup_spi15_default>; 2192 interrupts = <GIC_SPI 360 IRQ_TYPE_LEVEL_HIGH>; 2193 #address-cells = <1>; 2194 #size-cells = <0>; 2195 interconnects = <&aggre2_noc MASTER_QUP_2 0 &config_noc SLAVE_BLSP_2 0>, 2196 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_2 0>; 2197 interconnect-names = "qup-core", "qup-config"; 2198 dmas = <&gpi_dma1 0 7 QCOM_GPI_SPI>, 2199 <&gpi_dma1 1 7 QCOM_GPI_SPI>; 2200 dma-names = "tx", "rx"; 2201 status = "disabled"; 2202 }; 2203 2204 uart15: serial@a9c000 { 2205 compatible = "qcom,geni-uart"; 2206 reg = <0 0x00a9c000 0 0x4000>; 2207 clock-names = "se"; 2208 clocks = <&gcc GCC_QUPV3_WRAP1_S7_CLK>; 2209 pinctrl-names = "default"; 2210 pinctrl-0 = <&qup_uart15_default>; 2211 interrupts = <GIC_SPI 360 IRQ_TYPE_LEVEL_HIGH>; 2212 power-domains = <&rpmhpd SDM845_CX>; 2213 operating-points-v2 = <&qup_opp_table>; 2214 interconnects = <&aggre2_noc MASTER_QUP_2 0 &config_noc SLAVE_BLSP_2 0>, 2215 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_2 0>; 2216 interconnect-names = "qup-core", "qup-config"; 2217 status = "disabled"; 2218 }; 2219 }; 2220 2221 refgen: regulator@ff1000 { 2222 compatible = "qcom,sdm845-refgen-regulator"; 2223 reg = <0x0 0x00ff1000 0x0 0x60>; 2224 }; 2225 2226 llcc: system-cache-controller@1100000 { 2227 compatible = "qcom,sdm845-llcc"; 2228 reg = <0 0x01100000 0 0x45000>, <0 0x01180000 0 0x50000>, 2229 <0 0x01200000 0 0x50000>, <0 0x01280000 0 0x50000>, 2230 <0 0x01300000 0 0x50000>; 2231 reg-names = "llcc0_base", "llcc1_base", "llcc2_base", 2232 "llcc3_base", "llcc_broadcast_base"; 2233 interrupts = <GIC_SPI 582 IRQ_TYPE_LEVEL_HIGH>; 2234 }; 2235 2236 dma@10a2000 { 2237 compatible = "qcom,sdm845-dcc", "qcom,dcc"; 2238 reg = <0x0 0x010a2000 0x0 0x1000>, 2239 <0x0 0x010ae000 0x0 0x2000>; 2240 }; 2241 2242 pmu@114a000 { 2243 compatible = "qcom,sdm845-llcc-bwmon"; 2244 reg = <0 0x0114a000 0 0x1000>; 2245 interrupts = <GIC_SPI 580 IRQ_TYPE_LEVEL_HIGH>; 2246 interconnects = <&mem_noc MASTER_LLCC 3 &mem_noc SLAVE_EBI1 3>; 2247 2248 operating-points-v2 = <&llcc_bwmon_opp_table>; 2249 2250 llcc_bwmon_opp_table: opp-table { 2251 compatible = "operating-points-v2"; 2252 2253 /* 2254 * The interconnect path bandwidth taken from 2255 * cpu4_opp_table bandwidth for gladiator_noc-mem_noc 2256 * interconnect. This also matches the 2257 * bandwidth table of qcom,llccbw (qcom,bw-tbl, 2258 * bus width: 4 bytes) from msm-4.9 downstream 2259 * kernel. 2260 */ 2261 opp-0 { 2262 opp-peak-kBps = <800000>; 2263 }; 2264 opp-1 { 2265 opp-peak-kBps = <1804000>; 2266 }; 2267 opp-2 { 2268 opp-peak-kBps = <3072000>; 2269 }; 2270 opp-3 { 2271 opp-peak-kBps = <5412000>; 2272 }; 2273 opp-4 { 2274 opp-peak-kBps = <7216000>; 2275 }; 2276 }; 2277 }; 2278 2279 pmu@1436400 { 2280 compatible = "qcom,sdm845-cpu-bwmon", "qcom,sdm845-bwmon"; 2281 reg = <0 0x01436400 0 0x600>; 2282 interrupts = <GIC_SPI 581 IRQ_TYPE_LEVEL_HIGH>; 2283 interconnects = <&gladiator_noc MASTER_APPSS_PROC 3 &mem_noc SLAVE_LLCC 3>; 2284 2285 operating-points-v2 = <&cpu_bwmon_opp_table>; 2286 2287 cpu_bwmon_opp_table: opp-table { 2288 compatible = "operating-points-v2"; 2289 2290 /* 2291 * The interconnect path bandwidth taken from 2292 * cpu4_opp_table bandwidth for OSM L3 2293 * interconnect. This also matches the OSM L3 2294 * from bandwidth table of qcom,cpu4-l3lat-mon 2295 * (qcom,core-dev-table, bus width: 16 bytes) 2296 * from msm-4.9 downstream kernel. 2297 */ 2298 opp-0 { 2299 opp-peak-kBps = <4800000>; 2300 }; 2301 opp-1 { 2302 opp-peak-kBps = <9216000>; 2303 }; 2304 opp-2 { 2305 opp-peak-kBps = <15052800>; 2306 }; 2307 opp-3 { 2308 opp-peak-kBps = <20889600>; 2309 }; 2310 opp-4 { 2311 opp-peak-kBps = <25497600>; 2312 }; 2313 }; 2314 }; 2315 2316 pcie0: pcie@1c00000 { 2317 compatible = "qcom,pcie-sdm845"; 2318 reg = <0 0x01c00000 0 0x2000>, 2319 <0 0x60000000 0 0xf1d>, 2320 <0 0x60000f20 0 0xa8>, 2321 <0 0x60100000 0 0x100000>, 2322 <0 0x01c07000 0 0x1000>; 2323 reg-names = "parf", "dbi", "elbi", "config", "mhi"; 2324 device_type = "pci"; 2325 linux,pci-domain = <0>; 2326 bus-range = <0x00 0xff>; 2327 num-lanes = <1>; 2328 2329 #address-cells = <3>; 2330 #size-cells = <2>; 2331 2332 ranges = <0x01000000 0x0 0x00000000 0x0 0x60200000 0x0 0x100000>, 2333 <0x02000000 0x0 0x60300000 0x0 0x60300000 0x0 0xd00000>; 2334 2335 interrupts = <GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>, 2336 <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>, 2337 <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>, 2338 <GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH>, 2339 <GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>, 2340 <GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>, 2341 <GIC_SPI 147 IRQ_TYPE_LEVEL_HIGH>, 2342 <GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>, 2343 <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>; 2344 interrupt-names = "msi0", 2345 "msi1", 2346 "msi2", 2347 "msi3", 2348 "msi4", 2349 "msi5", 2350 "msi6", 2351 "msi7", 2352 "global"; 2353 #interrupt-cells = <1>; 2354 interrupt-map-mask = <0 0 0 0x7>; 2355 interrupt-map = <0 0 0 1 &intc 0 0 GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH>, /* int_a */ 2356 <0 0 0 2 &intc 0 0 GIC_SPI 150 IRQ_TYPE_LEVEL_HIGH>, /* int_b */ 2357 <0 0 0 3 &intc 0 0 GIC_SPI 151 IRQ_TYPE_LEVEL_HIGH>, /* int_c */ 2358 <0 0 0 4 &intc 0 0 GIC_SPI 152 IRQ_TYPE_LEVEL_HIGH>; /* int_d */ 2359 2360 clocks = <&gcc GCC_PCIE_0_PIPE_CLK>, 2361 <&gcc GCC_PCIE_0_AUX_CLK>, 2362 <&gcc GCC_PCIE_0_CFG_AHB_CLK>, 2363 <&gcc GCC_PCIE_0_MSTR_AXI_CLK>, 2364 <&gcc GCC_PCIE_0_SLV_AXI_CLK>, 2365 <&gcc GCC_PCIE_0_SLV_Q2A_AXI_CLK>, 2366 <&gcc GCC_AGGRE_NOC_PCIE_TBU_CLK>; 2367 clock-names = "pipe", 2368 "aux", 2369 "cfg", 2370 "bus_master", 2371 "bus_slave", 2372 "slave_q2a", 2373 "tbu"; 2374 2375 iommu-map = <0x0 &apps_smmu 0x1c10 0x1>, 2376 <0x100 &apps_smmu 0x1c11 0x1>, 2377 <0x200 &apps_smmu 0x1c12 0x1>, 2378 <0x300 &apps_smmu 0x1c13 0x1>, 2379 <0x400 &apps_smmu 0x1c14 0x1>, 2380 <0x500 &apps_smmu 0x1c15 0x1>, 2381 <0x600 &apps_smmu 0x1c16 0x1>, 2382 <0x700 &apps_smmu 0x1c17 0x1>, 2383 <0x800 &apps_smmu 0x1c18 0x1>, 2384 <0x900 &apps_smmu 0x1c19 0x1>, 2385 <0xa00 &apps_smmu 0x1c1a 0x1>, 2386 <0xb00 &apps_smmu 0x1c1b 0x1>, 2387 <0xc00 &apps_smmu 0x1c1c 0x1>, 2388 <0xd00 &apps_smmu 0x1c1d 0x1>, 2389 <0xe00 &apps_smmu 0x1c1e 0x1>, 2390 <0xf00 &apps_smmu 0x1c1f 0x1>; 2391 2392 resets = <&gcc GCC_PCIE_0_BCR>; 2393 reset-names = "pci"; 2394 2395 power-domains = <&gcc PCIE_0_GDSC>; 2396 2397 phys = <&pcie0_phy>; 2398 phy-names = "pciephy"; 2399 2400 status = "disabled"; 2401 2402 pcie@0 { 2403 device_type = "pci"; 2404 reg = <0x0 0x0 0x0 0x0 0x0>; 2405 bus-range = <0x01 0xff>; 2406 2407 #address-cells = <3>; 2408 #size-cells = <2>; 2409 ranges; 2410 }; 2411 }; 2412 2413 pcie0_phy: phy@1c06000 { 2414 compatible = "qcom,sdm845-qmp-pcie-phy"; 2415 reg = <0 0x01c06000 0 0x1000>; 2416 clocks = <&gcc GCC_PCIE_PHY_AUX_CLK>, 2417 <&gcc GCC_PCIE_0_CFG_AHB_CLK>, 2418 <&gcc GCC_PCIE_0_CLKREF_CLK>, 2419 <&gcc GCC_PCIE_PHY_REFGEN_CLK>, 2420 <&gcc GCC_PCIE_0_PIPE_CLK>; 2421 clock-names = "aux", 2422 "cfg_ahb", 2423 "ref", 2424 "refgen", 2425 "pipe"; 2426 2427 clock-output-names = "pcie_0_pipe_clk"; 2428 #clock-cells = <0>; 2429 2430 #phy-cells = <0>; 2431 2432 resets = <&gcc GCC_PCIE_0_PHY_BCR>; 2433 reset-names = "phy"; 2434 2435 assigned-clocks = <&gcc GCC_PCIE_PHY_REFGEN_CLK>; 2436 assigned-clock-rates = <100000000>; 2437 2438 status = "disabled"; 2439 }; 2440 2441 pcie1: pcie@1c08000 { 2442 compatible = "qcom,pcie-sdm845"; 2443 reg = <0 0x01c08000 0 0x2000>, 2444 <0 0x40000000 0 0xf1d>, 2445 <0 0x40000f20 0 0xa8>, 2446 <0 0x40100000 0 0x100000>, 2447 <0 0x01c0c000 0 0x1000>; 2448 reg-names = "parf", "dbi", "elbi", "config", "mhi"; 2449 device_type = "pci"; 2450 linux,pci-domain = <1>; 2451 bus-range = <0x00 0xff>; 2452 num-lanes = <1>; 2453 2454 #address-cells = <3>; 2455 #size-cells = <2>; 2456 2457 ranges = <0x01000000 0x0 0x00000000 0x0 0x40200000 0x0 0x100000>, 2458 <0x02000000 0x0 0x40300000 0x0 0x40300000 0x0 0x1fd00000>; 2459 2460 interrupts = <GIC_SPI 307 IRQ_TYPE_LEVEL_HIGH>, 2461 <GIC_SPI 308 IRQ_TYPE_LEVEL_HIGH>, 2462 <GIC_SPI 309 IRQ_TYPE_LEVEL_HIGH>, 2463 <GIC_SPI 312 IRQ_TYPE_LEVEL_HIGH>, 2464 <GIC_SPI 313 IRQ_TYPE_LEVEL_HIGH>, 2465 <GIC_SPI 314 IRQ_TYPE_LEVEL_HIGH>, 2466 <GIC_SPI 374 IRQ_TYPE_LEVEL_HIGH>, 2467 <GIC_SPI 375 IRQ_TYPE_LEVEL_HIGH>, 2468 <GIC_SPI 306 IRQ_TYPE_LEVEL_HIGH>; 2469 interrupt-names = "msi0", 2470 "msi1", 2471 "msi2", 2472 "msi3", 2473 "msi4", 2474 "msi5", 2475 "msi6", 2476 "msi7", 2477 "global"; 2478 #interrupt-cells = <1>; 2479 interrupt-map-mask = <0 0 0 0x7>; 2480 interrupt-map = <0 0 0 1 &intc 0 0 GIC_SPI 434 IRQ_TYPE_LEVEL_HIGH>, /* int_a */ 2481 <0 0 0 2 &intc 0 0 GIC_SPI 435 IRQ_TYPE_LEVEL_HIGH>, /* int_b */ 2482 <0 0 0 3 &intc 0 0 GIC_SPI 438 IRQ_TYPE_LEVEL_HIGH>, /* int_c */ 2483 <0 0 0 4 &intc 0 0 GIC_SPI 439 IRQ_TYPE_LEVEL_HIGH>; /* int_d */ 2484 2485 clocks = <&gcc GCC_PCIE_1_PIPE_CLK>, 2486 <&gcc GCC_PCIE_1_AUX_CLK>, 2487 <&gcc GCC_PCIE_1_CFG_AHB_CLK>, 2488 <&gcc GCC_PCIE_1_MSTR_AXI_CLK>, 2489 <&gcc GCC_PCIE_1_SLV_AXI_CLK>, 2490 <&gcc GCC_PCIE_1_SLV_Q2A_AXI_CLK>, 2491 <&gcc GCC_PCIE_1_CLKREF_CLK>, 2492 <&gcc GCC_AGGRE_NOC_PCIE_TBU_CLK>; 2493 clock-names = "pipe", 2494 "aux", 2495 "cfg", 2496 "bus_master", 2497 "bus_slave", 2498 "slave_q2a", 2499 "ref", 2500 "tbu"; 2501 2502 assigned-clocks = <&gcc GCC_PCIE_1_AUX_CLK>; 2503 assigned-clock-rates = <19200000>; 2504 2505 iommu-map = <0x0 &apps_smmu 0x1c00 0x1>, 2506 <0x100 &apps_smmu 0x1c01 0x1>, 2507 <0x200 &apps_smmu 0x1c02 0x1>, 2508 <0x300 &apps_smmu 0x1c03 0x1>, 2509 <0x400 &apps_smmu 0x1c04 0x1>, 2510 <0x500 &apps_smmu 0x1c05 0x1>, 2511 <0x600 &apps_smmu 0x1c06 0x1>, 2512 <0x700 &apps_smmu 0x1c07 0x1>, 2513 <0x800 &apps_smmu 0x1c08 0x1>, 2514 <0x900 &apps_smmu 0x1c09 0x1>, 2515 <0xa00 &apps_smmu 0x1c0a 0x1>, 2516 <0xb00 &apps_smmu 0x1c0b 0x1>, 2517 <0xc00 &apps_smmu 0x1c0c 0x1>, 2518 <0xd00 &apps_smmu 0x1c0d 0x1>, 2519 <0xe00 &apps_smmu 0x1c0e 0x1>, 2520 <0xf00 &apps_smmu 0x1c0f 0x1>; 2521 2522 resets = <&gcc GCC_PCIE_1_BCR>; 2523 reset-names = "pci"; 2524 2525 power-domains = <&gcc PCIE_1_GDSC>; 2526 2527 phys = <&pcie1_phy>; 2528 phy-names = "pciephy"; 2529 2530 status = "disabled"; 2531 2532 pcie@0 { 2533 device_type = "pci"; 2534 reg = <0x0 0x0 0x0 0x0 0x0>; 2535 bus-range = <0x01 0xff>; 2536 2537 #address-cells = <3>; 2538 #size-cells = <2>; 2539 ranges; 2540 }; 2541 }; 2542 2543 pcie1_phy: phy@1c0a000 { 2544 compatible = "qcom,sdm845-qhp-pcie-phy"; 2545 reg = <0 0x01c0a000 0 0x2000>; 2546 clocks = <&gcc GCC_PCIE_PHY_AUX_CLK>, 2547 <&gcc GCC_PCIE_1_CFG_AHB_CLK>, 2548 <&gcc GCC_PCIE_1_CLKREF_CLK>, 2549 <&gcc GCC_PCIE_PHY_REFGEN_CLK>, 2550 <&gcc GCC_PCIE_1_PIPE_CLK>; 2551 clock-names = "aux", 2552 "cfg_ahb", 2553 "ref", 2554 "refgen", 2555 "pipe"; 2556 2557 clock-output-names = "pcie_1_pipe_clk"; 2558 #clock-cells = <0>; 2559 2560 #phy-cells = <0>; 2561 2562 resets = <&gcc GCC_PCIE_1_PHY_BCR>; 2563 reset-names = "phy"; 2564 2565 assigned-clocks = <&gcc GCC_PCIE_PHY_REFGEN_CLK>; 2566 assigned-clock-rates = <100000000>; 2567 2568 status = "disabled"; 2569 }; 2570 2571 mem_noc: interconnect@1380000 { 2572 compatible = "qcom,sdm845-mem-noc"; 2573 reg = <0 0x01380000 0 0x27200>; 2574 #interconnect-cells = <2>; 2575 qcom,bcm-voters = <&apps_bcm_voter>; 2576 }; 2577 2578 dc_noc: interconnect@14e0000 { 2579 compatible = "qcom,sdm845-dc-noc"; 2580 reg = <0 0x014e0000 0 0x400>; 2581 #interconnect-cells = <2>; 2582 qcom,bcm-voters = <&apps_bcm_voter>; 2583 }; 2584 2585 config_noc: interconnect@1500000 { 2586 compatible = "qcom,sdm845-config-noc"; 2587 reg = <0 0x01500000 0 0x5080>; 2588 #interconnect-cells = <2>; 2589 qcom,bcm-voters = <&apps_bcm_voter>; 2590 }; 2591 2592 system_noc: interconnect@1620000 { 2593 compatible = "qcom,sdm845-system-noc"; 2594 reg = <0 0x01620000 0 0x18080>; 2595 #interconnect-cells = <2>; 2596 qcom,bcm-voters = <&apps_bcm_voter>; 2597 }; 2598 2599 aggre1_noc: interconnect@16e0000 { 2600 compatible = "qcom,sdm845-aggre1-noc"; 2601 reg = <0 0x016e0000 0 0x15080>; 2602 #interconnect-cells = <2>; 2603 qcom,bcm-voters = <&apps_bcm_voter>; 2604 }; 2605 2606 aggre2_noc: interconnect@1700000 { 2607 compatible = "qcom,sdm845-aggre2-noc"; 2608 reg = <0 0x01700000 0 0x1f300>; 2609 #interconnect-cells = <2>; 2610 qcom,bcm-voters = <&apps_bcm_voter>; 2611 }; 2612 2613 mmss_noc: interconnect@1740000 { 2614 compatible = "qcom,sdm845-mmss-noc"; 2615 reg = <0 0x01740000 0 0x1c100>; 2616 #interconnect-cells = <2>; 2617 qcom,bcm-voters = <&apps_bcm_voter>; 2618 }; 2619 2620 ufs_mem_hc: ufshc@1d84000 { 2621 compatible = "qcom,sdm845-ufshc", "qcom,ufshc", 2622 "jedec,ufs-2.0"; 2623 reg = <0 0x01d84000 0 0x2500>, 2624 <0 0x01d90000 0 0x8000>; 2625 reg-names = "std", "ice"; 2626 interrupts = <GIC_SPI 265 IRQ_TYPE_LEVEL_HIGH>; 2627 phys = <&ufs_mem_phy>; 2628 phy-names = "ufsphy"; 2629 lanes-per-direction = <2>; 2630 power-domains = <&gcc UFS_PHY_GDSC>; 2631 #reset-cells = <1>; 2632 resets = <&gcc GCC_UFS_PHY_BCR>; 2633 reset-names = "rst"; 2634 2635 iommus = <&apps_smmu 0x100 0xf>; 2636 2637 clock-names = 2638 "core_clk", 2639 "bus_aggr_clk", 2640 "iface_clk", 2641 "core_clk_unipro", 2642 "ref_clk", 2643 "tx_lane0_sync_clk", 2644 "rx_lane0_sync_clk", 2645 "rx_lane1_sync_clk", 2646 "ice_core_clk"; 2647 clocks = 2648 <&gcc GCC_UFS_PHY_AXI_CLK>, 2649 <&gcc GCC_AGGRE_UFS_PHY_AXI_CLK>, 2650 <&gcc GCC_UFS_PHY_AHB_CLK>, 2651 <&gcc GCC_UFS_PHY_UNIPRO_CORE_CLK>, 2652 <&rpmhcc RPMH_CXO_CLK>, 2653 <&gcc GCC_UFS_PHY_TX_SYMBOL_0_CLK>, 2654 <&gcc GCC_UFS_PHY_RX_SYMBOL_0_CLK>, 2655 <&gcc GCC_UFS_PHY_RX_SYMBOL_1_CLK>, 2656 <&gcc GCC_UFS_PHY_ICE_CORE_CLK>; 2657 2658 operating-points-v2 = <&ufs_opp_table>; 2659 2660 interconnects = <&aggre1_noc MASTER_UFS_MEM 0 &mem_noc SLAVE_EBI1 0>, 2661 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_UFS_MEM_CFG 0>; 2662 interconnect-names = "ufs-ddr", "cpu-ufs"; 2663 2664 status = "disabled"; 2665 2666 ufs_opp_table: opp-table { 2667 compatible = "operating-points-v2"; 2668 2669 opp-50000000 { 2670 opp-hz = /bits/ 64 <50000000>, 2671 /bits/ 64 <0>, 2672 /bits/ 64 <0>, 2673 /bits/ 64 <37500000>, 2674 /bits/ 64 <0>, 2675 /bits/ 64 <0>, 2676 /bits/ 64 <0>, 2677 /bits/ 64 <0>, 2678 /bits/ 64 <75000000>; 2679 required-opps = <&rpmhpd_opp_low_svs>; 2680 }; 2681 2682 opp-200000000 { 2683 opp-hz = /bits/ 64 <200000000>, 2684 /bits/ 64 <0>, 2685 /bits/ 64 <0>, 2686 /bits/ 64 <150000000>, 2687 /bits/ 64 <0>, 2688 /bits/ 64 <0>, 2689 /bits/ 64 <0>, 2690 /bits/ 64 <0>, 2691 /bits/ 64 <300000000>; 2692 required-opps = <&rpmhpd_opp_nom>; 2693 }; 2694 }; 2695 }; 2696 2697 ufs_mem_phy: phy@1d87000 { 2698 compatible = "qcom,sdm845-qmp-ufs-phy"; 2699 reg = <0 0x01d87000 0 0x1000>; 2700 2701 clocks = <&rpmhcc RPMH_CXO_CLK>, 2702 <&gcc GCC_UFS_PHY_PHY_AUX_CLK>, 2703 <&gcc GCC_UFS_MEM_CLKREF_CLK>; 2704 clock-names = "ref", 2705 "ref_aux", 2706 "qref"; 2707 2708 power-domains = <&gcc UFS_PHY_GDSC>; 2709 2710 resets = <&ufs_mem_hc 0>; 2711 reset-names = "ufsphy"; 2712 2713 #phy-cells = <0>; 2714 status = "disabled"; 2715 }; 2716 2717 cryptobam: dma-controller@1dc4000 { 2718 compatible = "qcom,bam-v1.7.4", "qcom,bam-v1.7.0"; 2719 reg = <0 0x01dc4000 0 0x24000>; 2720 interrupts = <GIC_SPI 272 IRQ_TYPE_LEVEL_HIGH>; 2721 clocks = <&rpmhcc RPMH_CE_CLK>; 2722 clock-names = "bam_clk"; 2723 #dma-cells = <1>; 2724 qcom,ee = <0>; 2725 qcom,controlled-remotely; 2726 iommus = <&apps_smmu 0x704 0x1>, 2727 <&apps_smmu 0x706 0x1>, 2728 <&apps_smmu 0x714 0x1>, 2729 <&apps_smmu 0x716 0x1>; 2730 }; 2731 2732 crypto: crypto@1dfa000 { 2733 compatible = "qcom,crypto-v5.4"; 2734 reg = <0 0x01dfa000 0 0x6000>; 2735 clocks = <&gcc GCC_CE1_AHB_CLK>, 2736 <&gcc GCC_CE1_AXI_CLK>, 2737 <&rpmhcc RPMH_CE_CLK>; 2738 clock-names = "iface", "bus", "core"; 2739 dmas = <&cryptobam 6>, <&cryptobam 7>; 2740 dma-names = "rx", "tx"; 2741 iommus = <&apps_smmu 0x704 0x1>, 2742 <&apps_smmu 0x706 0x1>, 2743 <&apps_smmu 0x714 0x1>, 2744 <&apps_smmu 0x716 0x1>; 2745 }; 2746 2747 ipa: ipa@1e40000 { 2748 compatible = "qcom,sdm845-ipa"; 2749 2750 iommus = <&apps_smmu 0x720 0x0>, 2751 <&apps_smmu 0x722 0x0>; 2752 reg = <0 0x01e40000 0 0x7000>, 2753 <0 0x01e47000 0 0x2000>, 2754 <0 0x01e04000 0 0x2c000>; 2755 reg-names = "ipa-reg", 2756 "ipa-shared", 2757 "gsi"; 2758 2759 interrupts-extended = <&intc GIC_SPI 311 IRQ_TYPE_EDGE_RISING>, 2760 <&intc GIC_SPI 432 IRQ_TYPE_LEVEL_HIGH>, 2761 <&ipa_smp2p_in 0 IRQ_TYPE_EDGE_RISING>, 2762 <&ipa_smp2p_in 1 IRQ_TYPE_EDGE_RISING>; 2763 interrupt-names = "ipa", 2764 "gsi", 2765 "ipa-clock-query", 2766 "ipa-setup-ready"; 2767 2768 clocks = <&rpmhcc RPMH_IPA_CLK>; 2769 clock-names = "core"; 2770 2771 interconnects = <&aggre2_noc MASTER_IPA 0 &mem_noc SLAVE_EBI1 0>, 2772 <&aggre2_noc MASTER_IPA 0 &system_noc SLAVE_IMEM 0>, 2773 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_IPA_CFG 0>; 2774 interconnect-names = "memory", 2775 "imem", 2776 "config"; 2777 2778 qcom,smem-states = <&ipa_smp2p_out 0>, 2779 <&ipa_smp2p_out 1>; 2780 qcom,smem-state-names = "ipa-clock-enabled-valid", 2781 "ipa-clock-enabled"; 2782 2783 status = "disabled"; 2784 }; 2785 2786 tcsr_mutex: hwlock@1f40000 { 2787 compatible = "qcom,tcsr-mutex"; 2788 reg = <0 0x01f40000 0 0x20000>; 2789 #hwlock-cells = <1>; 2790 }; 2791 2792 tcsr_regs_1: syscon@1f60000 { 2793 compatible = "qcom,sdm845-tcsr", "syscon"; 2794 reg = <0 0x01f60000 0 0x20000>; 2795 }; 2796 2797 tlmm: pinctrl@3400000 { 2798 compatible = "qcom,sdm845-pinctrl"; 2799 reg = <0 0x03400000 0 0xc00000>; 2800 interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>; 2801 gpio-controller; 2802 #gpio-cells = <2>; 2803 interrupt-controller; 2804 #interrupt-cells = <2>; 2805 gpio-ranges = <&tlmm 0 0 151>; 2806 wakeup-parent = <&pdc_intc>; 2807 2808 cci0_default: cci0-default-state { 2809 /* SDA, SCL */ 2810 pins = "gpio17", "gpio18"; 2811 function = "cci_i2c"; 2812 2813 bias-pull-up; 2814 drive-strength = <2>; /* 2 mA */ 2815 }; 2816 2817 cci0_sleep: cci0-sleep-state { 2818 /* SDA, SCL */ 2819 pins = "gpio17", "gpio18"; 2820 function = "cci_i2c"; 2821 2822 drive-strength = <2>; /* 2 mA */ 2823 bias-pull-down; 2824 }; 2825 2826 cci1_default: cci1-default-state { 2827 /* SDA, SCL */ 2828 pins = "gpio19", "gpio20"; 2829 function = "cci_i2c"; 2830 2831 bias-pull-up; 2832 drive-strength = <2>; /* 2 mA */ 2833 }; 2834 2835 cci1_sleep: cci1-sleep-state { 2836 /* SDA, SCL */ 2837 pins = "gpio19", "gpio20"; 2838 function = "cci_i2c"; 2839 2840 drive-strength = <2>; /* 2 mA */ 2841 bias-pull-down; 2842 }; 2843 2844 qspi_clk: qspi-clk-state { 2845 pins = "gpio95"; 2846 function = "qspi_clk"; 2847 }; 2848 2849 qspi_cs0: qspi-cs0-state { 2850 pins = "gpio90"; 2851 function = "qspi_cs"; 2852 }; 2853 2854 qspi_cs1: qspi-cs1-state { 2855 pins = "gpio89"; 2856 function = "qspi_cs"; 2857 }; 2858 2859 qspi_data0: qspi-data0-state { 2860 pins = "gpio91"; 2861 function = "qspi_data"; 2862 }; 2863 2864 qspi_data1: qspi-data1-state { 2865 pins = "gpio92"; 2866 function = "qspi_data"; 2867 }; 2868 2869 qspi_data23: qspi-data23-state { 2870 pins = "gpio93", "gpio94"; 2871 function = "qspi_data"; 2872 }; 2873 2874 qup_i2c0_default: qup-i2c0-default-state { 2875 pins = "gpio0", "gpio1"; 2876 function = "qup0"; 2877 }; 2878 2879 qup_i2c1_default: qup-i2c1-default-state { 2880 pins = "gpio17", "gpio18"; 2881 function = "qup1"; 2882 }; 2883 2884 qup_i2c2_default: qup-i2c2-default-state { 2885 pins = "gpio27", "gpio28"; 2886 function = "qup2"; 2887 }; 2888 2889 qup_i2c3_default: qup-i2c3-default-state { 2890 pins = "gpio41", "gpio42"; 2891 function = "qup3"; 2892 }; 2893 2894 qup_i2c4_default: qup-i2c4-default-state { 2895 pins = "gpio89", "gpio90"; 2896 function = "qup4"; 2897 }; 2898 2899 qup_i2c5_default: qup-i2c5-default-state { 2900 pins = "gpio85", "gpio86"; 2901 function = "qup5"; 2902 }; 2903 2904 qup_i2c6_default: qup-i2c6-default-state { 2905 pins = "gpio45", "gpio46"; 2906 function = "qup6"; 2907 }; 2908 2909 qup_i2c7_default: qup-i2c7-default-state { 2910 pins = "gpio93", "gpio94"; 2911 function = "qup7"; 2912 }; 2913 2914 qup_i2c8_default: qup-i2c8-default-state { 2915 pins = "gpio65", "gpio66"; 2916 function = "qup8"; 2917 }; 2918 2919 qup_i2c9_default: qup-i2c9-default-state { 2920 pins = "gpio6", "gpio7"; 2921 function = "qup9"; 2922 }; 2923 2924 qup_i2c10_default: qup-i2c10-default-state { 2925 pins = "gpio55", "gpio56"; 2926 function = "qup10"; 2927 }; 2928 2929 qup_i2c11_default: qup-i2c11-default-state { 2930 pins = "gpio31", "gpio32"; 2931 function = "qup11"; 2932 }; 2933 2934 qup_i2c12_default: qup-i2c12-default-state { 2935 pins = "gpio49", "gpio50"; 2936 function = "qup12"; 2937 }; 2938 2939 qup_i2c13_default: qup-i2c13-default-state { 2940 pins = "gpio105", "gpio106"; 2941 function = "qup13"; 2942 }; 2943 2944 qup_i2c14_default: qup-i2c14-default-state { 2945 pins = "gpio33", "gpio34"; 2946 function = "qup14"; 2947 }; 2948 2949 qup_i2c15_default: qup-i2c15-default-state { 2950 pins = "gpio81", "gpio82"; 2951 function = "qup15"; 2952 }; 2953 2954 qup_spi0_default: qup-spi0-default-state { 2955 pins = "gpio0", "gpio1", "gpio2", "gpio3"; 2956 function = "qup0"; 2957 }; 2958 2959 qup_spi1_default: qup-spi1-default-state { 2960 pins = "gpio17", "gpio18", "gpio19", "gpio20"; 2961 function = "qup1"; 2962 }; 2963 2964 qup_spi2_default: qup-spi2-default-state { 2965 pins = "gpio27", "gpio28", "gpio29", "gpio30"; 2966 function = "qup2"; 2967 }; 2968 2969 qup_spi3_default: qup-spi3-default-state { 2970 pins = "gpio41", "gpio42", "gpio43", "gpio44"; 2971 function = "qup3"; 2972 }; 2973 2974 qup_spi4_default: qup-spi4-default-state { 2975 pins = "gpio89", "gpio90", "gpio91", "gpio92"; 2976 function = "qup4"; 2977 }; 2978 2979 qup_spi5_default: qup-spi5-default-state { 2980 pins = "gpio85", "gpio86", "gpio87", "gpio88"; 2981 function = "qup5"; 2982 }; 2983 2984 qup_spi6_default: qup-spi6-default-state { 2985 pins = "gpio45", "gpio46", "gpio47", "gpio48"; 2986 function = "qup6"; 2987 }; 2988 2989 qup_spi7_default: qup-spi7-default-state { 2990 pins = "gpio93", "gpio94", "gpio95", "gpio96"; 2991 function = "qup7"; 2992 }; 2993 2994 qup_spi8_default: qup-spi8-default-state { 2995 pins = "gpio65", "gpio66", "gpio67", "gpio68"; 2996 function = "qup8"; 2997 }; 2998 2999 qup_spi9_default: qup-spi9-default-state { 3000 pins = "gpio6", "gpio7", "gpio4", "gpio5"; 3001 function = "qup9"; 3002 }; 3003 3004 qup_spi10_default: qup-spi10-default-state { 3005 pins = "gpio55", "gpio56", "gpio53", "gpio54"; 3006 function = "qup10"; 3007 }; 3008 3009 qup_spi11_default: qup-spi11-default-state { 3010 pins = "gpio31", "gpio32", "gpio33", "gpio34"; 3011 function = "qup11"; 3012 }; 3013 3014 qup_spi12_default: qup-spi12-default-state { 3015 pins = "gpio49", "gpio50", "gpio51", "gpio52"; 3016 function = "qup12"; 3017 }; 3018 3019 qup_spi13_default: qup-spi13-default-state { 3020 pins = "gpio105", "gpio106", "gpio107", "gpio108"; 3021 function = "qup13"; 3022 }; 3023 3024 qup_spi14_default: qup-spi14-default-state { 3025 pins = "gpio33", "gpio34", "gpio31", "gpio32"; 3026 function = "qup14"; 3027 }; 3028 3029 qup_spi15_default: qup-spi15-default-state { 3030 pins = "gpio81", "gpio82", "gpio83", "gpio84"; 3031 function = "qup15"; 3032 }; 3033 3034 qup_uart0_default: qup-uart0-default-state { 3035 qup_uart0_tx: tx-pins { 3036 pins = "gpio2"; 3037 function = "qup0"; 3038 }; 3039 3040 qup_uart0_rx: rx-pins { 3041 pins = "gpio3"; 3042 function = "qup0"; 3043 }; 3044 }; 3045 3046 qup_uart1_default: qup-uart1-default-state { 3047 qup_uart1_tx: tx-pins { 3048 pins = "gpio19"; 3049 function = "qup1"; 3050 }; 3051 3052 qup_uart1_rx: rx-pins { 3053 pins = "gpio20"; 3054 function = "qup1"; 3055 }; 3056 }; 3057 3058 qup_uart2_default: qup-uart2-default-state { 3059 qup_uart2_tx: tx-pins { 3060 pins = "gpio29"; 3061 function = "qup2"; 3062 }; 3063 3064 qup_uart2_rx: rx-pins { 3065 pins = "gpio30"; 3066 function = "qup2"; 3067 }; 3068 }; 3069 3070 qup_uart3_default: qup-uart3-default-state { 3071 qup_uart3_tx: tx-pins { 3072 pins = "gpio43"; 3073 function = "qup3"; 3074 }; 3075 3076 qup_uart3_rx: rx-pins { 3077 pins = "gpio44"; 3078 function = "qup3"; 3079 }; 3080 }; 3081 3082 qup_uart3_4pin: qup-uart3-4pin-state { 3083 qup_uart3_4pin_cts: cts-pins { 3084 pins = "gpio41"; 3085 function = "qup3"; 3086 }; 3087 3088 qup_uart3_4pin_rts_tx: rts-tx-pins { 3089 pins = "gpio42", "gpio43"; 3090 function = "qup3"; 3091 }; 3092 3093 qup_uart3_4pin_rx: rx-pins { 3094 pins = "gpio44"; 3095 function = "qup3"; 3096 }; 3097 }; 3098 3099 qup_uart4_default: qup-uart4-default-state { 3100 qup_uart4_tx: tx-pins { 3101 pins = "gpio91"; 3102 function = "qup4"; 3103 }; 3104 3105 qup_uart4_rx: rx-pins { 3106 pins = "gpio92"; 3107 function = "qup4"; 3108 }; 3109 }; 3110 3111 qup_uart5_default: qup-uart5-default-state { 3112 qup_uart5_tx: tx-pins { 3113 pins = "gpio87"; 3114 function = "qup5"; 3115 }; 3116 3117 qup_uart5_rx: rx-pins { 3118 pins = "gpio88"; 3119 function = "qup5"; 3120 }; 3121 }; 3122 3123 qup_uart6_default: qup-uart6-default-state { 3124 qup_uart6_tx: tx-pins { 3125 pins = "gpio47"; 3126 function = "qup6"; 3127 }; 3128 3129 qup_uart6_rx: rx-pins { 3130 pins = "gpio48"; 3131 function = "qup6"; 3132 }; 3133 }; 3134 3135 qup_uart6_4pin: qup-uart6-4pin-state { 3136 qup_uart6_4pin_cts: cts-pins { 3137 pins = "gpio45"; 3138 function = "qup6"; 3139 bias-pull-down; 3140 }; 3141 3142 qup_uart6_4pin_rts_tx: rts-tx-pins { 3143 pins = "gpio46", "gpio47"; 3144 function = "qup6"; 3145 drive-strength = <2>; 3146 bias-disable; 3147 }; 3148 3149 qup_uart6_4pin_rx: rx-pins { 3150 pins = "gpio48"; 3151 function = "qup6"; 3152 bias-pull-up; 3153 }; 3154 }; 3155 3156 qup_uart7_default: qup-uart7-default-state { 3157 qup_uart7_tx: tx-pins { 3158 pins = "gpio95"; 3159 function = "qup7"; 3160 }; 3161 3162 qup_uart7_rx: rx-pins { 3163 pins = "gpio96"; 3164 function = "qup7"; 3165 }; 3166 }; 3167 3168 qup_uart8_default: qup-uart8-default-state { 3169 qup_uart8_tx: tx-pins { 3170 pins = "gpio67"; 3171 function = "qup8"; 3172 }; 3173 3174 qup_uart8_rx: rx-pins { 3175 pins = "gpio68"; 3176 function = "qup8"; 3177 }; 3178 }; 3179 3180 qup_uart9_default: qup-uart9-default-state { 3181 qup_uart9_tx: tx-pins { 3182 pins = "gpio4"; 3183 function = "qup9"; 3184 }; 3185 3186 qup_uart9_rx: rx-pins { 3187 pins = "gpio5"; 3188 function = "qup9"; 3189 }; 3190 }; 3191 3192 qup_uart10_default: qup-uart10-default-state { 3193 qup_uart10_tx: tx-pins { 3194 pins = "gpio53"; 3195 function = "qup10"; 3196 }; 3197 3198 qup_uart10_rx: rx-pins { 3199 pins = "gpio54"; 3200 function = "qup10"; 3201 }; 3202 }; 3203 3204 qup_uart11_default: qup-uart11-default-state { 3205 qup_uart11_tx: tx-pins { 3206 pins = "gpio33"; 3207 function = "qup11"; 3208 }; 3209 3210 qup_uart11_rx: rx-pins { 3211 pins = "gpio34"; 3212 function = "qup11"; 3213 }; 3214 }; 3215 3216 qup_uart12_default: qup-uart12-default-state { 3217 qup_uart12_tx: tx-pins { 3218 pins = "gpio51"; 3219 function = "qup0"; 3220 }; 3221 3222 qup_uart12_rx: rx-pins { 3223 pins = "gpio52"; 3224 function = "qup0"; 3225 }; 3226 }; 3227 3228 qup_uart13_default: qup-uart13-default-state { 3229 qup_uart13_tx: tx-pins { 3230 pins = "gpio107"; 3231 function = "qup13"; 3232 }; 3233 3234 qup_uart13_rx: rx-pins { 3235 pins = "gpio108"; 3236 function = "qup13"; 3237 }; 3238 }; 3239 3240 qup_uart14_default: qup-uart14-default-state { 3241 qup_uart14_tx: tx-pins { 3242 pins = "gpio31"; 3243 function = "qup14"; 3244 }; 3245 3246 qup_uart14_rx: rx-pins { 3247 pins = "gpio32"; 3248 function = "qup14"; 3249 }; 3250 }; 3251 3252 qup_uart15_default: qup-uart15-default-state { 3253 qup_uart15_tx: tx-pins { 3254 pins = "gpio83"; 3255 function = "qup15"; 3256 }; 3257 3258 qup_uart15_rx: rx-pins { 3259 pins = "gpio84"; 3260 function = "qup15"; 3261 }; 3262 }; 3263 3264 quat_mi2s_sleep: quat-mi2s-sleep-state { 3265 pins = "gpio58", "gpio59"; 3266 function = "gpio"; 3267 drive-strength = <2>; 3268 bias-pull-down; 3269 }; 3270 3271 quat_mi2s_active: quat-mi2s-active-state { 3272 pins = "gpio58", "gpio59"; 3273 function = "qua_mi2s"; 3274 drive-strength = <8>; 3275 bias-disable; 3276 output-high; 3277 }; 3278 3279 quat_mi2s_sd0_sleep: quat-mi2s-sd0-sleep-state { 3280 pins = "gpio60"; 3281 function = "gpio"; 3282 drive-strength = <2>; 3283 bias-pull-down; 3284 }; 3285 3286 quat_mi2s_sd0_active: quat-mi2s-sd0-active-state { 3287 pins = "gpio60"; 3288 function = "qua_mi2s"; 3289 drive-strength = <8>; 3290 bias-disable; 3291 }; 3292 3293 quat_mi2s_sd1_sleep: quat-mi2s-sd1-sleep-state { 3294 pins = "gpio61"; 3295 function = "gpio"; 3296 drive-strength = <2>; 3297 bias-pull-down; 3298 }; 3299 3300 quat_mi2s_sd1_active: quat-mi2s-sd1-active-state { 3301 pins = "gpio61"; 3302 function = "qua_mi2s"; 3303 drive-strength = <8>; 3304 bias-disable; 3305 }; 3306 3307 quat_mi2s_sd2_sleep: quat-mi2s-sd2-sleep-state { 3308 pins = "gpio62"; 3309 function = "gpio"; 3310 drive-strength = <2>; 3311 bias-pull-down; 3312 }; 3313 3314 quat_mi2s_sd2_active: quat-mi2s-sd2-active-state { 3315 pins = "gpio62"; 3316 function = "qua_mi2s"; 3317 drive-strength = <8>; 3318 bias-disable; 3319 }; 3320 3321 quat_mi2s_sd3_sleep: quat-mi2s-sd3-sleep-state { 3322 pins = "gpio63"; 3323 function = "gpio"; 3324 drive-strength = <2>; 3325 bias-pull-down; 3326 }; 3327 3328 quat_mi2s_sd3_active: quat-mi2s-sd3-active-state { 3329 pins = "gpio63"; 3330 function = "qua_mi2s"; 3331 drive-strength = <8>; 3332 bias-disable; 3333 }; 3334 }; 3335 3336 mss_pil: remoteproc@4080000 { 3337 compatible = "qcom,sdm845-mss-pil"; 3338 reg = <0 0x04080000 0 0x408>, <0 0x04180000 0 0x48>; 3339 reg-names = "qdsp6", "rmb"; 3340 3341 interrupts-extended = 3342 <&intc GIC_SPI 266 IRQ_TYPE_EDGE_RISING>, 3343 <&modem_smp2p_in 0 IRQ_TYPE_EDGE_RISING>, 3344 <&modem_smp2p_in 1 IRQ_TYPE_EDGE_RISING>, 3345 <&modem_smp2p_in 2 IRQ_TYPE_EDGE_RISING>, 3346 <&modem_smp2p_in 3 IRQ_TYPE_EDGE_RISING>, 3347 <&modem_smp2p_in 7 IRQ_TYPE_EDGE_RISING>; 3348 interrupt-names = "wdog", "fatal", "ready", 3349 "handover", "stop-ack", 3350 "shutdown-ack"; 3351 3352 clocks = <&gcc GCC_MSS_CFG_AHB_CLK>, 3353 <&gcc GCC_MSS_Q6_MEMNOC_AXI_CLK>, 3354 <&gcc GCC_BOOT_ROM_AHB_CLK>, 3355 <&gcc GCC_MSS_GPLL0_DIV_CLK_SRC>, 3356 <&gcc GCC_MSS_SNOC_AXI_CLK>, 3357 <&gcc GCC_MSS_MFAB_AXIS_CLK>, 3358 <&gcc GCC_PRNG_AHB_CLK>, 3359 <&rpmhcc RPMH_CXO_CLK>; 3360 clock-names = "iface", "bus", "mem", "gpll0_mss", 3361 "snoc_axi", "mnoc_axi", "prng", "xo"; 3362 3363 qcom,qmp = <&aoss_qmp>; 3364 3365 qcom,smem-states = <&modem_smp2p_out 0>; 3366 qcom,smem-state-names = "stop"; 3367 3368 resets = <&aoss_reset AOSS_CC_MSS_RESTART>, 3369 <&pdc_reset PDC_MODEM_SYNC_RESET>; 3370 reset-names = "mss_restart", "pdc_reset"; 3371 3372 qcom,halt-regs = <&tcsr_regs_1 0x3000 0x5000 0x4000>; 3373 3374 power-domains = <&rpmhpd SDM845_CX>, 3375 <&rpmhpd SDM845_MX>, 3376 <&rpmhpd SDM845_MSS>; 3377 power-domain-names = "cx", "mx", "mss"; 3378 3379 status = "disabled"; 3380 3381 mba { 3382 memory-region = <&mba_region>; 3383 }; 3384 3385 mpss { 3386 memory-region = <&mpss_region>; 3387 }; 3388 3389 metadata { 3390 memory-region = <&mdata_mem>; 3391 }; 3392 3393 glink-edge { 3394 interrupts = <GIC_SPI 449 IRQ_TYPE_EDGE_RISING>; 3395 label = "modem"; 3396 qcom,remote-pid = <1>; 3397 mboxes = <&apss_shared 12>; 3398 }; 3399 }; 3400 3401 gpucc: clock-controller@5090000 { 3402 compatible = "qcom,sdm845-gpucc"; 3403 reg = <0 0x05090000 0 0x9000>; 3404 #clock-cells = <1>; 3405 #reset-cells = <1>; 3406 #power-domain-cells = <1>; 3407 clocks = <&rpmhcc RPMH_CXO_CLK>, 3408 <&gcc GCC_GPU_GPLL0_CLK_SRC>, 3409 <&gcc GCC_GPU_GPLL0_DIV_CLK_SRC>; 3410 clock-names = "bi_tcxo", 3411 "gcc_gpu_gpll0_clk_src", 3412 "gcc_gpu_gpll0_div_clk_src"; 3413 }; 3414 3415 slpi_pas: remoteproc@5c00000 { 3416 compatible = "qcom,sdm845-slpi-pas"; 3417 reg = <0 0x5c00000 0 0x4000>; 3418 3419 interrupts-extended = <&intc GIC_SPI 494 IRQ_TYPE_EDGE_RISING>, 3420 <&slpi_smp2p_in 0 IRQ_TYPE_EDGE_RISING>, 3421 <&slpi_smp2p_in 1 IRQ_TYPE_EDGE_RISING>, 3422 <&slpi_smp2p_in 2 IRQ_TYPE_EDGE_RISING>, 3423 <&slpi_smp2p_in 3 IRQ_TYPE_EDGE_RISING>; 3424 interrupt-names = "wdog", "fatal", "ready", 3425 "handover", "stop-ack"; 3426 3427 clocks = <&rpmhcc RPMH_CXO_CLK>; 3428 clock-names = "xo"; 3429 3430 qcom,qmp = <&aoss_qmp>; 3431 3432 power-domains = <&rpmhpd SDM845_LCX>, 3433 <&rpmhpd SDM845_LMX>; 3434 power-domain-names = "lcx", "lmx"; 3435 3436 memory-region = <&slpi_mem>; 3437 3438 qcom,smem-states = <&slpi_smp2p_out 0>; 3439 qcom,smem-state-names = "stop"; 3440 3441 status = "disabled"; 3442 3443 glink-edge { 3444 interrupts = <GIC_SPI 170 IRQ_TYPE_EDGE_RISING>; 3445 label = "dsps"; 3446 qcom,remote-pid = <3>; 3447 mboxes = <&apss_shared 24>; 3448 3449 fastrpc { 3450 compatible = "qcom,fastrpc"; 3451 qcom,glink-channels = "fastrpcglink-apps-dsp"; 3452 label = "sdsp"; 3453 qcom,non-secure-domain; 3454 qcom,vmids = <QCOM_SCM_VMID_HLOS QCOM_SCM_VMID_MSS_MSA 3455 QCOM_SCM_VMID_SSC_Q6 QCOM_SCM_VMID_ADSP_Q6>; 3456 memory-region = <&fastrpc_mem>; 3457 #address-cells = <1>; 3458 #size-cells = <0>; 3459 3460 compute-cb@0 { 3461 compatible = "qcom,fastrpc-compute-cb"; 3462 reg = <0>; 3463 }; 3464 }; 3465 }; 3466 }; 3467 3468 stm@6002000 { 3469 compatible = "arm,coresight-stm", "arm,primecell"; 3470 reg = <0 0x06002000 0 0x1000>, 3471 <0 0x16280000 0 0x180000>; 3472 reg-names = "stm-base", "stm-stimulus-base"; 3473 3474 clocks = <&aoss_qmp>; 3475 clock-names = "apb_pclk"; 3476 3477 out-ports { 3478 port { 3479 stm_out: endpoint { 3480 remote-endpoint = 3481 <&funnel0_in7>; 3482 }; 3483 }; 3484 }; 3485 }; 3486 3487 funnel@6041000 { 3488 compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; 3489 reg = <0 0x06041000 0 0x1000>; 3490 3491 clocks = <&aoss_qmp>; 3492 clock-names = "apb_pclk"; 3493 3494 out-ports { 3495 port { 3496 funnel0_out: endpoint { 3497 remote-endpoint = 3498 <&merge_funnel_in0>; 3499 }; 3500 }; 3501 }; 3502 3503 in-ports { 3504 #address-cells = <1>; 3505 #size-cells = <0>; 3506 3507 port@7 { 3508 reg = <7>; 3509 funnel0_in7: endpoint { 3510 remote-endpoint = <&stm_out>; 3511 }; 3512 }; 3513 }; 3514 }; 3515 3516 funnel@6043000 { 3517 compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; 3518 reg = <0 0x06043000 0 0x1000>; 3519 3520 clocks = <&aoss_qmp>; 3521 clock-names = "apb_pclk"; 3522 3523 out-ports { 3524 port { 3525 funnel2_out: endpoint { 3526 remote-endpoint = 3527 <&merge_funnel_in2>; 3528 }; 3529 }; 3530 }; 3531 3532 in-ports { 3533 #address-cells = <1>; 3534 #size-cells = <0>; 3535 3536 port@5 { 3537 reg = <5>; 3538 funnel2_in5: endpoint { 3539 remote-endpoint = 3540 <&apss_merge_funnel_out>; 3541 }; 3542 }; 3543 }; 3544 }; 3545 3546 funnel@6045000 { 3547 compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; 3548 reg = <0 0x06045000 0 0x1000>; 3549 3550 clocks = <&aoss_qmp>; 3551 clock-names = "apb_pclk"; 3552 3553 out-ports { 3554 port { 3555 merge_funnel_out: endpoint { 3556 remote-endpoint = <&etf_in>; 3557 }; 3558 }; 3559 }; 3560 3561 in-ports { 3562 #address-cells = <1>; 3563 #size-cells = <0>; 3564 3565 port@0 { 3566 reg = <0>; 3567 merge_funnel_in0: endpoint { 3568 remote-endpoint = 3569 <&funnel0_out>; 3570 }; 3571 }; 3572 3573 port@2 { 3574 reg = <2>; 3575 merge_funnel_in2: endpoint { 3576 remote-endpoint = 3577 <&funnel2_out>; 3578 }; 3579 }; 3580 }; 3581 }; 3582 3583 replicator@6046000 { 3584 compatible = "arm,coresight-dynamic-replicator", "arm,primecell"; 3585 reg = <0 0x06046000 0 0x1000>; 3586 3587 clocks = <&aoss_qmp>; 3588 clock-names = "apb_pclk"; 3589 3590 out-ports { 3591 port { 3592 replicator_out: endpoint { 3593 remote-endpoint = <&etr_in>; 3594 }; 3595 }; 3596 }; 3597 3598 in-ports { 3599 port { 3600 replicator_in: endpoint { 3601 remote-endpoint = <&etf_out>; 3602 }; 3603 }; 3604 }; 3605 }; 3606 3607 etf@6047000 { 3608 compatible = "arm,coresight-tmc", "arm,primecell"; 3609 reg = <0 0x06047000 0 0x1000>; 3610 3611 clocks = <&aoss_qmp>; 3612 clock-names = "apb_pclk"; 3613 3614 out-ports { 3615 port { 3616 etf_out: endpoint { 3617 remote-endpoint = 3618 <&replicator_in>; 3619 }; 3620 }; 3621 }; 3622 3623 in-ports { 3624 3625 port { 3626 etf_in: endpoint { 3627 remote-endpoint = 3628 <&merge_funnel_out>; 3629 }; 3630 }; 3631 }; 3632 }; 3633 3634 etr@6048000 { 3635 compatible = "arm,coresight-tmc", "arm,primecell"; 3636 reg = <0 0x06048000 0 0x1000>; 3637 3638 clocks = <&aoss_qmp>; 3639 clock-names = "apb_pclk"; 3640 arm,scatter-gather; 3641 3642 in-ports { 3643 port { 3644 etr_in: endpoint { 3645 remote-endpoint = 3646 <&replicator_out>; 3647 }; 3648 }; 3649 }; 3650 }; 3651 3652 etm@7040000 { 3653 compatible = "arm,coresight-etm4x", "arm,primecell"; 3654 reg = <0 0x07040000 0 0x1000>; 3655 3656 cpu = <&cpu0>; 3657 3658 clocks = <&aoss_qmp>; 3659 clock-names = "apb_pclk"; 3660 arm,coresight-loses-context-with-cpu; 3661 3662 out-ports { 3663 port { 3664 etm0_out: endpoint { 3665 remote-endpoint = 3666 <&apss_funnel_in0>; 3667 }; 3668 }; 3669 }; 3670 }; 3671 3672 etm@7140000 { 3673 compatible = "arm,coresight-etm4x", "arm,primecell"; 3674 reg = <0 0x07140000 0 0x1000>; 3675 3676 cpu = <&cpu1>; 3677 3678 clocks = <&aoss_qmp>; 3679 clock-names = "apb_pclk"; 3680 arm,coresight-loses-context-with-cpu; 3681 3682 out-ports { 3683 port { 3684 etm1_out: endpoint { 3685 remote-endpoint = 3686 <&apss_funnel_in1>; 3687 }; 3688 }; 3689 }; 3690 }; 3691 3692 etm@7240000 { 3693 compatible = "arm,coresight-etm4x", "arm,primecell"; 3694 reg = <0 0x07240000 0 0x1000>; 3695 3696 cpu = <&cpu2>; 3697 3698 clocks = <&aoss_qmp>; 3699 clock-names = "apb_pclk"; 3700 arm,coresight-loses-context-with-cpu; 3701 3702 out-ports { 3703 port { 3704 etm2_out: endpoint { 3705 remote-endpoint = 3706 <&apss_funnel_in2>; 3707 }; 3708 }; 3709 }; 3710 }; 3711 3712 etm@7340000 { 3713 compatible = "arm,coresight-etm4x", "arm,primecell"; 3714 reg = <0 0x07340000 0 0x1000>; 3715 3716 cpu = <&cpu3>; 3717 3718 clocks = <&aoss_qmp>; 3719 clock-names = "apb_pclk"; 3720 arm,coresight-loses-context-with-cpu; 3721 3722 out-ports { 3723 port { 3724 etm3_out: endpoint { 3725 remote-endpoint = 3726 <&apss_funnel_in3>; 3727 }; 3728 }; 3729 }; 3730 }; 3731 3732 etm@7440000 { 3733 compatible = "arm,coresight-etm4x", "arm,primecell"; 3734 reg = <0 0x07440000 0 0x1000>; 3735 3736 cpu = <&cpu4>; 3737 3738 clocks = <&aoss_qmp>; 3739 clock-names = "apb_pclk"; 3740 arm,coresight-loses-context-with-cpu; 3741 3742 out-ports { 3743 port { 3744 etm4_out: endpoint { 3745 remote-endpoint = 3746 <&apss_funnel_in4>; 3747 }; 3748 }; 3749 }; 3750 }; 3751 3752 etm@7540000 { 3753 compatible = "arm,coresight-etm4x", "arm,primecell"; 3754 reg = <0 0x07540000 0 0x1000>; 3755 3756 cpu = <&cpu5>; 3757 3758 clocks = <&aoss_qmp>; 3759 clock-names = "apb_pclk"; 3760 arm,coresight-loses-context-with-cpu; 3761 3762 out-ports { 3763 port { 3764 etm5_out: endpoint { 3765 remote-endpoint = 3766 <&apss_funnel_in5>; 3767 }; 3768 }; 3769 }; 3770 }; 3771 3772 etm@7640000 { 3773 compatible = "arm,coresight-etm4x", "arm,primecell"; 3774 reg = <0 0x07640000 0 0x1000>; 3775 3776 cpu = <&cpu6>; 3777 3778 clocks = <&aoss_qmp>; 3779 clock-names = "apb_pclk"; 3780 arm,coresight-loses-context-with-cpu; 3781 3782 out-ports { 3783 port { 3784 etm6_out: endpoint { 3785 remote-endpoint = 3786 <&apss_funnel_in6>; 3787 }; 3788 }; 3789 }; 3790 }; 3791 3792 etm@7740000 { 3793 compatible = "arm,coresight-etm4x", "arm,primecell"; 3794 reg = <0 0x07740000 0 0x1000>; 3795 3796 cpu = <&cpu7>; 3797 3798 clocks = <&aoss_qmp>; 3799 clock-names = "apb_pclk"; 3800 arm,coresight-loses-context-with-cpu; 3801 3802 out-ports { 3803 port { 3804 etm7_out: endpoint { 3805 remote-endpoint = 3806 <&apss_funnel_in7>; 3807 }; 3808 }; 3809 }; 3810 }; 3811 3812 funnel@7800000 { /* APSS Funnel */ 3813 compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; 3814 reg = <0 0x07800000 0 0x1000>; 3815 3816 clocks = <&aoss_qmp>; 3817 clock-names = "apb_pclk"; 3818 3819 out-ports { 3820 port { 3821 apss_funnel_out: endpoint { 3822 remote-endpoint = 3823 <&apss_merge_funnel_in>; 3824 }; 3825 }; 3826 }; 3827 3828 in-ports { 3829 #address-cells = <1>; 3830 #size-cells = <0>; 3831 3832 port@0 { 3833 reg = <0>; 3834 apss_funnel_in0: endpoint { 3835 remote-endpoint = 3836 <&etm0_out>; 3837 }; 3838 }; 3839 3840 port@1 { 3841 reg = <1>; 3842 apss_funnel_in1: endpoint { 3843 remote-endpoint = 3844 <&etm1_out>; 3845 }; 3846 }; 3847 3848 port@2 { 3849 reg = <2>; 3850 apss_funnel_in2: endpoint { 3851 remote-endpoint = 3852 <&etm2_out>; 3853 }; 3854 }; 3855 3856 port@3 { 3857 reg = <3>; 3858 apss_funnel_in3: endpoint { 3859 remote-endpoint = 3860 <&etm3_out>; 3861 }; 3862 }; 3863 3864 port@4 { 3865 reg = <4>; 3866 apss_funnel_in4: endpoint { 3867 remote-endpoint = 3868 <&etm4_out>; 3869 }; 3870 }; 3871 3872 port@5 { 3873 reg = <5>; 3874 apss_funnel_in5: endpoint { 3875 remote-endpoint = 3876 <&etm5_out>; 3877 }; 3878 }; 3879 3880 port@6 { 3881 reg = <6>; 3882 apss_funnel_in6: endpoint { 3883 remote-endpoint = 3884 <&etm6_out>; 3885 }; 3886 }; 3887 3888 port@7 { 3889 reg = <7>; 3890 apss_funnel_in7: endpoint { 3891 remote-endpoint = 3892 <&etm7_out>; 3893 }; 3894 }; 3895 }; 3896 }; 3897 3898 funnel@7810000 { 3899 compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; 3900 reg = <0 0x07810000 0 0x1000>; 3901 3902 clocks = <&aoss_qmp>; 3903 clock-names = "apb_pclk"; 3904 3905 out-ports { 3906 port { 3907 apss_merge_funnel_out: endpoint { 3908 remote-endpoint = 3909 <&funnel2_in5>; 3910 }; 3911 }; 3912 }; 3913 3914 in-ports { 3915 port { 3916 apss_merge_funnel_in: endpoint { 3917 remote-endpoint = 3918 <&apss_funnel_out>; 3919 }; 3920 }; 3921 }; 3922 }; 3923 3924 sdhc_2: mmc@8804000 { 3925 compatible = "qcom,sdm845-sdhci", "qcom,sdhci-msm-v5"; 3926 reg = <0 0x08804000 0 0x1000>; 3927 3928 interrupts = <GIC_SPI 204 IRQ_TYPE_LEVEL_HIGH>, 3929 <GIC_SPI 222 IRQ_TYPE_LEVEL_HIGH>; 3930 interrupt-names = "hc_irq", "pwr_irq"; 3931 3932 clocks = <&gcc GCC_SDCC2_AHB_CLK>, 3933 <&gcc GCC_SDCC2_APPS_CLK>, 3934 <&rpmhcc RPMH_CXO_CLK>; 3935 clock-names = "iface", "core", "xo"; 3936 iommus = <&apps_smmu 0xa0 0xf>; 3937 power-domains = <&rpmhpd SDM845_CX>; 3938 operating-points-v2 = <&sdhc2_opp_table>; 3939 3940 status = "disabled"; 3941 3942 sdhc2_opp_table: opp-table { 3943 compatible = "operating-points-v2"; 3944 3945 opp-9600000 { 3946 opp-hz = /bits/ 64 <9600000>; 3947 required-opps = <&rpmhpd_opp_min_svs>; 3948 }; 3949 3950 opp-19200000 { 3951 opp-hz = /bits/ 64 <19200000>; 3952 required-opps = <&rpmhpd_opp_low_svs>; 3953 }; 3954 3955 opp-100000000 { 3956 opp-hz = /bits/ 64 <100000000>; 3957 required-opps = <&rpmhpd_opp_svs>; 3958 }; 3959 3960 opp-201500000 { 3961 opp-hz = /bits/ 64 <201500000>; 3962 required-opps = <&rpmhpd_opp_svs_l1>; 3963 }; 3964 }; 3965 }; 3966 3967 qspi: spi@88df000 { 3968 compatible = "qcom,sdm845-qspi", "qcom,qspi-v1"; 3969 reg = <0 0x088df000 0 0x600>; 3970 iommus = <&apps_smmu 0x160 0x0>; 3971 #address-cells = <1>; 3972 #size-cells = <0>; 3973 interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>; 3974 clocks = <&gcc GCC_QSPI_CNOC_PERIPH_AHB_CLK>, 3975 <&gcc GCC_QSPI_CORE_CLK>; 3976 clock-names = "iface", "core"; 3977 power-domains = <&rpmhpd SDM845_CX>; 3978 operating-points-v2 = <&qspi_opp_table>; 3979 status = "disabled"; 3980 }; 3981 3982 slim: slim-ngd@171c0000 { 3983 compatible = "qcom,slim-ngd-v2.1.0"; 3984 reg = <0 0x171c0000 0 0x2c000>; 3985 interrupts = <GIC_SPI 163 IRQ_TYPE_LEVEL_HIGH>; 3986 3987 dmas = <&slimbam 3>, <&slimbam 4>; 3988 dma-names = "rx", "tx"; 3989 3990 iommus = <&apps_smmu 0x1806 0x0>; 3991 #address-cells = <1>; 3992 #size-cells = <0>; 3993 status = "disabled"; 3994 }; 3995 3996 lmh_cluster1: lmh@17d70800 { 3997 compatible = "qcom,sdm845-lmh"; 3998 reg = <0 0x17d70800 0 0x400>; 3999 interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>; 4000 cpus = <&cpu4>; 4001 qcom,lmh-temp-arm-millicelsius = <65000>; 4002 qcom,lmh-temp-low-millicelsius = <94500>; 4003 qcom,lmh-temp-high-millicelsius = <95000>; 4004 interrupt-controller; 4005 #interrupt-cells = <1>; 4006 }; 4007 4008 lmh_cluster0: lmh@17d78800 { 4009 compatible = "qcom,sdm845-lmh"; 4010 reg = <0 0x17d78800 0 0x400>; 4011 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>; 4012 cpus = <&cpu0>; 4013 qcom,lmh-temp-arm-millicelsius = <65000>; 4014 qcom,lmh-temp-low-millicelsius = <94500>; 4015 qcom,lmh-temp-high-millicelsius = <95000>; 4016 interrupt-controller; 4017 #interrupt-cells = <1>; 4018 }; 4019 4020 usb_1_hsphy: phy@88e2000 { 4021 compatible = "qcom,sdm845-qusb2-phy", "qcom,qusb2-v2-phy"; 4022 reg = <0 0x088e2000 0 0x400>; 4023 status = "disabled"; 4024 #phy-cells = <0>; 4025 4026 clocks = <&gcc GCC_USB_PHY_CFG_AHB2PHY_CLK>, 4027 <&rpmhcc RPMH_CXO_CLK>; 4028 clock-names = "cfg_ahb", "ref"; 4029 4030 resets = <&gcc GCC_QUSB2PHY_PRIM_BCR>; 4031 4032 nvmem-cells = <&qusb2p_hstx_trim>; 4033 }; 4034 4035 usb_2_hsphy: phy@88e3000 { 4036 compatible = "qcom,sdm845-qusb2-phy", "qcom,qusb2-v2-phy"; 4037 reg = <0 0x088e3000 0 0x400>; 4038 status = "disabled"; 4039 #phy-cells = <0>; 4040 4041 clocks = <&gcc GCC_USB_PHY_CFG_AHB2PHY_CLK>, 4042 <&rpmhcc RPMH_CXO_CLK>; 4043 clock-names = "cfg_ahb", "ref"; 4044 4045 resets = <&gcc GCC_QUSB2PHY_SEC_BCR>; 4046 4047 nvmem-cells = <&qusb2s_hstx_trim>; 4048 }; 4049 4050 usb_1_qmpphy: phy@88e8000 { 4051 compatible = "qcom,sdm845-qmp-usb3-dp-phy"; 4052 reg = <0 0x088e8000 0 0x3000>; 4053 status = "disabled"; 4054 4055 clocks = <&gcc GCC_USB3_PRIM_PHY_AUX_CLK>, 4056 <&gcc GCC_USB3_PRIM_CLKREF_CLK>, 4057 <&gcc GCC_USB3_PRIM_PHY_COM_AUX_CLK>, 4058 <&gcc GCC_USB3_PRIM_PHY_PIPE_CLK>, 4059 <&gcc GCC_USB_PHY_CFG_AHB2PHY_CLK>; 4060 clock-names = "aux", 4061 "ref", 4062 "com_aux", 4063 "usb3_pipe", 4064 "cfg_ahb"; 4065 4066 resets = <&gcc GCC_USB3_PHY_PRIM_BCR>, 4067 <&gcc GCC_USB3_DP_PHY_PRIM_BCR>; 4068 reset-names = "phy", "common"; 4069 4070 #clock-cells = <1>; 4071 #phy-cells = <1>; 4072 orientation-switch; 4073 4074 ports { 4075 #address-cells = <1>; 4076 #size-cells = <0>; 4077 4078 port@0 { 4079 reg = <0>; 4080 4081 usb_1_qmpphy_out: endpoint { 4082 }; 4083 }; 4084 4085 port@1 { 4086 reg = <1>; 4087 4088 usb_1_qmpphy_usb_ss_in: endpoint { 4089 remote-endpoint = <&usb_1_dwc3_ss>; 4090 }; 4091 }; 4092 4093 port@2 { 4094 reg = <2>; 4095 4096 usb_1_qmpphy_dp_in: endpoint { 4097 remote-endpoint = <&mdss_dp_out>; 4098 }; 4099 }; 4100 }; 4101 }; 4102 4103 usb_2_qmpphy: phy@88eb000 { 4104 compatible = "qcom,sdm845-qmp-usb3-uni-phy"; 4105 reg = <0 0x088eb000 0 0x1000>; 4106 4107 clocks = <&gcc GCC_USB3_SEC_PHY_AUX_CLK>, 4108 <&gcc GCC_USB_PHY_CFG_AHB2PHY_CLK>, 4109 <&gcc GCC_USB3_SEC_CLKREF_CLK>, 4110 <&gcc GCC_USB3_SEC_PHY_COM_AUX_CLK>, 4111 <&gcc GCC_USB3_SEC_PHY_PIPE_CLK>; 4112 clock-names = "aux", 4113 "cfg_ahb", 4114 "ref", 4115 "com_aux", 4116 "pipe"; 4117 clock-output-names = "usb3_uni_phy_pipe_clk_src"; 4118 #clock-cells = <0>; 4119 #phy-cells = <0>; 4120 4121 resets = <&gcc GCC_USB3_PHY_SEC_BCR>, 4122 <&gcc GCC_USB3PHY_PHY_SEC_BCR>; 4123 reset-names = "phy", 4124 "phy_phy"; 4125 4126 status = "disabled"; 4127 }; 4128 4129 usb_1: usb@a6f8800 { 4130 compatible = "qcom,sdm845-dwc3", "qcom,dwc3"; 4131 reg = <0 0x0a6f8800 0 0x400>; 4132 status = "disabled"; 4133 #address-cells = <2>; 4134 #size-cells = <2>; 4135 ranges; 4136 dma-ranges; 4137 4138 clocks = <&gcc GCC_CFG_NOC_USB3_PRIM_AXI_CLK>, 4139 <&gcc GCC_USB30_PRIM_MASTER_CLK>, 4140 <&gcc GCC_AGGRE_USB3_PRIM_AXI_CLK>, 4141 <&gcc GCC_USB30_PRIM_SLEEP_CLK>, 4142 <&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>; 4143 clock-names = "cfg_noc", 4144 "core", 4145 "iface", 4146 "sleep", 4147 "mock_utmi"; 4148 4149 assigned-clocks = <&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>, 4150 <&gcc GCC_USB30_PRIM_MASTER_CLK>; 4151 assigned-clock-rates = <19200000>, <150000000>; 4152 4153 interrupts-extended = <&intc GIC_SPI 130 IRQ_TYPE_LEVEL_HIGH>, 4154 <&intc GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>, 4155 <&pdc_intc 9 IRQ_TYPE_EDGE_BOTH>, 4156 <&pdc_intc 8 IRQ_TYPE_EDGE_BOTH>, 4157 <&pdc_intc 6 IRQ_TYPE_LEVEL_HIGH>; 4158 interrupt-names = "pwr_event", 4159 "hs_phy_irq", 4160 "dp_hs_phy_irq", 4161 "dm_hs_phy_irq", 4162 "ss_phy_irq"; 4163 4164 power-domains = <&gcc USB30_PRIM_GDSC>; 4165 4166 resets = <&gcc GCC_USB30_PRIM_BCR>; 4167 4168 interconnects = <&aggre2_noc MASTER_USB3_0 0 &mem_noc SLAVE_EBI1 0>, 4169 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_USB3_0 0>; 4170 interconnect-names = "usb-ddr", "apps-usb"; 4171 4172 usb_1_dwc3: usb@a600000 { 4173 compatible = "snps,dwc3"; 4174 reg = <0 0x0a600000 0 0xcd00>; 4175 interrupts = <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>; 4176 iommus = <&apps_smmu 0x740 0>; 4177 snps,dis_u2_susphy_quirk; 4178 snps,dis_enblslpm_quirk; 4179 snps,parkmode-disable-ss-quirk; 4180 snps,dis-u1-entry-quirk; 4181 snps,dis-u2-entry-quirk; 4182 phys = <&usb_1_hsphy>, <&usb_1_qmpphy QMP_USB43DP_USB3_PHY>; 4183 phy-names = "usb2-phy", "usb3-phy"; 4184 4185 ports { 4186 #address-cells = <1>; 4187 #size-cells = <0>; 4188 4189 port@0 { 4190 reg = <0>; 4191 4192 usb_1_dwc3_hs: endpoint { 4193 }; 4194 }; 4195 4196 port@1 { 4197 reg = <1>; 4198 4199 usb_1_dwc3_ss: endpoint { 4200 remote-endpoint = <&usb_1_qmpphy_usb_ss_in>; 4201 }; 4202 }; 4203 }; 4204 }; 4205 }; 4206 4207 usb_2: usb@a8f8800 { 4208 compatible = "qcom,sdm845-dwc3", "qcom,dwc3"; 4209 reg = <0 0x0a8f8800 0 0x400>; 4210 status = "disabled"; 4211 #address-cells = <2>; 4212 #size-cells = <2>; 4213 ranges; 4214 dma-ranges; 4215 4216 clocks = <&gcc GCC_CFG_NOC_USB3_SEC_AXI_CLK>, 4217 <&gcc GCC_USB30_SEC_MASTER_CLK>, 4218 <&gcc GCC_AGGRE_USB3_SEC_AXI_CLK>, 4219 <&gcc GCC_USB30_SEC_SLEEP_CLK>, 4220 <&gcc GCC_USB30_SEC_MOCK_UTMI_CLK>; 4221 clock-names = "cfg_noc", 4222 "core", 4223 "iface", 4224 "sleep", 4225 "mock_utmi"; 4226 4227 assigned-clocks = <&gcc GCC_USB30_SEC_MOCK_UTMI_CLK>, 4228 <&gcc GCC_USB30_SEC_MASTER_CLK>; 4229 assigned-clock-rates = <19200000>, <150000000>; 4230 4231 interrupts-extended = <&intc GIC_SPI 135 IRQ_TYPE_LEVEL_HIGH>, 4232 <&intc GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>, 4233 <&pdc_intc 11 IRQ_TYPE_EDGE_BOTH>, 4234 <&pdc_intc 10 IRQ_TYPE_EDGE_BOTH>, 4235 <&pdc_intc 7 IRQ_TYPE_LEVEL_HIGH>; 4236 interrupt-names = "pwr_event", 4237 "hs_phy_irq", 4238 "dp_hs_phy_irq", 4239 "dm_hs_phy_irq", 4240 "ss_phy_irq"; 4241 4242 power-domains = <&gcc USB30_SEC_GDSC>; 4243 4244 resets = <&gcc GCC_USB30_SEC_BCR>; 4245 4246 interconnects = <&aggre2_noc MASTER_USB3_1 0 &mem_noc SLAVE_EBI1 0>, 4247 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_USB3_1 0>; 4248 interconnect-names = "usb-ddr", "apps-usb"; 4249 4250 usb_2_dwc3: usb@a800000 { 4251 compatible = "snps,dwc3"; 4252 reg = <0 0x0a800000 0 0xcd00>; 4253 interrupts = <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>; 4254 iommus = <&apps_smmu 0x760 0>; 4255 snps,dis_u2_susphy_quirk; 4256 snps,dis_enblslpm_quirk; 4257 snps,parkmode-disable-ss-quirk; 4258 snps,dis-u1-entry-quirk; 4259 snps,dis-u2-entry-quirk; 4260 phys = <&usb_2_hsphy>, <&usb_2_qmpphy>; 4261 phy-names = "usb2-phy", "usb3-phy"; 4262 }; 4263 }; 4264 4265 venus: video-codec@aa00000 { 4266 compatible = "qcom,sdm845-venus-v2"; 4267 reg = <0 0x0aa00000 0 0xff000>; 4268 interrupts = <GIC_SPI 174 IRQ_TYPE_LEVEL_HIGH>; 4269 power-domains = <&videocc VENUS_GDSC>, 4270 <&videocc VCODEC0_GDSC>, 4271 <&videocc VCODEC1_GDSC>, 4272 <&rpmhpd SDM845_CX>; 4273 power-domain-names = "venus", "vcodec0", "vcodec1", "cx"; 4274 operating-points-v2 = <&venus_opp_table>; 4275 clocks = <&videocc VIDEO_CC_VENUS_CTL_CORE_CLK>, 4276 <&videocc VIDEO_CC_VENUS_AHB_CLK>, 4277 <&videocc VIDEO_CC_VENUS_CTL_AXI_CLK>, 4278 <&videocc VIDEO_CC_VCODEC0_CORE_CLK>, 4279 <&videocc VIDEO_CC_VCODEC0_AXI_CLK>, 4280 <&videocc VIDEO_CC_VCODEC1_CORE_CLK>, 4281 <&videocc VIDEO_CC_VCODEC1_AXI_CLK>; 4282 clock-names = "core", "iface", "bus", 4283 "vcodec0_core", "vcodec0_bus", 4284 "vcodec1_core", "vcodec1_bus"; 4285 iommus = <&apps_smmu 0x10a0 0x8>, 4286 <&apps_smmu 0x10b0 0x0>; 4287 memory-region = <&venus_mem>; 4288 interconnects = <&mmss_noc MASTER_VIDEO_P0 0 &mem_noc SLAVE_EBI1 0>, 4289 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_VENUS_CFG 0>; 4290 interconnect-names = "video-mem", "cpu-cfg"; 4291 4292 status = "disabled"; 4293 4294 venus_opp_table: opp-table { 4295 compatible = "operating-points-v2"; 4296 4297 opp-100000000 { 4298 opp-hz = /bits/ 64 <100000000>; 4299 required-opps = <&rpmhpd_opp_min_svs>; 4300 }; 4301 4302 opp-200000000 { 4303 opp-hz = /bits/ 64 <200000000>; 4304 required-opps = <&rpmhpd_opp_low_svs>; 4305 }; 4306 4307 opp-320000000 { 4308 opp-hz = /bits/ 64 <320000000>; 4309 required-opps = <&rpmhpd_opp_svs>; 4310 }; 4311 4312 opp-380000000 { 4313 opp-hz = /bits/ 64 <380000000>; 4314 required-opps = <&rpmhpd_opp_svs_l1>; 4315 }; 4316 4317 opp-444000000 { 4318 opp-hz = /bits/ 64 <444000000>; 4319 required-opps = <&rpmhpd_opp_nom>; 4320 }; 4321 4322 opp-533000097 { 4323 opp-hz = /bits/ 64 <533000097>; 4324 required-opps = <&rpmhpd_opp_turbo>; 4325 }; 4326 }; 4327 }; 4328 4329 videocc: clock-controller@ab00000 { 4330 compatible = "qcom,sdm845-videocc"; 4331 reg = <0 0x0ab00000 0 0x10000>; 4332 clocks = <&rpmhcc RPMH_CXO_CLK>; 4333 clock-names = "bi_tcxo"; 4334 #clock-cells = <1>; 4335 #power-domain-cells = <1>; 4336 #reset-cells = <1>; 4337 }; 4338 4339 camss: camss@acb3000 { 4340 compatible = "qcom,sdm845-camss"; 4341 4342 reg = <0 0x0acb3000 0 0x1000>, 4343 <0 0x0acba000 0 0x1000>, 4344 <0 0x0acc8000 0 0x1000>, 4345 <0 0x0ac65000 0 0x1000>, 4346 <0 0x0ac66000 0 0x1000>, 4347 <0 0x0ac67000 0 0x1000>, 4348 <0 0x0ac68000 0 0x1000>, 4349 <0 0x0acaf000 0 0x4000>, 4350 <0 0x0acb6000 0 0x4000>, 4351 <0 0x0acc4000 0 0x4000>; 4352 reg-names = "csid0", 4353 "csid1", 4354 "csid2", 4355 "csiphy0", 4356 "csiphy1", 4357 "csiphy2", 4358 "csiphy3", 4359 "vfe0", 4360 "vfe1", 4361 "vfe_lite"; 4362 4363 interrupts = <GIC_SPI 464 IRQ_TYPE_EDGE_RISING>, 4364 <GIC_SPI 466 IRQ_TYPE_EDGE_RISING>, 4365 <GIC_SPI 468 IRQ_TYPE_EDGE_RISING>, 4366 <GIC_SPI 477 IRQ_TYPE_EDGE_RISING>, 4367 <GIC_SPI 478 IRQ_TYPE_EDGE_RISING>, 4368 <GIC_SPI 479 IRQ_TYPE_EDGE_RISING>, 4369 <GIC_SPI 448 IRQ_TYPE_EDGE_RISING>, 4370 <GIC_SPI 465 IRQ_TYPE_EDGE_RISING>, 4371 <GIC_SPI 467 IRQ_TYPE_EDGE_RISING>, 4372 <GIC_SPI 469 IRQ_TYPE_EDGE_RISING>; 4373 interrupt-names = "csid0", 4374 "csid1", 4375 "csid2", 4376 "csiphy0", 4377 "csiphy1", 4378 "csiphy2", 4379 "csiphy3", 4380 "vfe0", 4381 "vfe1", 4382 "vfe_lite"; 4383 4384 power-domains = <&clock_camcc IFE_0_GDSC>, 4385 <&clock_camcc IFE_1_GDSC>, 4386 <&clock_camcc TITAN_TOP_GDSC>; 4387 4388 clocks = <&clock_camcc CAM_CC_CAMNOC_AXI_CLK>, 4389 <&clock_camcc CAM_CC_CPAS_AHB_CLK>, 4390 <&clock_camcc CAM_CC_CPHY_RX_CLK_SRC>, 4391 <&clock_camcc CAM_CC_IFE_0_CSID_CLK>, 4392 <&clock_camcc CAM_CC_IFE_0_CSID_CLK_SRC>, 4393 <&clock_camcc CAM_CC_IFE_1_CSID_CLK>, 4394 <&clock_camcc CAM_CC_IFE_1_CSID_CLK_SRC>, 4395 <&clock_camcc CAM_CC_IFE_LITE_CSID_CLK>, 4396 <&clock_camcc CAM_CC_IFE_LITE_CSID_CLK_SRC>, 4397 <&clock_camcc CAM_CC_CSIPHY0_CLK>, 4398 <&clock_camcc CAM_CC_CSI0PHYTIMER_CLK>, 4399 <&clock_camcc CAM_CC_CSI0PHYTIMER_CLK_SRC>, 4400 <&clock_camcc CAM_CC_CSIPHY1_CLK>, 4401 <&clock_camcc CAM_CC_CSI1PHYTIMER_CLK>, 4402 <&clock_camcc CAM_CC_CSI1PHYTIMER_CLK_SRC>, 4403 <&clock_camcc CAM_CC_CSIPHY2_CLK>, 4404 <&clock_camcc CAM_CC_CSI2PHYTIMER_CLK>, 4405 <&clock_camcc CAM_CC_CSI2PHYTIMER_CLK_SRC>, 4406 <&clock_camcc CAM_CC_CSIPHY3_CLK>, 4407 <&clock_camcc CAM_CC_CSI3PHYTIMER_CLK>, 4408 <&clock_camcc CAM_CC_CSI3PHYTIMER_CLK_SRC>, 4409 <&gcc GCC_CAMERA_AHB_CLK>, 4410 <&gcc GCC_CAMERA_AXI_CLK>, 4411 <&clock_camcc CAM_CC_SLOW_AHB_CLK_SRC>, 4412 <&clock_camcc CAM_CC_SOC_AHB_CLK>, 4413 <&clock_camcc CAM_CC_IFE_0_AXI_CLK>, 4414 <&clock_camcc CAM_CC_IFE_0_CLK>, 4415 <&clock_camcc CAM_CC_IFE_0_CPHY_RX_CLK>, 4416 <&clock_camcc CAM_CC_IFE_0_CLK_SRC>, 4417 <&clock_camcc CAM_CC_IFE_1_AXI_CLK>, 4418 <&clock_camcc CAM_CC_IFE_1_CLK>, 4419 <&clock_camcc CAM_CC_IFE_1_CPHY_RX_CLK>, 4420 <&clock_camcc CAM_CC_IFE_1_CLK_SRC>, 4421 <&clock_camcc CAM_CC_IFE_LITE_CLK>, 4422 <&clock_camcc CAM_CC_IFE_LITE_CPHY_RX_CLK>, 4423 <&clock_camcc CAM_CC_IFE_LITE_CLK_SRC>; 4424 clock-names = "camnoc_axi", 4425 "cpas_ahb", 4426 "cphy_rx_src", 4427 "csi0", 4428 "csi0_src", 4429 "csi1", 4430 "csi1_src", 4431 "csi2", 4432 "csi2_src", 4433 "csiphy0", 4434 "csiphy0_timer", 4435 "csiphy0_timer_src", 4436 "csiphy1", 4437 "csiphy1_timer", 4438 "csiphy1_timer_src", 4439 "csiphy2", 4440 "csiphy2_timer", 4441 "csiphy2_timer_src", 4442 "csiphy3", 4443 "csiphy3_timer", 4444 "csiphy3_timer_src", 4445 "gcc_camera_ahb", 4446 "gcc_camera_axi", 4447 "slow_ahb_src", 4448 "soc_ahb", 4449 "vfe0_axi", 4450 "vfe0", 4451 "vfe0_cphy_rx", 4452 "vfe0_src", 4453 "vfe1_axi", 4454 "vfe1", 4455 "vfe1_cphy_rx", 4456 "vfe1_src", 4457 "vfe_lite", 4458 "vfe_lite_cphy_rx", 4459 "vfe_lite_src"; 4460 4461 iommus = <&apps_smmu 0x0808 0x0>, 4462 <&apps_smmu 0x0810 0x8>, 4463 <&apps_smmu 0x0c08 0x0>, 4464 <&apps_smmu 0x0c10 0x8>; 4465 4466 status = "disabled"; 4467 4468 ports { 4469 #address-cells = <1>; 4470 #size-cells = <0>; 4471 4472 port@0 { 4473 reg = <0>; 4474 }; 4475 4476 port@1 { 4477 reg = <1>; 4478 }; 4479 4480 port@2 { 4481 reg = <2>; 4482 }; 4483 4484 port@3 { 4485 reg = <3>; 4486 }; 4487 }; 4488 }; 4489 4490 cci: cci@ac4a000 { 4491 compatible = "qcom,sdm845-cci", "qcom,msm8996-cci"; 4492 #address-cells = <1>; 4493 #size-cells = <0>; 4494 4495 reg = <0 0x0ac4a000 0 0x4000>; 4496 interrupts = <GIC_SPI 460 IRQ_TYPE_EDGE_RISING>; 4497 power-domains = <&clock_camcc TITAN_TOP_GDSC>; 4498 4499 clocks = <&clock_camcc CAM_CC_CAMNOC_AXI_CLK>, 4500 <&clock_camcc CAM_CC_SOC_AHB_CLK>, 4501 <&clock_camcc CAM_CC_SLOW_AHB_CLK_SRC>, 4502 <&clock_camcc CAM_CC_CPAS_AHB_CLK>, 4503 <&clock_camcc CAM_CC_CCI_CLK>, 4504 <&clock_camcc CAM_CC_CCI_CLK_SRC>; 4505 clock-names = "camnoc_axi", 4506 "soc_ahb", 4507 "slow_ahb_src", 4508 "cpas_ahb", 4509 "cci", 4510 "cci_src"; 4511 4512 assigned-clocks = <&clock_camcc CAM_CC_CAMNOC_AXI_CLK>, 4513 <&clock_camcc CAM_CC_CCI_CLK>; 4514 assigned-clock-rates = <80000000>, <37500000>; 4515 4516 pinctrl-names = "default", "sleep"; 4517 pinctrl-0 = <&cci0_default &cci1_default>; 4518 pinctrl-1 = <&cci0_sleep &cci1_sleep>; 4519 4520 status = "disabled"; 4521 4522 cci_i2c0: i2c-bus@0 { 4523 reg = <0>; 4524 clock-frequency = <1000000>; 4525 #address-cells = <1>; 4526 #size-cells = <0>; 4527 }; 4528 4529 cci_i2c1: i2c-bus@1 { 4530 reg = <1>; 4531 clock-frequency = <1000000>; 4532 #address-cells = <1>; 4533 #size-cells = <0>; 4534 }; 4535 }; 4536 4537 clock_camcc: clock-controller@ad00000 { 4538 compatible = "qcom,sdm845-camcc"; 4539 reg = <0 0x0ad00000 0 0x10000>; 4540 #clock-cells = <1>; 4541 #reset-cells = <1>; 4542 #power-domain-cells = <1>; 4543 clocks = <&rpmhcc RPMH_CXO_CLK>; 4544 clock-names = "bi_tcxo"; 4545 }; 4546 4547 mdss: display-subsystem@ae00000 { 4548 compatible = "qcom,sdm845-mdss"; 4549 reg = <0 0x0ae00000 0 0x1000>; 4550 reg-names = "mdss"; 4551 4552 power-domains = <&dispcc MDSS_GDSC>; 4553 4554 clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>, 4555 <&dispcc DISP_CC_MDSS_MDP_CLK>; 4556 clock-names = "iface", "core"; 4557 4558 interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>; 4559 interrupt-controller; 4560 #interrupt-cells = <1>; 4561 4562 interconnects = <&mmss_noc MASTER_MDP0 0 &mem_noc SLAVE_EBI1 0>, 4563 <&mmss_noc MASTER_MDP1 0 &mem_noc SLAVE_EBI1 0>; 4564 interconnect-names = "mdp0-mem", "mdp1-mem"; 4565 4566 iommus = <&apps_smmu 0x880 0x8>, 4567 <&apps_smmu 0xc80 0x8>; 4568 4569 status = "disabled"; 4570 4571 #address-cells = <2>; 4572 #size-cells = <2>; 4573 ranges; 4574 4575 mdss_mdp: display-controller@ae01000 { 4576 compatible = "qcom,sdm845-dpu"; 4577 reg = <0 0x0ae01000 0 0x8f000>, 4578 <0 0x0aeb0000 0 0x3000>; 4579 reg-names = "mdp", "vbif"; 4580 4581 clocks = <&gcc GCC_DISP_AXI_CLK>, 4582 <&dispcc DISP_CC_MDSS_AHB_CLK>, 4583 <&dispcc DISP_CC_MDSS_AXI_CLK>, 4584 <&dispcc DISP_CC_MDSS_MDP_CLK>, 4585 <&dispcc DISP_CC_MDSS_VSYNC_CLK>; 4586 clock-names = "gcc-bus", "iface", "bus", "core", "vsync"; 4587 4588 assigned-clocks = <&dispcc DISP_CC_MDSS_VSYNC_CLK>; 4589 assigned-clock-rates = <19200000>; 4590 operating-points-v2 = <&mdp_opp_table>; 4591 power-domains = <&rpmhpd SDM845_CX>; 4592 4593 interrupt-parent = <&mdss>; 4594 interrupts = <0>; 4595 4596 ports { 4597 #address-cells = <1>; 4598 #size-cells = <0>; 4599 4600 port@0 { 4601 reg = <0>; 4602 dpu_intf0_out: endpoint { 4603 remote-endpoint = <&mdss_dp_in>; 4604 }; 4605 }; 4606 4607 port@1 { 4608 reg = <1>; 4609 dpu_intf1_out: endpoint { 4610 remote-endpoint = <&mdss_dsi0_in>; 4611 }; 4612 }; 4613 4614 port@2 { 4615 reg = <2>; 4616 dpu_intf2_out: endpoint { 4617 remote-endpoint = <&mdss_dsi1_in>; 4618 }; 4619 }; 4620 }; 4621 4622 mdp_opp_table: opp-table { 4623 compatible = "operating-points-v2"; 4624 4625 opp-19200000 { 4626 opp-hz = /bits/ 64 <19200000>; 4627 required-opps = <&rpmhpd_opp_min_svs>; 4628 }; 4629 4630 opp-171428571 { 4631 opp-hz = /bits/ 64 <171428571>; 4632 required-opps = <&rpmhpd_opp_low_svs>; 4633 }; 4634 4635 opp-344000000 { 4636 opp-hz = /bits/ 64 <344000000>; 4637 required-opps = <&rpmhpd_opp_svs_l1>; 4638 }; 4639 4640 opp-430000000 { 4641 opp-hz = /bits/ 64 <430000000>; 4642 required-opps = <&rpmhpd_opp_nom>; 4643 }; 4644 }; 4645 }; 4646 4647 mdss_dp: displayport-controller@ae90000 { 4648 status = "disabled"; 4649 compatible = "qcom,sdm845-dp"; 4650 4651 reg = <0 0x0ae90000 0 0x200>, 4652 <0 0x0ae90200 0 0x200>, 4653 <0 0x0ae90400 0 0x600>, 4654 <0 0x0ae90a00 0 0x600>, 4655 <0 0x0ae91000 0 0x600>; 4656 4657 interrupt-parent = <&mdss>; 4658 interrupts = <12>; 4659 4660 clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>, 4661 <&dispcc DISP_CC_MDSS_DP_AUX_CLK>, 4662 <&dispcc DISP_CC_MDSS_DP_LINK_CLK>, 4663 <&dispcc DISP_CC_MDSS_DP_LINK_INTF_CLK>, 4664 <&dispcc DISP_CC_MDSS_DP_PIXEL_CLK>, 4665 <&dispcc DISP_CC_MDSS_DP_PIXEL1_CLK>; 4666 clock-names = "core_iface", 4667 "core_aux", 4668 "ctrl_link", 4669 "ctrl_link_iface", 4670 "stream_pixel", 4671 "stream_1_pixel"; 4672 assigned-clocks = <&dispcc DISP_CC_MDSS_DP_LINK_CLK_SRC>, 4673 <&dispcc DISP_CC_MDSS_DP_PIXEL_CLK_SRC>, 4674 <&dispcc DISP_CC_MDSS_DP_PIXEL1_CLK_SRC>; 4675 assigned-clock-parents = <&usb_1_qmpphy QMP_USB43DP_DP_LINK_CLK>, 4676 <&usb_1_qmpphy QMP_USB43DP_DP_VCO_DIV_CLK>, 4677 <&usb_1_qmpphy QMP_USB43DP_DP_VCO_DIV_CLK>; 4678 phys = <&usb_1_qmpphy QMP_USB43DP_DP_PHY>; 4679 phy-names = "dp"; 4680 4681 operating-points-v2 = <&dp_opp_table>; 4682 power-domains = <&rpmhpd SDM845_CX>; 4683 4684 ports { 4685 #address-cells = <1>; 4686 #size-cells = <0>; 4687 port@0 { 4688 reg = <0>; 4689 mdss_dp_in: endpoint { 4690 remote-endpoint = <&dpu_intf0_out>; 4691 }; 4692 }; 4693 4694 port@1 { 4695 reg = <1>; 4696 mdss_dp_out: endpoint { 4697 remote-endpoint = <&usb_1_qmpphy_dp_in>; 4698 }; 4699 }; 4700 }; 4701 4702 dp_opp_table: opp-table { 4703 compatible = "operating-points-v2"; 4704 4705 opp-162000000 { 4706 opp-hz = /bits/ 64 <162000000>; 4707 required-opps = <&rpmhpd_opp_low_svs>; 4708 }; 4709 4710 opp-270000000 { 4711 opp-hz = /bits/ 64 <270000000>; 4712 required-opps = <&rpmhpd_opp_svs>; 4713 }; 4714 4715 opp-540000000 { 4716 opp-hz = /bits/ 64 <540000000>; 4717 required-opps = <&rpmhpd_opp_svs_l1>; 4718 }; 4719 4720 opp-810000000 { 4721 opp-hz = /bits/ 64 <810000000>; 4722 required-opps = <&rpmhpd_opp_nom>; 4723 }; 4724 }; 4725 }; 4726 4727 mdss_dsi0: dsi@ae94000 { 4728 compatible = "qcom,sdm845-dsi-ctrl", 4729 "qcom,mdss-dsi-ctrl"; 4730 reg = <0 0x0ae94000 0 0x400>; 4731 reg-names = "dsi_ctrl"; 4732 4733 interrupt-parent = <&mdss>; 4734 interrupts = <4>; 4735 4736 clocks = <&dispcc DISP_CC_MDSS_BYTE0_CLK>, 4737 <&dispcc DISP_CC_MDSS_BYTE0_INTF_CLK>, 4738 <&dispcc DISP_CC_MDSS_PCLK0_CLK>, 4739 <&dispcc DISP_CC_MDSS_ESC0_CLK>, 4740 <&dispcc DISP_CC_MDSS_AHB_CLK>, 4741 <&dispcc DISP_CC_MDSS_AXI_CLK>; 4742 clock-names = "byte", 4743 "byte_intf", 4744 "pixel", 4745 "core", 4746 "iface", 4747 "bus"; 4748 assigned-clocks = <&dispcc DISP_CC_MDSS_BYTE0_CLK_SRC>, 4749 <&dispcc DISP_CC_MDSS_PCLK0_CLK_SRC>; 4750 assigned-clock-parents = <&mdss_dsi0_phy DSI_BYTE_PLL_CLK>, 4751 <&mdss_dsi0_phy DSI_PIXEL_PLL_CLK>; 4752 4753 operating-points-v2 = <&dsi_opp_table>; 4754 power-domains = <&rpmhpd SDM845_CX>; 4755 4756 phys = <&mdss_dsi0_phy>; 4757 4758 refgen-supply = <&refgen>; 4759 4760 status = "disabled"; 4761 4762 #address-cells = <1>; 4763 #size-cells = <0>; 4764 4765 ports { 4766 #address-cells = <1>; 4767 #size-cells = <0>; 4768 4769 port@0 { 4770 reg = <0>; 4771 mdss_dsi0_in: endpoint { 4772 remote-endpoint = <&dpu_intf1_out>; 4773 }; 4774 }; 4775 4776 port@1 { 4777 reg = <1>; 4778 mdss_dsi0_out: endpoint { 4779 }; 4780 }; 4781 }; 4782 }; 4783 4784 mdss_dsi0_phy: phy@ae94400 { 4785 compatible = "qcom,dsi-phy-10nm"; 4786 reg = <0 0x0ae94400 0 0x200>, 4787 <0 0x0ae94600 0 0x280>, 4788 <0 0x0ae94a00 0 0x1e0>; 4789 reg-names = "dsi_phy", 4790 "dsi_phy_lane", 4791 "dsi_pll"; 4792 4793 #clock-cells = <1>; 4794 #phy-cells = <0>; 4795 4796 clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>, 4797 <&rpmhcc RPMH_CXO_CLK>; 4798 clock-names = "iface", "ref"; 4799 4800 status = "disabled"; 4801 }; 4802 4803 mdss_dsi1: dsi@ae96000 { 4804 compatible = "qcom,sdm845-dsi-ctrl", 4805 "qcom,mdss-dsi-ctrl"; 4806 reg = <0 0x0ae96000 0 0x400>; 4807 reg-names = "dsi_ctrl"; 4808 4809 interrupt-parent = <&mdss>; 4810 interrupts = <5>; 4811 4812 clocks = <&dispcc DISP_CC_MDSS_BYTE1_CLK>, 4813 <&dispcc DISP_CC_MDSS_BYTE1_INTF_CLK>, 4814 <&dispcc DISP_CC_MDSS_PCLK1_CLK>, 4815 <&dispcc DISP_CC_MDSS_ESC1_CLK>, 4816 <&dispcc DISP_CC_MDSS_AHB_CLK>, 4817 <&dispcc DISP_CC_MDSS_AXI_CLK>; 4818 clock-names = "byte", 4819 "byte_intf", 4820 "pixel", 4821 "core", 4822 "iface", 4823 "bus"; 4824 assigned-clocks = <&dispcc DISP_CC_MDSS_BYTE1_CLK_SRC>, 4825 <&dispcc DISP_CC_MDSS_PCLK1_CLK_SRC>; 4826 assigned-clock-parents = <&mdss_dsi1_phy DSI_BYTE_PLL_CLK>, 4827 <&mdss_dsi1_phy DSI_PIXEL_PLL_CLK>; 4828 4829 operating-points-v2 = <&dsi_opp_table>; 4830 power-domains = <&rpmhpd SDM845_CX>; 4831 4832 phys = <&mdss_dsi1_phy>; 4833 4834 refgen-supply = <&refgen>; 4835 4836 status = "disabled"; 4837 4838 #address-cells = <1>; 4839 #size-cells = <0>; 4840 4841 ports { 4842 #address-cells = <1>; 4843 #size-cells = <0>; 4844 4845 port@0 { 4846 reg = <0>; 4847 mdss_dsi1_in: endpoint { 4848 remote-endpoint = <&dpu_intf2_out>; 4849 }; 4850 }; 4851 4852 port@1 { 4853 reg = <1>; 4854 mdss_dsi1_out: endpoint { 4855 }; 4856 }; 4857 }; 4858 }; 4859 4860 mdss_dsi1_phy: phy@ae96400 { 4861 compatible = "qcom,dsi-phy-10nm"; 4862 reg = <0 0x0ae96400 0 0x200>, 4863 <0 0x0ae96600 0 0x280>, 4864 <0 0x0ae96a00 0 0x10e>; 4865 reg-names = "dsi_phy", 4866 "dsi_phy_lane", 4867 "dsi_pll"; 4868 4869 #clock-cells = <1>; 4870 #phy-cells = <0>; 4871 4872 clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>, 4873 <&rpmhcc RPMH_CXO_CLK>; 4874 clock-names = "iface", "ref"; 4875 4876 status = "disabled"; 4877 }; 4878 }; 4879 4880 gpu: gpu@5000000 { 4881 compatible = "qcom,adreno-630.2", "qcom,adreno"; 4882 4883 reg = <0 0x05000000 0 0x40000>, <0 0x509e000 0 0x10>; 4884 reg-names = "kgsl_3d0_reg_memory", "cx_mem"; 4885 4886 /* 4887 * Look ma, no clocks! The GPU clocks and power are 4888 * controlled entirely by the GMU 4889 */ 4890 4891 interrupts = <GIC_SPI 300 IRQ_TYPE_LEVEL_HIGH>; 4892 4893 iommus = <&adreno_smmu 0>; 4894 4895 operating-points-v2 = <&gpu_opp_table>; 4896 4897 qcom,gmu = <&gmu>; 4898 #cooling-cells = <2>; 4899 4900 interconnects = <&mem_noc MASTER_GFX3D 0 &mem_noc SLAVE_EBI1 0>; 4901 interconnect-names = "gfx-mem"; 4902 4903 status = "disabled"; 4904 4905 gpu_zap_shader: zap-shader { 4906 memory-region = <&gpu_mem>; 4907 }; 4908 4909 gpu_opp_table: opp-table { 4910 compatible = "operating-points-v2"; 4911 4912 opp-710000000 { 4913 opp-hz = /bits/ 64 <710000000>; 4914 opp-level = <RPMH_REGULATOR_LEVEL_TURBO_L1>; 4915 opp-peak-kBps = <7216000>; 4916 }; 4917 4918 opp-675000000 { 4919 opp-hz = /bits/ 64 <675000000>; 4920 opp-level = <RPMH_REGULATOR_LEVEL_TURBO>; 4921 opp-peak-kBps = <7216000>; 4922 }; 4923 4924 opp-596000000 { 4925 opp-hz = /bits/ 64 <596000000>; 4926 opp-level = <RPMH_REGULATOR_LEVEL_NOM_L1>; 4927 opp-peak-kBps = <6220000>; 4928 }; 4929 4930 opp-520000000 { 4931 opp-hz = /bits/ 64 <520000000>; 4932 opp-level = <RPMH_REGULATOR_LEVEL_NOM>; 4933 opp-peak-kBps = <6220000>; 4934 }; 4935 4936 opp-414000000 { 4937 opp-hz = /bits/ 64 <414000000>; 4938 opp-level = <RPMH_REGULATOR_LEVEL_SVS_L1>; 4939 opp-peak-kBps = <4068000>; 4940 }; 4941 4942 opp-342000000 { 4943 opp-hz = /bits/ 64 <342000000>; 4944 opp-level = <RPMH_REGULATOR_LEVEL_SVS>; 4945 opp-peak-kBps = <2724000>; 4946 }; 4947 4948 opp-257000000 { 4949 opp-hz = /bits/ 64 <257000000>; 4950 opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS>; 4951 opp-peak-kBps = <1648000>; 4952 }; 4953 }; 4954 }; 4955 4956 adreno_smmu: iommu@5040000 { 4957 compatible = "qcom,sdm845-smmu-v2", "qcom,adreno-smmu", "qcom,smmu-v2"; 4958 reg = <0 0x05040000 0 0x10000>; 4959 #iommu-cells = <1>; 4960 #global-interrupts = <2>; 4961 interrupts = <GIC_SPI 229 IRQ_TYPE_LEVEL_HIGH>, 4962 <GIC_SPI 231 IRQ_TYPE_LEVEL_HIGH>, 4963 <GIC_SPI 364 IRQ_TYPE_EDGE_RISING>, 4964 <GIC_SPI 365 IRQ_TYPE_EDGE_RISING>, 4965 <GIC_SPI 366 IRQ_TYPE_EDGE_RISING>, 4966 <GIC_SPI 367 IRQ_TYPE_EDGE_RISING>, 4967 <GIC_SPI 368 IRQ_TYPE_EDGE_RISING>, 4968 <GIC_SPI 369 IRQ_TYPE_EDGE_RISING>, 4969 <GIC_SPI 370 IRQ_TYPE_EDGE_RISING>, 4970 <GIC_SPI 371 IRQ_TYPE_EDGE_RISING>; 4971 clocks = <&gcc GCC_GPU_MEMNOC_GFX_CLK>, 4972 <&gcc GCC_GPU_CFG_AHB_CLK>; 4973 clock-names = "bus", "iface"; 4974 4975 power-domains = <&gpucc GPU_CX_GDSC>; 4976 }; 4977 4978 gmu: gmu@506a000 { 4979 compatible = "qcom,adreno-gmu-630.2", "qcom,adreno-gmu"; 4980 4981 reg = <0 0x0506a000 0 0x30000>, 4982 <0 0x0b280000 0 0x10000>, 4983 <0 0x0b480000 0 0x10000>; 4984 reg-names = "gmu", "gmu_pdc", "gmu_pdc_seq"; 4985 4986 interrupts = <GIC_SPI 304 IRQ_TYPE_LEVEL_HIGH>, 4987 <GIC_SPI 305 IRQ_TYPE_LEVEL_HIGH>; 4988 interrupt-names = "hfi", "gmu"; 4989 4990 clocks = <&gpucc GPU_CC_CX_GMU_CLK>, 4991 <&gpucc GPU_CC_CXO_CLK>, 4992 <&gcc GCC_DDRSS_GPU_AXI_CLK>, 4993 <&gcc GCC_GPU_MEMNOC_GFX_CLK>; 4994 clock-names = "gmu", "cxo", "axi", "memnoc"; 4995 4996 power-domains = <&gpucc GPU_CX_GDSC>, 4997 <&gpucc GPU_GX_GDSC>; 4998 power-domain-names = "cx", "gx"; 4999 5000 iommus = <&adreno_smmu 5>; 5001 5002 operating-points-v2 = <&gmu_opp_table>; 5003 5004 gmu_opp_table: opp-table { 5005 compatible = "operating-points-v2"; 5006 5007 opp-400000000 { 5008 opp-hz = /bits/ 64 <400000000>; 5009 opp-level = <RPMH_REGULATOR_LEVEL_SVS>; 5010 }; 5011 5012 opp-200000000 { 5013 opp-hz = /bits/ 64 <200000000>; 5014 opp-level = <RPMH_REGULATOR_LEVEL_MIN_SVS>; 5015 }; 5016 }; 5017 }; 5018 5019 dispcc: clock-controller@af00000 { 5020 compatible = "qcom,sdm845-dispcc"; 5021 reg = <0 0x0af00000 0 0x10000>; 5022 clocks = <&rpmhcc RPMH_CXO_CLK>, 5023 <&gcc GCC_DISP_GPLL0_CLK_SRC>, 5024 <&gcc GCC_DISP_GPLL0_DIV_CLK_SRC>, 5025 <&mdss_dsi0_phy DSI_BYTE_PLL_CLK>, 5026 <&mdss_dsi0_phy DSI_PIXEL_PLL_CLK>, 5027 <&mdss_dsi1_phy DSI_BYTE_PLL_CLK>, 5028 <&mdss_dsi1_phy DSI_PIXEL_PLL_CLK>, 5029 <&usb_1_qmpphy QMP_USB43DP_DP_LINK_CLK>, 5030 <&usb_1_qmpphy QMP_USB43DP_DP_VCO_DIV_CLK>; 5031 clock-names = "bi_tcxo", 5032 "gcc_disp_gpll0_clk_src", 5033 "gcc_disp_gpll0_div_clk_src", 5034 "dsi0_phy_pll_out_byteclk", 5035 "dsi0_phy_pll_out_dsiclk", 5036 "dsi1_phy_pll_out_byteclk", 5037 "dsi1_phy_pll_out_dsiclk", 5038 "dp_link_clk_divsel_ten", 5039 "dp_vco_divided_clk_src_mux"; 5040 #clock-cells = <1>; 5041 #reset-cells = <1>; 5042 #power-domain-cells = <1>; 5043 }; 5044 5045 pdc_intc: interrupt-controller@b220000 { 5046 compatible = "qcom,sdm845-pdc", "qcom,pdc"; 5047 reg = <0 0x0b220000 0 0x30000>; 5048 qcom,pdc-ranges = <0 480 94>, <94 609 15>, <115 630 7>; 5049 #interrupt-cells = <2>; 5050 interrupt-parent = <&intc>; 5051 interrupt-controller; 5052 }; 5053 5054 pdc_reset: reset-controller@b2e0000 { 5055 compatible = "qcom,sdm845-pdc-global"; 5056 reg = <0 0x0b2e0000 0 0x20000>; 5057 #reset-cells = <1>; 5058 }; 5059 5060 tsens0: thermal-sensor@c263000 { 5061 compatible = "qcom,sdm845-tsens", "qcom,tsens-v2"; 5062 reg = <0 0x0c263000 0 0x1ff>, /* TM */ 5063 <0 0x0c222000 0 0x1ff>; /* SROT */ 5064 #qcom,sensors = <13>; 5065 interrupts = <GIC_SPI 506 IRQ_TYPE_LEVEL_HIGH>, 5066 <GIC_SPI 508 IRQ_TYPE_LEVEL_HIGH>; 5067 interrupt-names = "uplow", "critical"; 5068 #thermal-sensor-cells = <1>; 5069 }; 5070 5071 tsens1: thermal-sensor@c265000 { 5072 compatible = "qcom,sdm845-tsens", "qcom,tsens-v2"; 5073 reg = <0 0x0c265000 0 0x1ff>, /* TM */ 5074 <0 0x0c223000 0 0x1ff>; /* SROT */ 5075 #qcom,sensors = <8>; 5076 interrupts = <GIC_SPI 507 IRQ_TYPE_LEVEL_HIGH>, 5077 <GIC_SPI 509 IRQ_TYPE_LEVEL_HIGH>; 5078 interrupt-names = "uplow", "critical"; 5079 #thermal-sensor-cells = <1>; 5080 }; 5081 5082 aoss_reset: reset-controller@c2a0000 { 5083 compatible = "qcom,sdm845-aoss-cc"; 5084 reg = <0 0x0c2a0000 0 0x31000>; 5085 #reset-cells = <1>; 5086 }; 5087 5088 aoss_qmp: power-management@c300000 { 5089 compatible = "qcom,sdm845-aoss-qmp", "qcom,aoss-qmp"; 5090 reg = <0 0x0c300000 0 0x400>; 5091 interrupts = <GIC_SPI 389 IRQ_TYPE_EDGE_RISING>; 5092 mboxes = <&apss_shared 0>; 5093 5094 #clock-cells = <0>; 5095 5096 cx_cdev: cx { 5097 #cooling-cells = <2>; 5098 }; 5099 5100 ebi_cdev: ebi { 5101 #cooling-cells = <2>; 5102 }; 5103 }; 5104 5105 sram@c3f0000 { 5106 compatible = "qcom,sdm845-rpmh-stats"; 5107 reg = <0 0x0c3f0000 0 0x400>; 5108 }; 5109 5110 spmi_bus: spmi@c440000 { 5111 compatible = "qcom,spmi-pmic-arb"; 5112 reg = <0 0x0c440000 0 0x1100>, 5113 <0 0x0c600000 0 0x2000000>, 5114 <0 0x0e600000 0 0x100000>, 5115 <0 0x0e700000 0 0xa0000>, 5116 <0 0x0c40a000 0 0x26000>; 5117 reg-names = "core", "chnls", "obsrvr", "intr", "cnfg"; 5118 interrupt-names = "periph_irq"; 5119 interrupts = <GIC_SPI 481 IRQ_TYPE_LEVEL_HIGH>; 5120 qcom,ee = <0>; 5121 qcom,channel = <0>; 5122 #address-cells = <2>; 5123 #size-cells = <0>; 5124 interrupt-controller; 5125 #interrupt-cells = <4>; 5126 }; 5127 5128 sram@14680000 { 5129 compatible = "qcom,sdm845-imem", "syscon", "simple-mfd"; 5130 reg = <0 0x14680000 0 0x40000>; 5131 5132 #address-cells = <1>; 5133 #size-cells = <1>; 5134 5135 ranges = <0 0 0x14680000 0x40000>; 5136 5137 pil-reloc@3f94c { 5138 compatible = "qcom,pil-reloc-info"; 5139 reg = <0x3f94c 0xc8>; 5140 }; 5141 }; 5142 5143 apps_smmu: iommu@15000000 { 5144 compatible = "qcom,sdm845-smmu-500", "arm,mmu-500"; 5145 reg = <0 0x15000000 0 0x80000>; 5146 #iommu-cells = <2>; 5147 #global-interrupts = <1>; 5148 interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>, 5149 <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>, 5150 <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>, 5151 <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>, 5152 <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>, 5153 <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>, 5154 <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>, 5155 <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>, 5156 <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>, 5157 <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>, 5158 <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>, 5159 <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>, 5160 <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>, 5161 <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>, 5162 <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>, 5163 <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>, 5164 <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>, 5165 <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>, 5166 <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>, 5167 <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>, 5168 <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>, 5169 <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>, 5170 <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>, 5171 <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>, 5172 <GIC_SPI 181 IRQ_TYPE_LEVEL_HIGH>, 5173 <GIC_SPI 182 IRQ_TYPE_LEVEL_HIGH>, 5174 <GIC_SPI 183 IRQ_TYPE_LEVEL_HIGH>, 5175 <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>, 5176 <GIC_SPI 185 IRQ_TYPE_LEVEL_HIGH>, 5177 <GIC_SPI 186 IRQ_TYPE_LEVEL_HIGH>, 5178 <GIC_SPI 187 IRQ_TYPE_LEVEL_HIGH>, 5179 <GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>, 5180 <GIC_SPI 189 IRQ_TYPE_LEVEL_HIGH>, 5181 <GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>, 5182 <GIC_SPI 191 IRQ_TYPE_LEVEL_HIGH>, 5183 <GIC_SPI 192 IRQ_TYPE_LEVEL_HIGH>, 5184 <GIC_SPI 315 IRQ_TYPE_LEVEL_HIGH>, 5185 <GIC_SPI 316 IRQ_TYPE_LEVEL_HIGH>, 5186 <GIC_SPI 317 IRQ_TYPE_LEVEL_HIGH>, 5187 <GIC_SPI 318 IRQ_TYPE_LEVEL_HIGH>, 5188 <GIC_SPI 319 IRQ_TYPE_LEVEL_HIGH>, 5189 <GIC_SPI 320 IRQ_TYPE_LEVEL_HIGH>, 5190 <GIC_SPI 321 IRQ_TYPE_LEVEL_HIGH>, 5191 <GIC_SPI 322 IRQ_TYPE_LEVEL_HIGH>, 5192 <GIC_SPI 323 IRQ_TYPE_LEVEL_HIGH>, 5193 <GIC_SPI 324 IRQ_TYPE_LEVEL_HIGH>, 5194 <GIC_SPI 325 IRQ_TYPE_LEVEL_HIGH>, 5195 <GIC_SPI 326 IRQ_TYPE_LEVEL_HIGH>, 5196 <GIC_SPI 327 IRQ_TYPE_LEVEL_HIGH>, 5197 <GIC_SPI 328 IRQ_TYPE_LEVEL_HIGH>, 5198 <GIC_SPI 329 IRQ_TYPE_LEVEL_HIGH>, 5199 <GIC_SPI 330 IRQ_TYPE_LEVEL_HIGH>, 5200 <GIC_SPI 331 IRQ_TYPE_LEVEL_HIGH>, 5201 <GIC_SPI 332 IRQ_TYPE_LEVEL_HIGH>, 5202 <GIC_SPI 333 IRQ_TYPE_LEVEL_HIGH>, 5203 <GIC_SPI 334 IRQ_TYPE_LEVEL_HIGH>, 5204 <GIC_SPI 335 IRQ_TYPE_LEVEL_HIGH>, 5205 <GIC_SPI 336 IRQ_TYPE_LEVEL_HIGH>, 5206 <GIC_SPI 337 IRQ_TYPE_LEVEL_HIGH>, 5207 <GIC_SPI 338 IRQ_TYPE_LEVEL_HIGH>, 5208 <GIC_SPI 339 IRQ_TYPE_LEVEL_HIGH>, 5209 <GIC_SPI 340 IRQ_TYPE_LEVEL_HIGH>, 5210 <GIC_SPI 341 IRQ_TYPE_LEVEL_HIGH>, 5211 <GIC_SPI 342 IRQ_TYPE_LEVEL_HIGH>, 5212 <GIC_SPI 343 IRQ_TYPE_LEVEL_HIGH>; 5213 }; 5214 5215 anoc_1_tbu: tbu@150c5000 { 5216 compatible = "qcom,sdm845-tbu"; 5217 reg = <0x0 0x150c5000 0x0 0x1000>; 5218 interconnects = <&system_noc MASTER_GNOC_SNOC QCOM_ICC_TAG_ACTIVE_ONLY 5219 &config_noc SLAVE_IMEM_CFG QCOM_ICC_TAG_ACTIVE_ONLY>; 5220 power-domains = <&gcc HLOS1_VOTE_AGGRE_NOC_MMU_TBU1_GDSC>; 5221 qcom,stream-id-range = <&apps_smmu 0x0 0x400>; 5222 }; 5223 5224 anoc_2_tbu: tbu@150c9000 { 5225 compatible = "qcom,sdm845-tbu"; 5226 reg = <0x0 0x150c9000 0x0 0x1000>; 5227 interconnects = <&system_noc MASTER_GNOC_SNOC QCOM_ICC_TAG_ACTIVE_ONLY 5228 &config_noc SLAVE_IMEM_CFG QCOM_ICC_TAG_ACTIVE_ONLY>; 5229 power-domains = <&gcc HLOS1_VOTE_AGGRE_NOC_MMU_TBU2_GDSC>; 5230 qcom,stream-id-range = <&apps_smmu 0x400 0x400>; 5231 }; 5232 5233 mnoc_hf_0_tbu: tbu@150cd000 { 5234 compatible = "qcom,sdm845-tbu"; 5235 reg = <0x0 0x150cd000 0x0 0x1000>; 5236 interconnects = <&mmss_noc MASTER_MDP0 QCOM_ICC_TAG_ACTIVE_ONLY 5237 &mmss_noc SLAVE_MNOC_HF_MEM_NOC QCOM_ICC_TAG_ACTIVE_ONLY>; 5238 power-domains = <&gcc HLOS1_VOTE_MMNOC_MMU_TBU_HF0_GDSC>; 5239 qcom,stream-id-range = <&apps_smmu 0x800 0x400>; 5240 }; 5241 5242 mnoc_hf_1_tbu: tbu@150d1000 { 5243 compatible = "qcom,sdm845-tbu"; 5244 reg = <0x0 0x150d1000 0x0 0x1000>; 5245 interconnects = <&mmss_noc MASTER_MDP0 QCOM_ICC_TAG_ACTIVE_ONLY 5246 &mmss_noc SLAVE_MNOC_HF_MEM_NOC QCOM_ICC_TAG_ACTIVE_ONLY>; 5247 power-domains = <&gcc HLOS1_VOTE_MMNOC_MMU_TBU_HF1_GDSC>; 5248 qcom,stream-id-range = <&apps_smmu 0xc00 0x400>; 5249 }; 5250 5251 mnoc_sf_0_tbu: tbu@150d5000 { 5252 compatible = "qcom,sdm845-tbu"; 5253 reg = <0x0 0x150d5000 0x0 0x1000>; 5254 interconnects = <&mmss_noc MASTER_CAMNOC_SF QCOM_ICC_TAG_ACTIVE_ONLY 5255 &mmss_noc SLAVE_MNOC_SF_MEM_NOC QCOM_ICC_TAG_ACTIVE_ONLY>; 5256 power-domains = <&gcc HLOS1_VOTE_MMNOC_MMU_TBU_SF_GDSC>; 5257 qcom,stream-id-range = <&apps_smmu 0x1000 0x400>; 5258 }; 5259 5260 compute_dsp_tbu: tbu@150d9000 { 5261 compatible = "qcom,sdm845-tbu"; 5262 reg = <0x0 0x150d9000 0x0 0x1000>; 5263 interconnects = <&system_noc MASTER_GNOC_SNOC QCOM_ICC_TAG_ACTIVE_ONLY 5264 &config_noc SLAVE_IMEM_CFG QCOM_ICC_TAG_ACTIVE_ONLY>; 5265 qcom,stream-id-range = <&apps_smmu 0x1400 0x400>; 5266 }; 5267 5268 adsp_tbu: tbu@150dd000 { 5269 compatible = "qcom,sdm845-tbu"; 5270 reg = <0x0 0x150dd000 0x0 0x1000>; 5271 interconnects = <&system_noc MASTER_GNOC_SNOC QCOM_ICC_TAG_ACTIVE_ONLY 5272 &config_noc SLAVE_IMEM_CFG QCOM_ICC_TAG_ACTIVE_ONLY>; 5273 power-domains = <&gcc HLOS1_VOTE_AGGRE_NOC_MMU_AUDIO_TBU_GDSC>; 5274 qcom,stream-id-range = <&apps_smmu 0x1800 0x400>; 5275 }; 5276 5277 anoc_1_pcie_tbu: tbu@150e1000 { 5278 compatible = "qcom,sdm845-tbu"; 5279 reg = <0x0 0x150e1000 0x0 0x1000>; 5280 clocks = <&gcc GCC_AGGRE_NOC_PCIE_TBU_CLK>; 5281 interconnects = <&system_noc MASTER_GNOC_SNOC QCOM_ICC_TAG_ACTIVE_ONLY 5282 &config_noc SLAVE_IMEM_CFG QCOM_ICC_TAG_ACTIVE_ONLY>; 5283 power-domains = <&gcc HLOS1_VOTE_AGGRE_NOC_MMU_PCIE_TBU_GDSC>; 5284 qcom,stream-id-range = <&apps_smmu 0x1c00 0x400>; 5285 }; 5286 5287 lpasscc: clock-controller@17014000 { 5288 compatible = "qcom,sdm845-lpasscc"; 5289 reg = <0 0x17014000 0 0x1f004>, <0 0x17300000 0 0x200>; 5290 reg-names = "cc", "qdsp6ss"; 5291 #clock-cells = <1>; 5292 status = "disabled"; 5293 }; 5294 5295 gladiator_noc: interconnect@17900000 { 5296 compatible = "qcom,sdm845-gladiator-noc"; 5297 reg = <0 0x17900000 0 0xd080>; 5298 #interconnect-cells = <2>; 5299 qcom,bcm-voters = <&apps_bcm_voter>; 5300 }; 5301 5302 watchdog@17980000 { 5303 compatible = "qcom,apss-wdt-sdm845", "qcom,kpss-wdt"; 5304 reg = <0 0x17980000 0 0x1000>; 5305 clocks = <&sleep_clk>; 5306 interrupts = <GIC_SPI 0 IRQ_TYPE_EDGE_RISING>; 5307 }; 5308 5309 apss_shared: mailbox@17990000 { 5310 compatible = "qcom,sdm845-apss-shared"; 5311 reg = <0 0x17990000 0 0x1000>; 5312 #mbox-cells = <1>; 5313 }; 5314 5315 apps_rsc: rsc@179c0000 { 5316 compatible = "qcom,sdm845-rpmh-apps-rsc", "qcom,rpmh-rsc"; 5317 label = "apps_rsc"; 5318 reg = <0 0x179c0000 0 0x10000>, 5319 <0 0x179d0000 0 0x10000>, 5320 <0 0x179e0000 0 0x10000>; 5321 reg-names = "drv-0", "drv-1", "drv-2"; 5322 interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>, 5323 <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>, 5324 <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>; 5325 qcom,tcs-offset = <0xd00>; 5326 qcom,drv-id = <2>; 5327 qcom,tcs-config = <ACTIVE_TCS 2>, 5328 <SLEEP_TCS 3>, 5329 <WAKE_TCS 3>, 5330 <CONTROL_TCS 1>; 5331 power-domains = <&cluster_pd>; 5332 5333 apps_bcm_voter: bcm-voter { 5334 compatible = "qcom,bcm-voter"; 5335 }; 5336 5337 rpmhcc: clock-controller { 5338 compatible = "qcom,sdm845-rpmh-clk"; 5339 #clock-cells = <1>; 5340 clock-names = "xo"; 5341 clocks = <&xo_board>; 5342 }; 5343 5344 rpmhpd: power-controller { 5345 compatible = "qcom,sdm845-rpmhpd"; 5346 #power-domain-cells = <1>; 5347 operating-points-v2 = <&rpmhpd_opp_table>; 5348 5349 rpmhpd_opp_table: opp-table { 5350 compatible = "operating-points-v2"; 5351 5352 rpmhpd_opp_ret: opp1 { 5353 opp-level = <RPMH_REGULATOR_LEVEL_RETENTION>; 5354 }; 5355 5356 rpmhpd_opp_min_svs: opp2 { 5357 opp-level = <RPMH_REGULATOR_LEVEL_MIN_SVS>; 5358 }; 5359 5360 rpmhpd_opp_low_svs: opp3 { 5361 opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS>; 5362 }; 5363 5364 rpmhpd_opp_svs: opp4 { 5365 opp-level = <RPMH_REGULATOR_LEVEL_SVS>; 5366 }; 5367 5368 rpmhpd_opp_svs_l1: opp5 { 5369 opp-level = <RPMH_REGULATOR_LEVEL_SVS_L1>; 5370 }; 5371 5372 rpmhpd_opp_nom: opp6 { 5373 opp-level = <RPMH_REGULATOR_LEVEL_NOM>; 5374 }; 5375 5376 rpmhpd_opp_nom_l1: opp7 { 5377 opp-level = <RPMH_REGULATOR_LEVEL_NOM_L1>; 5378 }; 5379 5380 rpmhpd_opp_nom_l2: opp8 { 5381 opp-level = <RPMH_REGULATOR_LEVEL_NOM_L2>; 5382 }; 5383 5384 rpmhpd_opp_turbo: opp9 { 5385 opp-level = <RPMH_REGULATOR_LEVEL_TURBO>; 5386 }; 5387 5388 rpmhpd_opp_turbo_l1: opp10 { 5389 opp-level = <RPMH_REGULATOR_LEVEL_TURBO_L1>; 5390 }; 5391 }; 5392 }; 5393 }; 5394 5395 intc: interrupt-controller@17a00000 { 5396 compatible = "arm,gic-v3"; 5397 #address-cells = <2>; 5398 #size-cells = <2>; 5399 ranges; 5400 #interrupt-cells = <3>; 5401 interrupt-controller; 5402 reg = <0 0x17a00000 0 0x10000>, /* GICD */ 5403 <0 0x17a60000 0 0x100000>; /* GICR * 8 */ 5404 interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>; 5405 5406 msi-controller@17a40000 { 5407 compatible = "arm,gic-v3-its"; 5408 msi-controller; 5409 #msi-cells = <1>; 5410 reg = <0 0x17a40000 0 0x20000>; 5411 status = "disabled"; 5412 }; 5413 }; 5414 5415 slimbam: dma-controller@17184000 { 5416 compatible = "qcom,bam-v1.7.4", "qcom,bam-v1.7.0"; 5417 qcom,controlled-remotely; 5418 reg = <0 0x17184000 0 0x2a000>; 5419 num-channels = <23>; 5420 interrupts = <GIC_SPI 164 IRQ_TYPE_LEVEL_HIGH>; 5421 #dma-cells = <1>; 5422 qcom,ee = <1>; 5423 qcom,num-ees = <4>; 5424 iommus = <&apps_smmu 0x1806 0x0>; 5425 }; 5426 5427 timer@17c90000 { 5428 #address-cells = <1>; 5429 #size-cells = <1>; 5430 ranges = <0 0 0 0x20000000>; 5431 compatible = "arm,armv7-timer-mem"; 5432 reg = <0 0x17c90000 0 0x1000>; 5433 5434 frame@17ca0000 { 5435 frame-number = <0>; 5436 interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>, 5437 <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>; 5438 reg = <0x17ca0000 0x1000>, 5439 <0x17cb0000 0x1000>; 5440 }; 5441 5442 frame@17cc0000 { 5443 frame-number = <1>; 5444 interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>; 5445 reg = <0x17cc0000 0x1000>; 5446 status = "disabled"; 5447 }; 5448 5449 frame@17cd0000 { 5450 frame-number = <2>; 5451 interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>; 5452 reg = <0x17cd0000 0x1000>; 5453 status = "disabled"; 5454 }; 5455 5456 frame@17ce0000 { 5457 frame-number = <3>; 5458 interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>; 5459 reg = <0x17ce0000 0x1000>; 5460 status = "disabled"; 5461 }; 5462 5463 frame@17cf0000 { 5464 frame-number = <4>; 5465 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>; 5466 reg = <0x17cf0000 0x1000>; 5467 status = "disabled"; 5468 }; 5469 5470 frame@17d00000 { 5471 frame-number = <5>; 5472 interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>; 5473 reg = <0x17d00000 0x1000>; 5474 status = "disabled"; 5475 }; 5476 5477 frame@17d10000 { 5478 frame-number = <6>; 5479 interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>; 5480 reg = <0x17d10000 0x1000>; 5481 status = "disabled"; 5482 }; 5483 }; 5484 5485 osm_l3: interconnect@17d41000 { 5486 compatible = "qcom,sdm845-osm-l3", "qcom,osm-l3"; 5487 reg = <0 0x17d41000 0 0x1400>; 5488 5489 clocks = <&rpmhcc RPMH_CXO_CLK>, <&gcc GPLL0>; 5490 clock-names = "xo", "alternate"; 5491 5492 #interconnect-cells = <1>; 5493 }; 5494 5495 cpufreq_hw: cpufreq@17d43000 { 5496 compatible = "qcom,sdm845-cpufreq-hw", "qcom,cpufreq-hw"; 5497 reg = <0 0x17d43000 0 0x1400>, <0 0x17d45800 0 0x1400>; 5498 reg-names = "freq-domain0", "freq-domain1"; 5499 5500 interrupts-extended = <&lmh_cluster0 0>, <&lmh_cluster1 0>; 5501 5502 clocks = <&rpmhcc RPMH_CXO_CLK>, <&gcc GPLL0>; 5503 clock-names = "xo", "alternate"; 5504 5505 #freq-domain-cells = <1>; 5506 #clock-cells = <1>; 5507 }; 5508 5509 wifi: wifi@18800000 { 5510 compatible = "qcom,wcn3990-wifi"; 5511 status = "disabled"; 5512 reg = <0 0x18800000 0 0x800000>; 5513 reg-names = "membase"; 5514 memory-region = <&wlan_msa_mem>; 5515 clock-names = "cxo_ref_clk_pin"; 5516 clocks = <&rpmhcc RPMH_RF_CLK2>; 5517 interrupts = 5518 <GIC_SPI 414 IRQ_TYPE_LEVEL_HIGH>, 5519 <GIC_SPI 415 IRQ_TYPE_LEVEL_HIGH>, 5520 <GIC_SPI 416 IRQ_TYPE_LEVEL_HIGH>, 5521 <GIC_SPI 417 IRQ_TYPE_LEVEL_HIGH>, 5522 <GIC_SPI 418 IRQ_TYPE_LEVEL_HIGH>, 5523 <GIC_SPI 419 IRQ_TYPE_LEVEL_HIGH>, 5524 <GIC_SPI 420 IRQ_TYPE_LEVEL_HIGH>, 5525 <GIC_SPI 421 IRQ_TYPE_LEVEL_HIGH>, 5526 <GIC_SPI 422 IRQ_TYPE_LEVEL_HIGH>, 5527 <GIC_SPI 423 IRQ_TYPE_LEVEL_HIGH>, 5528 <GIC_SPI 424 IRQ_TYPE_LEVEL_HIGH>, 5529 <GIC_SPI 425 IRQ_TYPE_LEVEL_HIGH>; 5530 iommus = <&apps_smmu 0x0040 0x1>; 5531 }; 5532 }; 5533 5534 sound: sound { 5535 }; 5536 5537 thermal-zones { 5538 cpu0-thermal { 5539 polling-delay-passive = <250>; 5540 5541 thermal-sensors = <&tsens0 1>; 5542 5543 trips { 5544 cpu0_alert0: trip-point0 { 5545 temperature = <90000>; 5546 hysteresis = <2000>; 5547 type = "passive"; 5548 }; 5549 5550 cpu0_alert1: trip-point1 { 5551 temperature = <95000>; 5552 hysteresis = <2000>; 5553 type = "passive"; 5554 }; 5555 5556 cpu0_crit: cpu-crit { 5557 temperature = <110000>; 5558 hysteresis = <1000>; 5559 type = "critical"; 5560 }; 5561 }; 5562 }; 5563 5564 cpu1-thermal { 5565 polling-delay-passive = <250>; 5566 5567 thermal-sensors = <&tsens0 2>; 5568 5569 trips { 5570 cpu1_alert0: trip-point0 { 5571 temperature = <90000>; 5572 hysteresis = <2000>; 5573 type = "passive"; 5574 }; 5575 5576 cpu1_alert1: trip-point1 { 5577 temperature = <95000>; 5578 hysteresis = <2000>; 5579 type = "passive"; 5580 }; 5581 5582 cpu1_crit: cpu-crit { 5583 temperature = <110000>; 5584 hysteresis = <1000>; 5585 type = "critical"; 5586 }; 5587 }; 5588 }; 5589 5590 cpu2-thermal { 5591 polling-delay-passive = <250>; 5592 5593 thermal-sensors = <&tsens0 3>; 5594 5595 trips { 5596 cpu2_alert0: trip-point0 { 5597 temperature = <90000>; 5598 hysteresis = <2000>; 5599 type = "passive"; 5600 }; 5601 5602 cpu2_alert1: trip-point1 { 5603 temperature = <95000>; 5604 hysteresis = <2000>; 5605 type = "passive"; 5606 }; 5607 5608 cpu2_crit: cpu-crit { 5609 temperature = <110000>; 5610 hysteresis = <1000>; 5611 type = "critical"; 5612 }; 5613 }; 5614 }; 5615 5616 cpu3-thermal { 5617 polling-delay-passive = <250>; 5618 5619 thermal-sensors = <&tsens0 4>; 5620 5621 trips { 5622 cpu3_alert0: trip-point0 { 5623 temperature = <90000>; 5624 hysteresis = <2000>; 5625 type = "passive"; 5626 }; 5627 5628 cpu3_alert1: trip-point1 { 5629 temperature = <95000>; 5630 hysteresis = <2000>; 5631 type = "passive"; 5632 }; 5633 5634 cpu3_crit: cpu-crit { 5635 temperature = <110000>; 5636 hysteresis = <1000>; 5637 type = "critical"; 5638 }; 5639 }; 5640 }; 5641 5642 cpu4-thermal { 5643 polling-delay-passive = <250>; 5644 5645 thermal-sensors = <&tsens0 7>; 5646 5647 trips { 5648 cpu4_alert0: trip-point0 { 5649 temperature = <90000>; 5650 hysteresis = <2000>; 5651 type = "passive"; 5652 }; 5653 5654 cpu4_alert1: trip-point1 { 5655 temperature = <95000>; 5656 hysteresis = <2000>; 5657 type = "passive"; 5658 }; 5659 5660 cpu4_crit: cpu-crit { 5661 temperature = <110000>; 5662 hysteresis = <1000>; 5663 type = "critical"; 5664 }; 5665 }; 5666 }; 5667 5668 cpu5-thermal { 5669 polling-delay-passive = <250>; 5670 5671 thermal-sensors = <&tsens0 8>; 5672 5673 trips { 5674 cpu5_alert0: trip-point0 { 5675 temperature = <90000>; 5676 hysteresis = <2000>; 5677 type = "passive"; 5678 }; 5679 5680 cpu5_alert1: trip-point1 { 5681 temperature = <95000>; 5682 hysteresis = <2000>; 5683 type = "passive"; 5684 }; 5685 5686 cpu5_crit: cpu-crit { 5687 temperature = <110000>; 5688 hysteresis = <1000>; 5689 type = "critical"; 5690 }; 5691 }; 5692 }; 5693 5694 cpu6-thermal { 5695 polling-delay-passive = <250>; 5696 5697 thermal-sensors = <&tsens0 9>; 5698 5699 trips { 5700 cpu6_alert0: trip-point0 { 5701 temperature = <90000>; 5702 hysteresis = <2000>; 5703 type = "passive"; 5704 }; 5705 5706 cpu6_alert1: trip-point1 { 5707 temperature = <95000>; 5708 hysteresis = <2000>; 5709 type = "passive"; 5710 }; 5711 5712 cpu6_crit: cpu-crit { 5713 temperature = <110000>; 5714 hysteresis = <1000>; 5715 type = "critical"; 5716 }; 5717 }; 5718 }; 5719 5720 cpu7-thermal { 5721 polling-delay-passive = <250>; 5722 5723 thermal-sensors = <&tsens0 10>; 5724 5725 trips { 5726 cpu7_alert0: trip-point0 { 5727 temperature = <90000>; 5728 hysteresis = <2000>; 5729 type = "passive"; 5730 }; 5731 5732 cpu7_alert1: trip-point1 { 5733 temperature = <95000>; 5734 hysteresis = <2000>; 5735 type = "passive"; 5736 }; 5737 5738 cpu7_crit: cpu-crit { 5739 temperature = <110000>; 5740 hysteresis = <1000>; 5741 type = "critical"; 5742 }; 5743 }; 5744 }; 5745 5746 aoss0-thermal { 5747 polling-delay-passive = <250>; 5748 5749 thermal-sensors = <&tsens0 0>; 5750 5751 trips { 5752 aoss0_alert0: trip-point0 { 5753 temperature = <90000>; 5754 hysteresis = <2000>; 5755 type = "hot"; 5756 }; 5757 }; 5758 }; 5759 5760 cluster0-thermal { 5761 polling-delay-passive = <250>; 5762 5763 thermal-sensors = <&tsens0 5>; 5764 5765 trips { 5766 cluster0_alert0: trip-point0 { 5767 temperature = <90000>; 5768 hysteresis = <2000>; 5769 type = "hot"; 5770 }; 5771 cluster0_crit: cluster0-crit { 5772 temperature = <110000>; 5773 hysteresis = <2000>; 5774 type = "critical"; 5775 }; 5776 }; 5777 }; 5778 5779 cluster1-thermal { 5780 polling-delay-passive = <250>; 5781 5782 thermal-sensors = <&tsens0 6>; 5783 5784 trips { 5785 cluster1_alert0: trip-point0 { 5786 temperature = <90000>; 5787 hysteresis = <2000>; 5788 type = "hot"; 5789 }; 5790 cluster1_crit: cluster1-crit { 5791 temperature = <110000>; 5792 hysteresis = <2000>; 5793 type = "critical"; 5794 }; 5795 }; 5796 }; 5797 5798 gpu-top-thermal { 5799 polling-delay-passive = <250>; 5800 5801 thermal-sensors = <&tsens0 11>; 5802 5803 cooling-maps { 5804 map0 { 5805 trip = <&gpu_top_alert0>; 5806 cooling-device = <&gpu THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 5807 }; 5808 }; 5809 5810 trips { 5811 gpu_top_alert0: trip-point0 { 5812 temperature = <85000>; 5813 hysteresis = <1000>; 5814 type = "passive"; 5815 }; 5816 5817 trip-point1 { 5818 temperature = <90000>; 5819 hysteresis = <1000>; 5820 type = "hot"; 5821 }; 5822 5823 trip-point2 { 5824 temperature = <110000>; 5825 hysteresis = <1000>; 5826 type = "critical"; 5827 }; 5828 }; 5829 }; 5830 5831 gpu-bottom-thermal { 5832 polling-delay-passive = <250>; 5833 5834 thermal-sensors = <&tsens0 12>; 5835 5836 cooling-maps { 5837 map0 { 5838 trip = <&gpu_bottom_alert0>; 5839 cooling-device = <&gpu THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 5840 }; 5841 }; 5842 5843 trips { 5844 gpu_bottom_alert0: trip-point0 { 5845 temperature = <85000>; 5846 hysteresis = <1000>; 5847 type = "passive"; 5848 }; 5849 5850 trip-point1 { 5851 temperature = <90000>; 5852 hysteresis = <1000>; 5853 type = "hot"; 5854 }; 5855 5856 trip-point2 { 5857 temperature = <110000>; 5858 hysteresis = <1000>; 5859 type = "critical"; 5860 }; 5861 }; 5862 }; 5863 5864 aoss1-thermal { 5865 polling-delay-passive = <250>; 5866 5867 thermal-sensors = <&tsens1 0>; 5868 5869 trips { 5870 aoss1_alert0: trip-point0 { 5871 temperature = <90000>; 5872 hysteresis = <2000>; 5873 type = "hot"; 5874 }; 5875 }; 5876 }; 5877 5878 q6-modem-thermal { 5879 polling-delay-passive = <250>; 5880 5881 thermal-sensors = <&tsens1 1>; 5882 5883 trips { 5884 q6_modem_alert0: trip-point0 { 5885 temperature = <90000>; 5886 hysteresis = <2000>; 5887 type = "hot"; 5888 }; 5889 }; 5890 }; 5891 5892 mem-thermal { 5893 polling-delay-passive = <250>; 5894 5895 thermal-sensors = <&tsens1 2>; 5896 5897 trips { 5898 mem_alert0: trip-point0 { 5899 temperature = <90000>; 5900 hysteresis = <2000>; 5901 type = "hot"; 5902 }; 5903 }; 5904 }; 5905 5906 wlan-thermal { 5907 polling-delay-passive = <250>; 5908 5909 thermal-sensors = <&tsens1 3>; 5910 5911 trips { 5912 wlan_alert0: trip-point0 { 5913 temperature = <90000>; 5914 hysteresis = <2000>; 5915 type = "hot"; 5916 }; 5917 }; 5918 }; 5919 5920 q6-hvx-thermal { 5921 polling-delay-passive = <250>; 5922 5923 thermal-sensors = <&tsens1 4>; 5924 5925 trips { 5926 q6_hvx_alert0: trip-point0 { 5927 temperature = <90000>; 5928 hysteresis = <2000>; 5929 type = "hot"; 5930 }; 5931 }; 5932 }; 5933 5934 camera-thermal { 5935 polling-delay-passive = <250>; 5936 5937 thermal-sensors = <&tsens1 5>; 5938 5939 trips { 5940 camera_alert0: trip-point0 { 5941 temperature = <90000>; 5942 hysteresis = <2000>; 5943 type = "hot"; 5944 }; 5945 }; 5946 }; 5947 5948 video-thermal { 5949 polling-delay-passive = <250>; 5950 5951 thermal-sensors = <&tsens1 6>; 5952 5953 trips { 5954 video_alert0: trip-point0 { 5955 temperature = <90000>; 5956 hysteresis = <2000>; 5957 type = "hot"; 5958 }; 5959 }; 5960 }; 5961 5962 modem-thermal { 5963 polling-delay-passive = <250>; 5964 5965 thermal-sensors = <&tsens1 7>; 5966 5967 trips { 5968 modem_alert0: trip-point0 { 5969 temperature = <90000>; 5970 hysteresis = <2000>; 5971 type = "hot"; 5972 }; 5973 }; 5974 }; 5975 }; 5976 5977 timer { 5978 compatible = "arm,armv8-timer"; 5979 interrupts = <GIC_PPI 1 IRQ_TYPE_LEVEL_LOW>, 5980 <GIC_PPI 2 IRQ_TYPE_LEVEL_LOW>, 5981 <GIC_PPI 3 IRQ_TYPE_LEVEL_LOW>, 5982 <GIC_PPI 0 IRQ_TYPE_LEVEL_LOW>; 5983 }; 5984}; 5985