1// SPDX-License-Identifier: (GPL-2.0 OR MIT) 2/* 3 * (C) 2018 MediaTek Inc. 4 * Copyright (C) 2022 BayLibre SAS 5 * Authors: Fabien Parent <fparent@baylibre.com> 6 * Bernhard Rosenkränzer <bero@baylibre.com> 7 * Alexandre Mergnat <amergnat@baylibre.com> 8 */ 9 10#include <dt-bindings/clock/mediatek,mt8365-clk.h> 11#include <dt-bindings/interrupt-controller/arm-gic.h> 12#include <dt-bindings/interrupt-controller/irq.h> 13#include <dt-bindings/memory/mediatek,mt8365-larb-port.h> 14#include <dt-bindings/phy/phy.h> 15#include <dt-bindings/power/mediatek,mt8365-power.h> 16 17/ { 18 compatible = "mediatek,mt8365"; 19 interrupt-parent = <&sysirq>; 20 #address-cells = <2>; 21 #size-cells = <2>; 22 23 aliases { 24 aal0 = &aal0; 25 ccorr0 = &ccorr0; 26 color0 = &color0; 27 dither0 = &dither0; 28 dpi0 = &dpi0; 29 dsi0 = &dsi0; 30 gamma0 = &gamma0; 31 ovl0 = &ovl0; 32 rdma0 = &rdma0; 33 rdma1 = &rdma1; 34 }; 35 36 cpus { 37 #address-cells = <1>; 38 #size-cells = <0>; 39 40 cluster0_opp: opp-table-0 { 41 compatible = "operating-points-v2"; 42 opp-shared; 43 44 opp-850000000 { 45 opp-hz = /bits/ 64 <850000000>; 46 opp-microvolt = <650000>; 47 }; 48 49 opp-918000000 { 50 opp-hz = /bits/ 64 <918000000>; 51 opp-microvolt = <668750>; 52 }; 53 54 opp-987000000 { 55 opp-hz = /bits/ 64 <987000000>; 56 opp-microvolt = <687500>; 57 }; 58 59 opp-1056000000 { 60 opp-hz = /bits/ 64 <1056000000>; 61 opp-microvolt = <706250>; 62 }; 63 64 opp-1125000000 { 65 opp-hz = /bits/ 64 <1125000000>; 66 opp-microvolt = <725000>; 67 }; 68 69 opp-1216000000 { 70 opp-hz = /bits/ 64 <1216000000>; 71 opp-microvolt = <750000>; 72 }; 73 74 opp-1308000000 { 75 opp-hz = /bits/ 64 <1308000000>; 76 opp-microvolt = <775000>; 77 }; 78 79 opp-1400000000 { 80 opp-hz = /bits/ 64 <1400000000>; 81 opp-microvolt = <800000>; 82 }; 83 84 opp-1466000000 { 85 opp-hz = /bits/ 64 <1466000000>; 86 opp-microvolt = <825000>; 87 }; 88 89 opp-1533000000 { 90 opp-hz = /bits/ 64 <1533000000>; 91 opp-microvolt = <850000>; 92 }; 93 94 opp-1633000000 { 95 opp-hz = /bits/ 64 <1633000000>; 96 opp-microvolt = <887500>; 97 }; 98 99 opp-1700000000 { 100 opp-hz = /bits/ 64 <1700000000>; 101 opp-microvolt = <912500>; 102 }; 103 104 opp-1767000000 { 105 opp-hz = /bits/ 64 <1767000000>; 106 opp-microvolt = <937500>; 107 }; 108 109 opp-1834000000 { 110 opp-hz = /bits/ 64 <1834000000>; 111 opp-microvolt = <962500>; 112 }; 113 114 opp-1917000000 { 115 opp-hz = /bits/ 64 <1917000000>; 116 opp-microvolt = <993750>; 117 }; 118 119 opp-2001000000 { 120 opp-hz = /bits/ 64 <2001000000>; 121 opp-microvolt = <1025000>; 122 }; 123 }; 124 125 cpu-map { 126 cluster0 { 127 core0 { 128 cpu = <&cpu0>; 129 }; 130 core1 { 131 cpu = <&cpu1>; 132 }; 133 core2 { 134 cpu = <&cpu2>; 135 }; 136 core3 { 137 cpu = <&cpu3>; 138 }; 139 }; 140 }; 141 142 cpu0: cpu@0 { 143 device_type = "cpu"; 144 compatible = "arm,cortex-a53"; 145 reg = <0x0>; 146 #cooling-cells = <2>; 147 enable-method = "psci"; 148 cpu-idle-states = <&CPU_MCDI &CLUSTER_MCDI &CLUSTER_DPIDLE>; 149 i-cache-size = <0x8000>; 150 i-cache-line-size = <64>; 151 i-cache-sets = <256>; 152 d-cache-size = <0x8000>; 153 d-cache-line-size = <64>; 154 d-cache-sets = <256>; 155 next-level-cache = <&l2>; 156 clocks = <&mcucfg CLK_MCU_BUS_SEL>, 157 <&apmixedsys CLK_APMIXED_MAINPLL>; 158 clock-names = "cpu", "intermediate"; 159 operating-points-v2 = <&cluster0_opp>; 160 }; 161 162 cpu1: cpu@1 { 163 device_type = "cpu"; 164 compatible = "arm,cortex-a53"; 165 reg = <0x1>; 166 #cooling-cells = <2>; 167 enable-method = "psci"; 168 cpu-idle-states = <&CPU_MCDI &CLUSTER_MCDI &CLUSTER_DPIDLE>; 169 i-cache-size = <0x8000>; 170 i-cache-line-size = <64>; 171 i-cache-sets = <256>; 172 d-cache-size = <0x8000>; 173 d-cache-line-size = <64>; 174 d-cache-sets = <256>; 175 next-level-cache = <&l2>; 176 clocks = <&mcucfg CLK_MCU_BUS_SEL>, 177 <&apmixedsys CLK_APMIXED_MAINPLL>; 178 clock-names = "cpu", "intermediate", "armpll"; 179 operating-points-v2 = <&cluster0_opp>; 180 }; 181 182 cpu2: cpu@2 { 183 device_type = "cpu"; 184 compatible = "arm,cortex-a53"; 185 reg = <0x2>; 186 #cooling-cells = <2>; 187 enable-method = "psci"; 188 cpu-idle-states = <&CPU_MCDI &CLUSTER_MCDI &CLUSTER_DPIDLE>; 189 i-cache-size = <0x8000>; 190 i-cache-line-size = <64>; 191 i-cache-sets = <256>; 192 d-cache-size = <0x8000>; 193 d-cache-line-size = <64>; 194 d-cache-sets = <256>; 195 next-level-cache = <&l2>; 196 clocks = <&mcucfg CLK_MCU_BUS_SEL>, 197 <&apmixedsys CLK_APMIXED_MAINPLL>; 198 clock-names = "cpu", "intermediate", "armpll"; 199 operating-points-v2 = <&cluster0_opp>; 200 }; 201 202 cpu3: cpu@3 { 203 device_type = "cpu"; 204 compatible = "arm,cortex-a53"; 205 reg = <0x3>; 206 #cooling-cells = <2>; 207 enable-method = "psci"; 208 cpu-idle-states = <&CPU_MCDI &CLUSTER_MCDI &CLUSTER_DPIDLE>; 209 i-cache-size = <0x8000>; 210 i-cache-line-size = <64>; 211 i-cache-sets = <256>; 212 d-cache-size = <0x8000>; 213 d-cache-line-size = <64>; 214 d-cache-sets = <256>; 215 next-level-cache = <&l2>; 216 clocks = <&mcucfg CLK_MCU_BUS_SEL>, 217 <&apmixedsys CLK_APMIXED_MAINPLL>; 218 clock-names = "cpu", "intermediate", "armpll"; 219 operating-points-v2 = <&cluster0_opp>; 220 }; 221 222 idle-states { 223 entry-method = "psci"; 224 225 CPU_MCDI: cpu-mcdi { 226 compatible = "arm,idle-state"; 227 local-timer-stop; 228 arm,psci-suspend-param = <0x00010001>; 229 entry-latency-us = <300>; 230 exit-latency-us = <200>; 231 min-residency-us = <1000>; 232 }; 233 234 CLUSTER_MCDI: cluster-mcdi { 235 compatible = "arm,idle-state"; 236 local-timer-stop; 237 arm,psci-suspend-param = <0x01010001>; 238 entry-latency-us = <350>; 239 exit-latency-us = <250>; 240 min-residency-us = <1200>; 241 }; 242 243 CLUSTER_DPIDLE: cluster-dpidle { 244 compatible = "arm,idle-state"; 245 local-timer-stop; 246 arm,psci-suspend-param = <0x01010004>; 247 entry-latency-us = <300>; 248 exit-latency-us = <800>; 249 min-residency-us = <3300>; 250 }; 251 }; 252 253 l2: l2-cache { 254 compatible = "cache"; 255 cache-level = <2>; 256 cache-size = <0x80000>; 257 cache-line-size = <64>; 258 cache-sets = <512>; 259 cache-unified; 260 }; 261 }; 262 263 clk26m: oscillator { 264 compatible = "fixed-clock"; 265 #clock-cells = <0>; 266 clock-frequency = <26000000>; 267 clock-output-names = "clk26m"; 268 }; 269 270 psci { 271 compatible = "arm,psci-1.0"; 272 method = "smc"; 273 }; 274 275 soc { 276 #address-cells = <2>; 277 #size-cells = <2>; 278 compatible = "simple-bus"; 279 ranges; 280 281 gic: interrupt-controller@c000000 { 282 compatible = "arm,gic-v3"; 283 #interrupt-cells = <3>; 284 interrupt-parent = <&gic>; 285 interrupt-controller; 286 reg = <0 0x0c000000 0 0x10000>, /* GICD */ 287 <0 0x0c080000 0 0x80000>, /* GICR */ 288 <0 0x0c400000 0 0x2000>, /* GICC */ 289 <0 0x0c410000 0 0x1000>, /* GICH */ 290 <0 0x0c420000 0 0x2000>; /* GICV */ 291 292 interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>; 293 }; 294 295 topckgen: syscon@10000000 { 296 compatible = "mediatek,mt8365-topckgen", "syscon"; 297 reg = <0 0x10000000 0 0x1000>; 298 #clock-cells = <1>; 299 }; 300 301 infracfg: syscon@10001000 { 302 compatible = "mediatek,mt8365-infracfg", "syscon"; 303 reg = <0 0x10001000 0 0x1000>; 304 #clock-cells = <1>; 305 }; 306 307 pericfg: syscon@10003000 { 308 compatible = "mediatek,mt8365-pericfg", "syscon"; 309 reg = <0 0x10003000 0 0x1000>; 310 #clock-cells = <1>; 311 }; 312 313 syscfg_pctl: syscfg-pctl@10005000 { 314 compatible = "mediatek,mt8365-syscfg", "syscon"; 315 reg = <0 0x10005000 0 0x1000>; 316 }; 317 318 scpsys: syscon@10006000 { 319 compatible = "mediatek,mt8365-scpsys", "syscon", "simple-mfd"; 320 reg = <0 0x10006000 0 0x1000>; 321 322 /* System Power Manager */ 323 spm: power-controller { 324 compatible = "mediatek,mt8365-power-controller"; 325 #address-cells = <1>; 326 #size-cells = <0>; 327 #power-domain-cells = <1>; 328 329 /* power domains of the SoC */ 330 power-domain@MT8365_POWER_DOMAIN_MM { 331 reg = <MT8365_POWER_DOMAIN_MM>; 332 clocks = <&topckgen CLK_TOP_MM_SEL>, 333 <&mmsys CLK_MM_MM_SMI_COMMON>, 334 <&mmsys CLK_MM_MM_SMI_COMM0>, 335 <&mmsys CLK_MM_MM_SMI_COMM1>, 336 <&mmsys CLK_MM_MM_SMI_LARB0>; 337 clock-names = "mm", "mm-0", "mm-1", 338 "mm-2", "mm-3"; 339 #power-domain-cells = <0>; 340 mediatek,infracfg = <&infracfg>; 341 mediatek,infracfg-nao = <&infracfg_nao>; 342 #address-cells = <1>; 343 #size-cells = <0>; 344 345 power-domain@MT8365_POWER_DOMAIN_CAM { 346 reg = <MT8365_POWER_DOMAIN_CAM>; 347 clocks = <&camsys CLK_CAM_LARB2>, 348 <&camsys CLK_CAM_SENIF>, 349 <&camsys CLK_CAMSV0>, 350 <&camsys CLK_CAMSV1>, 351 <&camsys CLK_CAM_FDVT>, 352 <&camsys CLK_CAM_WPE>; 353 clock-names = "cam-0", "cam-1", 354 "cam-2", "cam-3", 355 "cam-4", "cam-5"; 356 #power-domain-cells = <0>; 357 mediatek,infracfg = <&infracfg>; 358 mediatek,smi = <&smi_common>; 359 }; 360 361 power-domain@MT8365_POWER_DOMAIN_VDEC { 362 reg = <MT8365_POWER_DOMAIN_VDEC>; 363 #power-domain-cells = <0>; 364 mediatek,smi = <&smi_common>; 365 }; 366 367 power-domain@MT8365_POWER_DOMAIN_VENC { 368 reg = <MT8365_POWER_DOMAIN_VENC>; 369 #power-domain-cells = <0>; 370 mediatek,smi = <&smi_common>; 371 }; 372 373 power-domain@MT8365_POWER_DOMAIN_APU { 374 reg = <MT8365_POWER_DOMAIN_APU>; 375 clocks = <&infracfg CLK_IFR_APU_AXI>, 376 <&apu CLK_APU_IPU_CK>, 377 <&apu CLK_APU_AXI>, 378 <&apu CLK_APU_JTAG>, 379 <&apu CLK_APU_IF_CK>, 380 <&apu CLK_APU_EDMA>, 381 <&apu CLK_APU_AHB>; 382 clock-names = "apu", "apu-0", 383 "apu-1", "apu-2", 384 "apu-3", "apu-4", 385 "apu-5"; 386 #power-domain-cells = <0>; 387 mediatek,infracfg = <&infracfg>; 388 mediatek,smi = <&smi_common>; 389 }; 390 }; 391 392 power-domain@MT8365_POWER_DOMAIN_CONN { 393 reg = <MT8365_POWER_DOMAIN_CONN>; 394 clocks = <&topckgen CLK_TOP_CONN_32K>, 395 <&topckgen CLK_TOP_CONN_26M>; 396 clock-names = "conn", "conn1"; 397 #power-domain-cells = <0>; 398 mediatek,infracfg = <&infracfg>; 399 }; 400 401 power-domain@MT8365_POWER_DOMAIN_MFG { 402 reg = <MT8365_POWER_DOMAIN_MFG>; 403 clocks = <&topckgen CLK_TOP_MFG_SEL>; 404 clock-names = "mfg"; 405 #power-domain-cells = <0>; 406 mediatek,infracfg = <&infracfg>; 407 }; 408 409 power-domain@MT8365_POWER_DOMAIN_AUDIO { 410 reg = <MT8365_POWER_DOMAIN_AUDIO>; 411 clocks = <&topckgen CLK_TOP_AUD_INTBUS_SEL>, 412 <&infracfg CLK_IFR_AUDIO>, 413 <&infracfg CLK_IFR_AUD_26M_BK>; 414 clock-names = "audio", "audio1", "audio2"; 415 #power-domain-cells = <0>; 416 mediatek,infracfg = <&infracfg>; 417 }; 418 419 power-domain@MT8365_POWER_DOMAIN_DSP { 420 reg = <MT8365_POWER_DOMAIN_DSP>; 421 clocks = <&topckgen CLK_TOP_DSP_SEL>, 422 <&topckgen CLK_TOP_DSP_26M>; 423 clock-names = "dsp", "dsp1"; 424 #power-domain-cells = <0>; 425 mediatek,infracfg = <&infracfg>; 426 }; 427 }; 428 }; 429 430 watchdog: watchdog@10007000 { 431 compatible = "mediatek,mt8365-wdt", "mediatek,mt6589-wdt"; 432 reg = <0 0x10007000 0 0x100>; 433 #reset-cells = <1>; 434 }; 435 436 pio: pinctrl@1000b000 { 437 compatible = "mediatek,mt8365-pinctrl"; 438 reg = <0 0x1000b000 0 0x1000>; 439 mediatek,pctl-regmap = <&syscfg_pctl>; 440 gpio-controller; 441 #gpio-cells = <2>; 442 interrupt-controller; 443 #interrupt-cells = <2>; 444 interrupts = <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>; 445 }; 446 447 apmixedsys: syscon@1000c000 { 448 compatible = "mediatek,mt8365-apmixedsys", "syscon"; 449 reg = <0 0x1000c000 0 0x1000>; 450 #clock-cells = <1>; 451 }; 452 453 pwrap: pwrap@1000d000 { 454 compatible = "mediatek,mt8365-pwrap"; 455 reg = <0 0x1000d000 0 0x1000>; 456 reg-names = "pwrap"; 457 interrupts = <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>; 458 clocks = <&infracfg CLK_IFR_PWRAP_SPI>, 459 <&infracfg CLK_IFR_PMIC_AP>, 460 <&infracfg CLK_IFR_PWRAP_SYS>, 461 <&infracfg CLK_IFR_PWRAP_TMR>; 462 clock-names = "spi", "wrap", "sys", "tmr"; 463 }; 464 465 keypad: keypad@10010000 { 466 compatible = "mediatek,mt8365-keypad", 467 "mediatek,mt6779-keypad"; 468 reg = <0 0x10010000 0 0x1000>; 469 wakeup-source; 470 interrupts = <GIC_SPI 124 IRQ_TYPE_EDGE_FALLING>; 471 clocks = <&clk26m>; 472 clock-names = "kpd"; 473 status = "disabled"; 474 }; 475 476 mcucfg: syscon@10200000 { 477 compatible = "mediatek,mt8365-mcucfg", "syscon"; 478 reg = <0 0x10200000 0 0x2000>; 479 #clock-cells = <1>; 480 }; 481 482 sysirq: interrupt-controller@10200a80 { 483 compatible = "mediatek,mt8365-sysirq", "mediatek,mt6577-sysirq"; 484 interrupt-controller; 485 #interrupt-cells = <3>; 486 interrupt-parent = <&gic>; 487 reg = <0 0x10200a80 0 0x20>; 488 }; 489 490 iommu: iommu@10205000 { 491 compatible = "mediatek,mt8365-m4u"; 492 reg = <0 0x10205000 0 0x1000>; 493 interrupts = <GIC_SPI 102 IRQ_TYPE_LEVEL_LOW>; 494 mediatek,larbs = <&larb0>, <&larb1>, <&larb2>, <&larb3>; 495 #iommu-cells = <1>; 496 }; 497 498 infracfg_nao: infracfg@1020e000 { 499 compatible = "mediatek,mt8365-infracfg", "syscon"; 500 reg = <0 0x1020e000 0 0x1000>; 501 #clock-cells = <1>; 502 }; 503 504 rng: rng@1020f000 { 505 compatible = "mediatek,mt8365-rng", "mediatek,mt7623-rng"; 506 reg = <0 0x1020f000 0 0x100>; 507 clocks = <&infracfg CLK_IFR_TRNG>; 508 clock-names = "rng"; 509 }; 510 511 apdma: dma-controller@11000280 { 512 compatible = "mediatek,mt8365-uart-dma", "mediatek,mt6577-uart-dma"; 513 reg = <0 0x11000280 0 0x80>, 514 <0 0x11000300 0 0x80>, 515 <0 0x11000380 0 0x80>, 516 <0 0x11000400 0 0x80>, 517 <0 0x11000580 0 0x80>, 518 <0 0x11000600 0 0x80>; 519 interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_LOW>, 520 <GIC_SPI 46 IRQ_TYPE_LEVEL_LOW>, 521 <GIC_SPI 47 IRQ_TYPE_LEVEL_LOW>, 522 <GIC_SPI 48 IRQ_TYPE_LEVEL_LOW>, 523 <GIC_SPI 51 IRQ_TYPE_LEVEL_LOW>, 524 <GIC_SPI 52 IRQ_TYPE_LEVEL_LOW>; 525 dma-requests = <6>; 526 clocks = <&infracfg CLK_IFR_AP_DMA>; 527 clock-names = "apdma"; 528 #dma-cells = <1>; 529 }; 530 531 uart0: serial@11002000 { 532 compatible = "mediatek,mt8365-uart", "mediatek,mt6577-uart"; 533 reg = <0 0x11002000 0 0x1000>; 534 interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_LOW>; 535 clocks = <&clk26m>, <&infracfg CLK_IFR_UART0>; 536 clock-names = "baud", "bus"; 537 dmas = <&apdma 0>, <&apdma 1>; 538 dma-names = "tx", "rx"; 539 status = "disabled"; 540 }; 541 542 uart1: serial@11003000 { 543 compatible = "mediatek,mt8365-uart", "mediatek,mt6577-uart"; 544 reg = <0 0x11003000 0 0x1000>; 545 interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_LOW>; 546 clocks = <&clk26m>, <&infracfg CLK_IFR_UART1>; 547 clock-names = "baud", "bus"; 548 dmas = <&apdma 2>, <&apdma 3>; 549 dma-names = "tx", "rx"; 550 status = "disabled"; 551 }; 552 553 uart2: serial@11004000 { 554 compatible = "mediatek,mt8365-uart", "mediatek,mt6577-uart"; 555 reg = <0 0x11004000 0 0x1000>; 556 interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_LOW>; 557 clocks = <&clk26m>, <&infracfg CLK_IFR_UART2>; 558 clock-names = "baud", "bus"; 559 dmas = <&apdma 4>, <&apdma 5>; 560 dma-names = "tx", "rx"; 561 status = "disabled"; 562 }; 563 564 pwm: pwm@11006000 { 565 compatible = "mediatek,mt8365-pwm"; 566 reg = <0 0x11006000 0 0x1000>; 567 #pwm-cells = <2>; 568 interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_LOW>; 569 clocks = <&infracfg CLK_IFR_PWM_HCLK>, 570 <&infracfg CLK_IFR_PWM>, 571 <&infracfg CLK_IFR_PWM1>, 572 <&infracfg CLK_IFR_PWM2>, 573 <&infracfg CLK_IFR_PWM3>; 574 clock-names = "top", "main", "pwm1", "pwm2", "pwm3"; 575 }; 576 577 i2c0: i2c@11007000 { 578 compatible = "mediatek,mt8365-i2c", "mediatek,mt8168-i2c"; 579 reg = <0 0x11007000 0 0xa0>, <0 0x11000080 0 0x80>; 580 interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_LOW>; 581 clock-div = <1>; 582 clocks = <&infracfg CLK_IFR_I2C0_AXI>, <&infracfg CLK_IFR_AP_DMA>; 583 clock-names = "main", "dma"; 584 #address-cells = <1>; 585 #size-cells = <0>; 586 status = "disabled"; 587 }; 588 589 i2c1: i2c@11008000 { 590 compatible = "mediatek,mt8365-i2c", "mediatek,mt8168-i2c"; 591 reg = <0 0x11008000 0 0xa0>, <0 0x11000100 0 0x80>; 592 interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_LOW>; 593 clock-div = <1>; 594 clocks = <&infracfg CLK_IFR_I2C1_AXI>, <&infracfg CLK_IFR_AP_DMA>; 595 clock-names = "main", "dma"; 596 #address-cells = <1>; 597 #size-cells = <0>; 598 status = "disabled"; 599 }; 600 601 i2c2: i2c@11009000 { 602 compatible = "mediatek,mt8365-i2c", "mediatek,mt8168-i2c"; 603 reg = <0 0x11009000 0 0xa0>, <0 0x11000180 0 0x80>; 604 interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_LOW>; 605 clock-div = <1>; 606 clocks = <&infracfg CLK_IFR_I2C2_AXI>, <&infracfg CLK_IFR_AP_DMA>; 607 clock-names = "main", "dma"; 608 #address-cells = <1>; 609 #size-cells = <0>; 610 status = "disabled"; 611 }; 612 613 spi: spi@1100a000 { 614 compatible = "mediatek,mt8365-spi", "mediatek,mt7622-spi"; 615 reg = <0 0x1100a000 0 0x100>; 616 #address-cells = <1>; 617 #size-cells = <0>; 618 interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_LOW>; 619 clocks = <&topckgen CLK_TOP_UNIVPLL2_D4>, 620 <&topckgen CLK_TOP_SPI_SEL>, 621 <&infracfg CLK_IFR_SPI0>; 622 clock-names = "parent-clk", "sel-clk", "spi-clk"; 623 status = "disabled"; 624 }; 625 626 disp_pwm: pwm@1100e000 { 627 compatible = "mediatek,mt8365-disp-pwm", "mediatek,mt8183-disp-pwm"; 628 reg = <0 0x1100e000 0 0x1000>; 629 clock-names = "main", "mm"; 630 clocks = <&topckgen CLK_TOP_DISP_PWM_SEL>, <&infracfg CLK_IFR_DISP_PWM>; 631 power-domains = <&spm MT8365_POWER_DOMAIN_MM>; 632 #pwm-cells = <2>; 633 }; 634 635 i2c3: i2c@1100f000 { 636 compatible = "mediatek,mt8365-i2c", "mediatek,mt8168-i2c"; 637 reg = <0 0x1100f000 0 0xa0>, <0 0x11000200 0 0x80>; 638 interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_LOW>; 639 clock-div = <1>; 640 clocks = <&infracfg CLK_IFR_I2C3_AXI>, <&infracfg CLK_IFR_AP_DMA>; 641 clock-names = "main", "dma"; 642 #address-cells = <1>; 643 #size-cells = <0>; 644 status = "disabled"; 645 }; 646 647 ssusb: usb@11201000 { 648 compatible = "mediatek,mt8365-mtu3", "mediatek,mtu3"; 649 reg = <0 0x11201000 0 0x2e00>, <0 0x11203e00 0 0x0100>; 650 reg-names = "mac", "ippc"; 651 interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_LOW>; 652 phys = <&u2port0 PHY_TYPE_USB2>, 653 <&u2port1 PHY_TYPE_USB2>; 654 clocks = <&topckgen CLK_TOP_SSUSB_TOP_CK_EN>, 655 <&infracfg CLK_IFR_SSUSB_REF>, 656 <&infracfg CLK_IFR_SSUSB_SYS>, 657 <&infracfg CLK_IFR_ICUSB>; 658 clock-names = "sys_ck", "ref_ck", "mcu_ck", "dma_ck"; 659 #address-cells = <2>; 660 #size-cells = <2>; 661 ranges; 662 status = "disabled"; 663 664 usb_host: usb@11200000 { 665 compatible = "mediatek,mt8365-xhci", "mediatek,mtk-xhci"; 666 reg = <0 0x11200000 0 0x1000>; 667 reg-names = "mac"; 668 interrupts = <GIC_SPI 67 IRQ_TYPE_LEVEL_LOW>; 669 clocks = <&topckgen CLK_TOP_SSUSB_TOP_CK_EN>, 670 <&infracfg CLK_IFR_SSUSB_REF>, 671 <&infracfg CLK_IFR_SSUSB_SYS>, 672 <&infracfg CLK_IFR_ICUSB>, 673 <&infracfg CLK_IFR_SSUSB_XHCI>; 674 clock-names = "sys_ck", "ref_ck", "mcu_ck", 675 "dma_ck", "xhci_ck"; 676 status = "disabled"; 677 }; 678 }; 679 680 mmc0: mmc@11230000 { 681 compatible = "mediatek,mt8365-mmc", "mediatek,mt8183-mmc"; 682 reg = <0 0x11230000 0 0x1000>, 683 <0 0x11cd0000 0 0x1000>; 684 interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_LOW>; 685 clocks = <&topckgen CLK_TOP_MSDC50_0_SEL>, 686 <&infracfg CLK_IFR_MSDC0_HCLK>, 687 <&infracfg CLK_IFR_MSDC0_SRC>; 688 clock-names = "source", "hclk", "source_cg"; 689 status = "disabled"; 690 }; 691 692 mmc1: mmc@11240000 { 693 compatible = "mediatek,mt8365-mmc", "mediatek,mt8183-mmc"; 694 reg = <0 0x11240000 0 0x1000>, 695 <0 0x11c90000 0 0x1000>; 696 interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_LOW>; 697 clocks = <&topckgen CLK_TOP_MSDC30_1_SEL>, 698 <&infracfg CLK_IFR_MSDC1_HCLK>, 699 <&infracfg CLK_IFR_MSDC1_SRC>; 700 clock-names = "source", "hclk", "source_cg"; 701 status = "disabled"; 702 }; 703 704 mmc2: mmc@11250000 { 705 compatible = "mediatek,mt8365-mmc", "mediatek,mt8183-mmc"; 706 reg = <0 0x11250000 0 0x1000>, 707 <0 0x11c60000 0 0x1000>; 708 interrupts = <GIC_SPI 68 IRQ_TYPE_LEVEL_LOW>; 709 clocks = <&topckgen CLK_TOP_MSDC50_2_SEL>, 710 <&infracfg CLK_IFR_MSDC2_HCLK>, 711 <&infracfg CLK_IFR_MSDC2_SRC>, 712 <&infracfg CLK_IFR_MSDC2_BK>, 713 <&infracfg CLK_IFR_AP_MSDC0>; 714 clock-names = "source", "hclk", "source_cg", 715 "bus_clk", "sys_cg"; 716 status = "disabled"; 717 }; 718 719 ethernet: ethernet@112a0000 { 720 compatible = "mediatek,mt8365-eth"; 721 reg = <0 0x112a0000 0 0x1000>; 722 mediatek,pericfg = <&infracfg>; 723 interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>; 724 clocks = <&topckgen CLK_TOP_ETH_SEL>, 725 <&infracfg CLK_IFR_NIC_AXI>, 726 <&infracfg CLK_IFR_NIC_SLV_AXI>; 727 clock-names = "core", "reg", "trans"; 728 status = "disabled"; 729 }; 730 731 mipi_tx0: dsi-phy@11c00000 { 732 compatible = "mediatek,mt8365-mipi-tx", "mediatek,mt8183-mipi-tx"; 733 reg = <0 0x11c00000 0 0x800>; 734 clock-output-names = "mipi_tx0_pll"; 735 clocks = <&clk26m>; 736 #clock-cells = <0>; 737 #phy-cells = <0>; 738 }; 739 740 u3phy: t-phy@11cc0000 { 741 compatible = "mediatek,mt8365-tphy", "mediatek,generic-tphy-v2"; 742 #address-cells = <1>; 743 #size-cells = <1>; 744 ranges = <0 0 0x11cc0000 0x9000>; 745 746 u2port0: usb-phy@0 { 747 reg = <0x0 0x400>; 748 clocks = <&topckgen CLK_TOP_SSUSB_PHY_CK_EN>, 749 <&topckgen CLK_TOP_USB20_48M_EN>; 750 clock-names = "ref", "da_ref"; 751 #phy-cells = <1>; 752 }; 753 754 u2port1: usb-phy@1000 { 755 reg = <0x1000 0x400>; 756 clocks = <&topckgen CLK_TOP_SSUSB_PHY_CK_EN>, 757 <&topckgen CLK_TOP_USB20_48M_EN>; 758 clock-names = "ref", "da_ref"; 759 #phy-cells = <1>; 760 }; 761 }; 762 763 mmsys: syscon@14000000 { 764 compatible = "mediatek,mt8365-mmsys", "syscon"; 765 reg = <0 0x14000000 0 0x1000>; 766 #clock-cells = <1>; 767 port { 768 #address-cells = <1>; 769 #size-cells = <0>; 770 771 mmsys_main: endpoint@0 { 772 reg = <0>; 773 remote-endpoint = <&ovl0_in>; 774 }; 775 mmsys_ext: endpoint@1 { 776 reg = <1>; 777 remote-endpoint = <&rdma1_in>; 778 }; 779 }; 780 }; 781 782 mutex: mutex@14001000 { 783 compatible = "mediatek,mt8365-disp-mutex"; 784 reg = <0 0x14001000 0 0x1000>; 785 interrupts = <GIC_SPI 154 IRQ_TYPE_LEVEL_LOW>; 786 power-domains = <&spm MT8365_POWER_DOMAIN_MM>; 787 }; 788 789 smi_common: smi@14002000 { 790 compatible = "mediatek,mt8365-smi-common"; 791 reg = <0 0x14002000 0 0x1000>; 792 clocks = <&mmsys CLK_MM_MM_SMI_COMMON>, 793 <&mmsys CLK_MM_MM_SMI_COMMON>, 794 <&mmsys CLK_MM_MM_SMI_COMM0>, 795 <&mmsys CLK_MM_MM_SMI_COMM1>; 796 clock-names = "apb", "smi", "gals0", "gals1"; 797 power-domains = <&spm MT8365_POWER_DOMAIN_MM>; 798 }; 799 800 larb0: larb@14003000 { 801 compatible = "mediatek,mt8365-smi-larb", 802 "mediatek,mt8186-smi-larb"; 803 reg = <0 0x14003000 0 0x1000>; 804 mediatek,smi = <&smi_common>; 805 clocks = <&mmsys CLK_MM_MM_SMI_LARB0>, 806 <&mmsys CLK_MM_MM_SMI_LARB0>; 807 clock-names = "apb", "smi"; 808 power-domains = <&spm MT8365_POWER_DOMAIN_MM>; 809 mediatek,larb-id = <0>; 810 }; 811 812 ovl0: ovl@1400b000 { 813 compatible = "mediatek,mt8365-disp-ovl", "mediatek,mt8192-disp-ovl"; 814 reg = <0 0x1400b000 0 0x1000>; 815 clocks = <&mmsys CLK_MM_MM_DISP_OVL0>; 816 interrupts = <GIC_SPI 161 IRQ_TYPE_LEVEL_LOW>; 817 iommus = <&iommu M4U_PORT_DISP_OVL0>; 818 power-domains = <&spm MT8365_POWER_DOMAIN_MM>; 819 ports { 820 #address-cells = <1>; 821 #size-cells = <0>; 822 823 port@0 { 824 #address-cells = <1>; 825 #size-cells = <0>; 826 reg = <0>; 827 ovl0_in: endpoint@0 { 828 reg = <0>; 829 remote-endpoint = <&mmsys_main>; 830 }; 831 }; 832 833 port@1 { 834 #address-cells = <1>; 835 #size-cells = <0>; 836 reg = <1>; 837 ovl0_out: endpoint@0 { 838 reg = <0>; 839 remote-endpoint = <&rdma0_in>; 840 }; 841 }; 842 }; 843 }; 844 845 rdma0: rdma@1400d000 { 846 compatible = "mediatek,mt8365-disp-rdma", "mediatek,mt8183-disp-rdma"; 847 reg = <0 0x1400d000 0 0x1000>; 848 clocks = <&mmsys CLK_MM_MM_DISP_RDMA0>; 849 interrupts = <GIC_SPI 162 IRQ_TYPE_LEVEL_LOW>; 850 iommus = <&iommu M4U_PORT_DISP_RDMA0>; 851 mediatek,rdma-fifo-size = <5120>; 852 power-domains = <&spm MT8365_POWER_DOMAIN_MM>; 853 ports { 854 #address-cells = <1>; 855 #size-cells = <0>; 856 857 port@0 { 858 #address-cells = <1>; 859 #size-cells = <0>; 860 reg = <0>; 861 rdma0_in: endpoint@0 { 862 reg = <0>; 863 remote-endpoint = <&ovl0_out>; 864 }; 865 }; 866 867 port@1 { 868 #address-cells = <1>; 869 #size-cells = <0>; 870 reg = <1>; 871 rdma0_out: endpoint@0 { 872 reg = <0>; 873 remote-endpoint = <&color0_in>; 874 }; 875 }; 876 }; 877 }; 878 879 color0: color@1400f000 { 880 compatible = "mediatek,mt8365-disp-color", "mediatek,mt8173-disp-color"; 881 reg = <0 0x1400f000 0 0x1000>; 882 clocks = <&mmsys CLK_MM_MM_DISP_COLOR0>; 883 interrupts = <GIC_SPI 164 IRQ_TYPE_LEVEL_LOW>; 884 power-domains = <&spm MT8365_POWER_DOMAIN_MM>; 885 ports { 886 #address-cells = <1>; 887 #size-cells = <0>; 888 889 port@0 { 890 #address-cells = <1>; 891 #size-cells = <0>; 892 reg = <0>; 893 color0_in: endpoint@0 { 894 reg = <0>; 895 remote-endpoint = <&rdma0_out>; 896 }; 897 }; 898 899 port@1 { 900 #address-cells = <1>; 901 #size-cells = <0>; 902 reg = <1>; 903 color0_out: endpoint@0 { 904 reg = <0>; 905 remote-endpoint = <&ccorr0_in>; 906 }; 907 }; 908 }; 909 }; 910 911 ccorr0: ccorr@14010000 { 912 compatible = "mediatek,mt8365-disp-ccorr", "mediatek,mt8183-disp-ccorr"; 913 reg = <0 0x14010000 0 0x1000>; 914 clocks = <&mmsys CLK_MM_MM_DISP_CCORR0>; 915 interrupts = <GIC_SPI 165 IRQ_TYPE_LEVEL_LOW>; 916 power-domains = <&spm MT8365_POWER_DOMAIN_MM>; 917 ports { 918 #address-cells = <1>; 919 #size-cells = <0>; 920 921 port@0 { 922 #address-cells = <1>; 923 #size-cells = <0>; 924 reg = <0>; 925 ccorr0_in: endpoint@0 { 926 reg = <0>; 927 remote-endpoint = <&color0_out>; 928 }; 929 }; 930 931 port@1 { 932 #address-cells = <1>; 933 #size-cells = <0>; 934 reg = <1>; 935 ccorr0_out: endpoint@0 { 936 reg = <0>; 937 remote-endpoint = <&aal0_in>; 938 }; 939 }; 940 }; 941 }; 942 943 aal0: aal@14011000 { 944 compatible = "mediatek,mt8365-disp-aal", "mediatek,mt8183-disp-aal"; 945 reg = <0 0x14011000 0 0x1000>; 946 clocks = <&mmsys CLK_MM_MM_DISP_AAL0>; 947 interrupts = <GIC_SPI 166 IRQ_TYPE_LEVEL_LOW>; 948 power-domains = <&spm MT8365_POWER_DOMAIN_MM>; 949 ports { 950 #address-cells = <1>; 951 #size-cells = <0>; 952 953 port@0 { 954 #address-cells = <1>; 955 #size-cells = <0>; 956 reg = <0>; 957 aal0_in: endpoint@0 { 958 reg = <0>; 959 remote-endpoint = <&ccorr0_out>; 960 }; 961 }; 962 963 port@1 { 964 #address-cells = <1>; 965 #size-cells = <0>; 966 reg = <1>; 967 aal0_out: endpoint@0 { 968 reg = <0>; 969 remote-endpoint = <&gamma0_in>; 970 }; 971 }; 972 }; 973 }; 974 975 gamma0: gamma@14012000 { 976 compatible = "mediatek,mt8365-disp-gamma", "mediatek,mt8183-disp-gamma"; 977 reg = <0 0x14012000 0 0x1000>; 978 clocks = <&mmsys CLK_MM_MM_DISP_GAMMA0>; 979 interrupts = <GIC_SPI 167 IRQ_TYPE_LEVEL_LOW>; 980 power-domains = <&spm MT8365_POWER_DOMAIN_MM>; 981 ports { 982 #address-cells = <1>; 983 #size-cells = <0>; 984 985 port@0 { 986 #address-cells = <1>; 987 #size-cells = <0>; 988 reg = <0>; 989 gamma0_in: endpoint@0 { 990 reg = <0>; 991 remote-endpoint = <&aal0_out>; 992 }; 993 }; 994 995 port@1 { 996 #address-cells = <1>; 997 #size-cells = <0>; 998 reg = <1>; 999 gamma0_out: endpoint@0 { 1000 reg = <0>; 1001 remote-endpoint = <&dither0_in>; 1002 }; 1003 }; 1004 }; 1005 }; 1006 1007 dither0: dither@14013000 { 1008 compatible = "mediatek,mt8365-disp-dither", "mediatek,mt8183-disp-dither"; 1009 reg = <0 0x14013000 0 0x1000>; 1010 clocks = <&mmsys CLK_MM_MM_DISP_DITHER0>; 1011 interrupts = <GIC_SPI 168 IRQ_TYPE_LEVEL_LOW>; 1012 power-domains = <&spm MT8365_POWER_DOMAIN_MM>; 1013 ports { 1014 #address-cells = <1>; 1015 #size-cells = <0>; 1016 1017 port@0 { 1018 #address-cells = <1>; 1019 #size-cells = <0>; 1020 reg = <0>; 1021 dither0_in: endpoint@0 { 1022 reg = <0>; 1023 remote-endpoint = <&gamma0_out>; 1024 }; 1025 }; 1026 1027 port@1 { 1028 #address-cells = <1>; 1029 #size-cells = <0>; 1030 reg = <1>; 1031 dither0_out: endpoint@0 { 1032 reg = <0>; 1033 }; 1034 }; 1035 }; 1036 }; 1037 1038 dsi0: dsi@14014000 { 1039 compatible = "mediatek,mt8365-dsi", "mediatek,mt8183-dsi"; 1040 reg = <0 0x14014000 0 0x1000>; 1041 clock-names = "engine", "digital", "hs"; 1042 clocks = <&mmsys CLK_MM_MM_DSI0>, 1043 <&mmsys CLK_MM_DSI0_DIG_DSI>, 1044 <&mipi_tx0>; 1045 interrupts = <GIC_SPI 169 IRQ_TYPE_LEVEL_LOW>; 1046 phy-names = "dphy"; 1047 phys = <&mipi_tx0>; 1048 power-domains = <&spm MT8365_POWER_DOMAIN_MM>; 1049 }; 1050 1051 rdma1: rdma@14016000 { 1052 compatible = "mediatek,mt8365-disp-rdma", "mediatek,mt8183-disp-rdma"; 1053 reg = <0 0x14016000 0 0x1000>; 1054 clocks = <&mmsys CLK_MM_MM_DISP_RDMA1>; 1055 interrupts = <GIC_SPI 195 IRQ_TYPE_LEVEL_LOW>; 1056 iommus = <&iommu M4U_PORT_DISP_RDMA1>; 1057 mediatek,rdma-fifo-size = <2048>; 1058 power-domains = <&spm MT8365_POWER_DOMAIN_MM>; 1059 ports { 1060 #address-cells = <1>; 1061 #size-cells = <0>; 1062 1063 port@0 { 1064 #address-cells = <1>; 1065 #size-cells = <0>; 1066 reg = <0>; 1067 rdma1_in: endpoint@1 { 1068 reg = <1>; 1069 remote-endpoint = <&mmsys_ext>; 1070 }; 1071 }; 1072 1073 port@1 { 1074 #address-cells = <1>; 1075 #size-cells = <0>; 1076 reg = <1>; 1077 rdma1_out: endpoint@1 { 1078 reg = <1>; 1079 }; 1080 }; 1081 }; 1082 }; 1083 1084 dpi0: dpi@14018000 { 1085 compatible = "mediatek,mt8365-dpi", "mediatek,mt8192-dpi"; 1086 reg = <0 0x14018000 0 0x1000>; 1087 clocks = <&mmsys CLK_MM_DPI0_DPI0>, 1088 <&mmsys CLK_MM_MM_DPI0>, 1089 <&apmixedsys CLK_APMIXED_LVDSPLL>; 1090 clock-names = "pixel", "engine", "pll"; 1091 interrupts = <GIC_SPI 197 IRQ_TYPE_LEVEL_LOW>; 1092 power-domains = <&spm MT8365_POWER_DOMAIN_MM>; 1093 status = "disabled"; 1094 }; 1095 1096 camsys: syscon@15000000 { 1097 compatible = "mediatek,mt8365-imgsys", "syscon"; 1098 reg = <0 0x15000000 0 0x1000>; 1099 #clock-cells = <1>; 1100 }; 1101 1102 larb2: larb@15001000 { 1103 compatible = "mediatek,mt8365-smi-larb", 1104 "mediatek,mt8186-smi-larb"; 1105 reg = <0 0x15001000 0 0x1000>; 1106 mediatek,smi = <&smi_common>; 1107 clocks = <&mmsys CLK_MM_MM_SMI_IMG>, 1108 <&camsys CLK_CAM_LARB2>; 1109 clock-names = "apb", "smi"; 1110 power-domains = <&spm MT8365_POWER_DOMAIN_CAM>; 1111 mediatek,larb-id = <2>; 1112 }; 1113 1114 vdecsys: syscon@16000000 { 1115 compatible = "mediatek,mt8365-vdecsys", "syscon"; 1116 reg = <0 0x16000000 0 0x1000>; 1117 #clock-cells = <1>; 1118 }; 1119 1120 larb3: larb@16010000 { 1121 compatible = "mediatek,mt8365-smi-larb", 1122 "mediatek,mt8186-smi-larb"; 1123 reg = <0 0x16010000 0 0x1000>; 1124 mediatek,smi = <&smi_common>; 1125 clocks = <&vdecsys CLK_VDEC_LARB1>, 1126 <&vdecsys CLK_VDEC_LARB1>; 1127 clock-names = "apb", "smi"; 1128 power-domains = <&spm MT8365_POWER_DOMAIN_VDEC>; 1129 mediatek,larb-id = <3>; 1130 }; 1131 1132 vencsys: syscon@17000000 { 1133 compatible = "mediatek,mt8365-vencsys", "syscon"; 1134 reg = <0 0x17000000 0 0x1000>; 1135 #clock-cells = <1>; 1136 }; 1137 1138 larb1: larb@17010000 { 1139 compatible = "mediatek,mt8365-smi-larb", 1140 "mediatek,mt8186-smi-larb"; 1141 reg = <0 0x17010000 0 0x1000>; 1142 mediatek,smi = <&smi_common>; 1143 clocks = <&vencsys CLK_VENC>, <&vencsys CLK_VENC>; 1144 clock-names = "apb", "smi"; 1145 power-domains = <&spm MT8365_POWER_DOMAIN_VENC>; 1146 mediatek,larb-id = <1>; 1147 }; 1148 1149 apu: syscon@19020000 { 1150 compatible = "mediatek,mt8365-apu", "syscon"; 1151 reg = <0 0x19020000 0 0x1000>; 1152 #clock-cells = <1>; 1153 }; 1154 1155 afe: audio-controller@11220000 { 1156 compatible = "mediatek,mt8365-afe-pcm"; 1157 reg = <0 0x11220000 0 0x1000>; 1158 #sound-dai-cells = <0>; 1159 clocks = <&clk26m>, 1160 <&topckgen CLK_TOP_AUDIO_SEL>, 1161 <&topckgen CLK_TOP_AUD_I2S0_M>, 1162 <&topckgen CLK_TOP_AUD_I2S1_M>, 1163 <&topckgen CLK_TOP_AUD_I2S2_M>, 1164 <&topckgen CLK_TOP_AUD_I2S3_M>, 1165 <&topckgen CLK_TOP_AUD_ENGEN1_SEL>, 1166 <&topckgen CLK_TOP_AUD_ENGEN2_SEL>, 1167 <&topckgen CLK_TOP_AUD_1_SEL>, 1168 <&topckgen CLK_TOP_AUD_2_SEL>, 1169 <&topckgen CLK_TOP_APLL_I2S0_SEL>, 1170 <&topckgen CLK_TOP_APLL_I2S1_SEL>, 1171 <&topckgen CLK_TOP_APLL_I2S2_SEL>, 1172 <&topckgen CLK_TOP_APLL_I2S3_SEL>; 1173 clock-names = "top_clk26m_clk", 1174 "top_audio_sel", 1175 "audio_i2s0_m", 1176 "audio_i2s1_m", 1177 "audio_i2s2_m", 1178 "audio_i2s3_m", 1179 "engen1", 1180 "engen2", 1181 "aud1", 1182 "aud2", 1183 "i2s0_m_sel", 1184 "i2s1_m_sel", 1185 "i2s2_m_sel", 1186 "i2s3_m_sel"; 1187 interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_LOW>; 1188 power-domains = <&spm MT8365_POWER_DOMAIN_AUDIO>; 1189 status = "disabled"; 1190 }; 1191 }; 1192 1193 timer { 1194 compatible = "arm,armv8-timer"; 1195 interrupt-parent = <&gic>; 1196 interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_LOW>, 1197 <GIC_PPI 14 IRQ_TYPE_LEVEL_LOW>, 1198 <GIC_PPI 11 IRQ_TYPE_LEVEL_LOW>, 1199 <GIC_PPI 10 IRQ_TYPE_LEVEL_LOW>; 1200 }; 1201 1202 system_clk: dummy13m { 1203 compatible = "fixed-clock"; 1204 clock-frequency = <13000000>; 1205 #clock-cells = <0>; 1206 }; 1207 1208 systimer: timer@10017000 { 1209 compatible = "mediatek,mt8365-systimer", "mediatek,mt6765-timer"; 1210 reg = <0 0x10017000 0 0x100>; 1211 interrupts = <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>; 1212 clocks = <&system_clk>; 1213 clock-names = "clk13m"; 1214 }; 1215}; 1216