1// SPDX-License-Identifier: BSD-3-Clause 2/* 3 * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. 4 */ 5 6#include <dt-bindings/clock/qcom,glymur-dispcc.h> 7#include <dt-bindings/clock/qcom,glymur-gcc.h> 8#include <dt-bindings/clock/qcom,glymur-gpucc.h> 9#include <dt-bindings/clock/qcom,glymur-tcsr.h> 10#include <dt-bindings/clock/qcom,glymur-videocc.h> 11#include <dt-bindings/clock/qcom,kaanapali-gxclkctl.h> 12#include <dt-bindings/clock/qcom,rpmh.h> 13#include <dt-bindings/dma/qcom-gpi.h> 14#include <dt-bindings/gpio/gpio.h> 15#include <dt-bindings/interconnect/qcom,icc.h> 16#include <dt-bindings/interconnect/qcom,glymur-rpmh.h> 17#include <dt-bindings/interrupt-controller/arm-gic.h> 18#include <dt-bindings/mailbox/qcom-ipcc.h> 19#include <dt-bindings/phy/phy-qcom-qmp.h> 20#include <dt-bindings/power/qcom,rpmhpd.h> 21#include <dt-bindings/power/qcom-rpmpd.h> 22#include <dt-bindings/regulator/qcom,rpmh-regulator.h> 23#include <dt-bindings/soc/qcom,rpmh-rsc.h> 24#include <dt-bindings/spmi/spmi.h> 25 26#include "glymur-ipcc.h" 27 28/ { 29 interrupt-parent = <&intc>; 30 #address-cells = <2>; 31 #size-cells = <2>; 32 33 cpus { 34 #address-cells = <2>; 35 #size-cells = <0>; 36 37 cpu0: cpu@0 { 38 device_type = "cpu"; 39 compatible = "qcom,oryon-2-2"; 40 reg = <0x0 0x0>; 41 enable-method = "psci"; 42 power-domains = <&cpu_pd0>, <&scmi_perf 0>; 43 power-domain-names = "psci", "perf"; 44 next-level-cache = <&l2_0>; 45 #cooling-cells = <2>; 46 47 l2_0: l2-cache { 48 compatible = "cache"; 49 cache-level = <2>; 50 cache-unified; 51 }; 52 }; 53 54 cpu1: cpu@100 { 55 device_type = "cpu"; 56 compatible = "qcom,oryon-2-2"; 57 reg = <0x0 0x100>; 58 enable-method = "psci"; 59 power-domains = <&cpu_pd1>, <&scmi_perf 0>; 60 power-domain-names = "psci", "perf"; 61 next-level-cache = <&l2_0>; 62 #cooling-cells = <2>; 63 }; 64 65 cpu2: cpu@200 { 66 device_type = "cpu"; 67 compatible = "qcom,oryon-2-2"; 68 reg = <0x0 0x200>; 69 enable-method = "psci"; 70 power-domains = <&cpu_pd2>, <&scmi_perf 0>; 71 power-domain-names = "psci", "perf"; 72 next-level-cache = <&l2_0>; 73 #cooling-cells = <2>; 74 }; 75 76 cpu3: cpu@300 { 77 device_type = "cpu"; 78 compatible = "qcom,oryon-2-2"; 79 reg = <0x0 0x300>; 80 enable-method = "psci"; 81 power-domains = <&cpu_pd3>, <&scmi_perf 0>; 82 power-domain-names = "psci", "perf"; 83 next-level-cache = <&l2_0>; 84 #cooling-cells = <2>; 85 }; 86 87 cpu4: cpu@400 { 88 device_type = "cpu"; 89 compatible = "qcom,oryon-2-2"; 90 reg = <0x0 0x400>; 91 enable-method = "psci"; 92 power-domains = <&cpu_pd4>, <&scmi_perf 0>; 93 power-domain-names = "psci", "perf"; 94 next-level-cache = <&l2_0>; 95 #cooling-cells = <2>; 96 }; 97 98 cpu5: cpu@500 { 99 device_type = "cpu"; 100 compatible = "qcom,oryon-2-2"; 101 reg = <0x0 0x500>; 102 enable-method = "psci"; 103 power-domains = <&cpu_pd5>, <&scmi_perf 0>; 104 power-domain-names = "psci", "perf"; 105 next-level-cache = <&l2_0>; 106 #cooling-cells = <2>; 107 }; 108 109 cpu6: cpu@10000 { 110 device_type = "cpu"; 111 compatible = "qcom,oryon-2-1"; 112 reg = <0x0 0x10000>; 113 enable-method = "psci"; 114 power-domains = <&cpu_pd6>, <&scmi_perf 1>; 115 power-domain-names = "psci", "perf"; 116 next-level-cache = <&l2_1>; 117 #cooling-cells = <2>; 118 119 l2_1: l2-cache { 120 compatible = "cache"; 121 cache-level = <2>; 122 cache-unified; 123 }; 124 }; 125 126 cpu7: cpu@10100 { 127 device_type = "cpu"; 128 compatible = "qcom,oryon-2-1"; 129 reg = <0x0 0x10100>; 130 enable-method = "psci"; 131 power-domains = <&cpu_pd7>, <&scmi_perf 1>; 132 power-domain-names = "psci", "perf"; 133 next-level-cache = <&l2_1>; 134 #cooling-cells = <2>; 135 }; 136 137 cpu8: cpu@10200 { 138 device_type = "cpu"; 139 compatible = "qcom,oryon-2-1"; 140 reg = <0x0 0x10200>; 141 enable-method = "psci"; 142 power-domains = <&cpu_pd8>, <&scmi_perf 1>; 143 power-domain-names = "psci", "perf"; 144 next-level-cache = <&l2_1>; 145 #cooling-cells = <2>; 146 }; 147 148 cpu9: cpu@10300 { 149 device_type = "cpu"; 150 compatible = "qcom,oryon-2-1"; 151 reg = <0x0 0x10300>; 152 enable-method = "psci"; 153 power-domains = <&cpu_pd9>, <&scmi_perf 1>; 154 power-domain-names = "psci", "perf"; 155 next-level-cache = <&l2_1>; 156 #cooling-cells = <2>; 157 }; 158 159 cpu10: cpu@10400 { 160 device_type = "cpu"; 161 compatible = "qcom,oryon-2-1"; 162 reg = <0x0 0x10400>; 163 enable-method = "psci"; 164 power-domains = <&cpu_pd10>, <&scmi_perf 1>; 165 power-domain-names = "psci", "perf"; 166 next-level-cache = <&l2_1>; 167 #cooling-cells = <2>; 168 }; 169 170 cpu11: cpu@10500 { 171 device_type = "cpu"; 172 compatible = "qcom,oryon-2-1"; 173 reg = <0x0 0x10500>; 174 enable-method = "psci"; 175 power-domains = <&cpu_pd11>, <&scmi_perf 1>; 176 power-domain-names = "psci", "perf"; 177 next-level-cache = <&l2_1>; 178 #cooling-cells = <2>; 179 }; 180 181 cpu12: cpu@20000 { 182 device_type = "cpu"; 183 compatible = "qcom,oryon-2-1"; 184 reg = <0x0 0x20000>; 185 enable-method = "psci"; 186 power-domains = <&cpu_pd12>, <&scmi_perf 2>; 187 power-domain-names = "psci", "perf"; 188 next-level-cache = <&l2_2>; 189 #cooling-cells = <2>; 190 191 l2_2: l2-cache { 192 compatible = "cache"; 193 cache-level = <2>; 194 cache-unified; 195 }; 196 }; 197 198 cpu13: cpu@20100 { 199 device_type = "cpu"; 200 compatible = "qcom,oryon-2-1"; 201 reg = <0x0 0x20100>; 202 enable-method = "psci"; 203 power-domains = <&cpu_pd13>, <&scmi_perf 2>; 204 power-domain-names = "psci", "perf"; 205 next-level-cache = <&l2_2>; 206 #cooling-cells = <2>; 207 }; 208 209 cpu14: cpu@20200 { 210 device_type = "cpu"; 211 compatible = "qcom,oryon-2-1"; 212 reg = <0x0 0x20200>; 213 enable-method = "psci"; 214 power-domains = <&cpu_pd14>, <&scmi_perf 2>; 215 power-domain-names = "psci", "perf"; 216 next-level-cache = <&l2_2>; 217 #cooling-cells = <2>; 218 }; 219 220 cpu15: cpu@20300 { 221 device_type = "cpu"; 222 compatible = "qcom,oryon-2-1"; 223 reg = <0x0 0x20300>; 224 enable-method = "psci"; 225 power-domains = <&cpu_pd15>, <&scmi_perf 2>; 226 power-domain-names = "psci", "perf"; 227 next-level-cache = <&l2_2>; 228 #cooling-cells = <2>; 229 }; 230 231 cpu16: cpu@20400 { 232 device_type = "cpu"; 233 compatible = "qcom,oryon-2-1"; 234 reg = <0x0 0x20400>; 235 enable-method = "psci"; 236 power-domains = <&cpu_pd16>, <&scmi_perf 2>; 237 power-domain-names = "psci", "perf"; 238 next-level-cache = <&l2_2>; 239 #cooling-cells = <2>; 240 }; 241 242 cpu17: cpu@20500 { 243 device_type = "cpu"; 244 compatible = "qcom,oryon-2-1"; 245 reg = <0x0 0x20500>; 246 enable-method = "psci"; 247 power-domains = <&cpu_pd17>, <&scmi_perf 2>; 248 power-domain-names = "psci", "perf"; 249 next-level-cache = <&l2_2>; 250 #cooling-cells = <2>; 251 }; 252 253 cpu-map { 254 cluster0 { 255 core0 { 256 cpu = <&cpu0>; 257 }; 258 259 core1 { 260 cpu = <&cpu1>; 261 }; 262 263 core2 { 264 cpu = <&cpu2>; 265 }; 266 267 core3 { 268 cpu = <&cpu3>; 269 }; 270 271 core4 { 272 cpu = <&cpu4>; 273 }; 274 275 core5 { 276 cpu = <&cpu5>; 277 }; 278 }; 279 280 cluster1 { 281 core0 { 282 cpu = <&cpu6>; 283 }; 284 285 core1 { 286 cpu = <&cpu7>; 287 }; 288 289 core2 { 290 cpu = <&cpu8>; 291 }; 292 293 core3 { 294 cpu = <&cpu9>; 295 }; 296 297 core4 { 298 cpu = <&cpu10>; 299 }; 300 301 core5 { 302 cpu = <&cpu11>; 303 }; 304 }; 305 306 cpu_map_cluster2: cluster2 { 307 core0 { 308 cpu = <&cpu12>; 309 }; 310 311 core1 { 312 cpu = <&cpu13>; 313 }; 314 315 core2 { 316 cpu = <&cpu14>; 317 }; 318 319 core3 { 320 cpu = <&cpu15>; 321 }; 322 323 core4 { 324 cpu = <&cpu16>; 325 }; 326 327 core5 { 328 cpu = <&cpu17>; 329 }; 330 }; 331 }; 332 333 idle-states { 334 entry-method = "psci"; 335 336 cpu_c4: cpu-sleep-0 { 337 compatible = "arm,idle-state"; 338 idle-state-name = "ret"; 339 arm,psci-suspend-param = <0x00000004>; 340 entry-latency-us = <180>; 341 exit-latency-us = <320>; 342 min-residency-us = <1000>; 343 }; 344 }; 345 346 domain-idle-states { 347 cluster_cl5: cluster-sleep-0 { 348 compatible = "domain-idle-state"; 349 arm,psci-suspend-param = <0x01000054>; 350 entry-latency-us = <2000>; 351 exit-latency-us = <2000>; 352 min-residency-us = <9000>; 353 }; 354 355 domain_ss3: domain-sleep-0 { 356 compatible = "domain-idle-state"; 357 arm,psci-suspend-param = <0x0200c354>; 358 entry-latency-us = <2800>; 359 exit-latency-us = <4400>; 360 min-residency-us = <10150>; 361 }; 362 }; 363 }; 364 365 dummy-sink { 366 compatible = "arm,coresight-dummy-sink"; 367 368 in-ports { 369 port { 370 eud_in: endpoint { 371 remote-endpoint = <&swao_rep_out1>; 372 }; 373 }; 374 }; 375 }; 376 377 firmware { 378 scm: scm { 379 compatible = "qcom,scm-glymur", "qcom,scm"; 380 qcom,dload-mode = <&tcsr 0x4000>; 381 interconnects = <&aggre2_noc MASTER_CRYPTO QCOM_ICC_TAG_ALWAYS 382 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 383 }; 384 385 scmi { 386 compatible = "arm,scmi"; 387 mboxes = <&pdp0_mbox 0>, <&pdp0_mbox 1>; 388 mbox-names = "tx", "rx"; 389 shmem = <&cpu_scp_lpri1>, <&cpu_scp_lpri0>; 390 391 #address-cells = <1>; 392 #size-cells = <0>; 393 394 scmi_perf: protocol@13 { 395 reg = <0x13>; 396 #power-domain-cells = <1>; 397 }; 398 }; 399 }; 400 401 clk_virt: interconnect-0 { 402 compatible = "qcom,glymur-clk-virt"; 403 #interconnect-cells = <2>; 404 qcom,bcm-voters = <&apps_bcm_voter>; 405 }; 406 407 mc_virt: interconnect-1 { 408 compatible = "qcom,glymur-mc-virt"; 409 #interconnect-cells = <2>; 410 qcom,bcm-voters = <&apps_bcm_voter>; 411 }; 412 413 pmu { 414 compatible = "arm,armv8-pmuv3"; 415 interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_LOW>; 416 }; 417 418 psci { 419 compatible = "arm,psci-1.0"; 420 method = "smc"; 421 422 cpu_pd0: power-domain-cpu0 { 423 #power-domain-cells = <0>; 424 power-domains = <&cluster0_pd>; 425 domain-idle-states = <&cpu_c4>; 426 }; 427 428 cpu_pd1: power-domain-cpu1 { 429 #power-domain-cells = <0>; 430 power-domains = <&cluster0_pd>; 431 domain-idle-states = <&cpu_c4>; 432 }; 433 434 cpu_pd2: power-domain-cpu2 { 435 #power-domain-cells = <0>; 436 power-domains = <&cluster0_pd>; 437 domain-idle-states = <&cpu_c4>; 438 }; 439 440 cpu_pd3: power-domain-cpu3 { 441 #power-domain-cells = <0>; 442 power-domains = <&cluster0_pd>; 443 domain-idle-states = <&cpu_c4>; 444 }; 445 446 cpu_pd4: power-domain-cpu4 { 447 #power-domain-cells = <0>; 448 power-domains = <&cluster0_pd>; 449 domain-idle-states = <&cpu_c4>; 450 }; 451 452 cpu_pd5: power-domain-cpu5 { 453 #power-domain-cells = <0>; 454 power-domains = <&cluster0_pd>; 455 domain-idle-states = <&cpu_c4>; 456 }; 457 458 cpu_pd6: power-domain-cpu6 { 459 #power-domain-cells = <0>; 460 power-domains = <&cluster1_pd>; 461 domain-idle-states = <&cpu_c4>; 462 }; 463 464 cpu_pd7: power-domain-cpu7 { 465 #power-domain-cells = <0>; 466 power-domains = <&cluster1_pd>; 467 domain-idle-states = <&cpu_c4>; 468 }; 469 470 cpu_pd8: power-domain-cpu8 { 471 #power-domain-cells = <0>; 472 power-domains = <&cluster1_pd>; 473 domain-idle-states = <&cpu_c4>; 474 }; 475 476 cpu_pd9: power-domain-cpu9 { 477 #power-domain-cells = <0>; 478 power-domains = <&cluster1_pd>; 479 domain-idle-states = <&cpu_c4>; 480 }; 481 482 cpu_pd10: power-domain-cpu10 { 483 #power-domain-cells = <0>; 484 power-domains = <&cluster1_pd>; 485 domain-idle-states = <&cpu_c4>; 486 }; 487 488 cpu_pd11: power-domain-cpu11 { 489 #power-domain-cells = <0>; 490 power-domains = <&cluster1_pd>; 491 domain-idle-states = <&cpu_c4>; 492 }; 493 494 cpu_pd12: power-domain-cpu12 { 495 #power-domain-cells = <0>; 496 power-domains = <&cluster2_pd>; 497 domain-idle-states = <&cpu_c4>; 498 }; 499 500 cpu_pd13: power-domain-cpu13 { 501 #power-domain-cells = <0>; 502 power-domains = <&cluster2_pd>; 503 domain-idle-states = <&cpu_c4>; 504 }; 505 506 cpu_pd14: power-domain-cpu14 { 507 #power-domain-cells = <0>; 508 power-domains = <&cluster2_pd>; 509 domain-idle-states = <&cpu_c4>; 510 }; 511 512 cpu_pd15: power-domain-cpu15 { 513 #power-domain-cells = <0>; 514 power-domains = <&cluster2_pd>; 515 domain-idle-states = <&cpu_c4>; 516 }; 517 518 cpu_pd16: power-domain-cpu16 { 519 #power-domain-cells = <0>; 520 power-domains = <&cluster2_pd>; 521 domain-idle-states = <&cpu_c4>; 522 }; 523 524 cpu_pd17: power-domain-cpu17 { 525 #power-domain-cells = <0>; 526 power-domains = <&cluster2_pd>; 527 domain-idle-states = <&cpu_c4>; 528 }; 529 530 cluster0_pd: power-domain-cpu-cluster0 { 531 #power-domain-cells = <0>; 532 power-domains = <&system_pd>; 533 domain-idle-states = <&cluster_cl5>; 534 }; 535 536 cluster1_pd: power-domain-cpu-cluster1 { 537 #power-domain-cells = <0>; 538 power-domains = <&system_pd>; 539 domain-idle-states = <&cluster_cl5>; 540 }; 541 542 cluster2_pd: power-domain-cpu-cluster2 { 543 #power-domain-cells = <0>; 544 power-domains = <&system_pd>; 545 domain-idle-states = <&cluster_cl5>; 546 }; 547 548 system_pd: power-domain-system { 549 #power-domain-cells = <0>; 550 domain-idle-states = <&domain_ss3>; 551 }; 552 }; 553 554 reserved-memory { 555 #address-cells = <2>; 556 #size-cells = <2>; 557 ranges; 558 559 pdp_mem: pdp@81400000 { 560 reg = <0x0 0x81400000 0x0 0x100000>; 561 no-map; 562 }; 563 564 aop_cmd_db_mem: aop-cmd-db@81c60000 { 565 compatible = "qcom,cmd-db"; 566 reg = <0x0 0x81c60000 0x0 0x20000>; 567 no-map; 568 }; 569 570 pdp_ns_shared_mem: pdp-ns-shared@81e00000 { 571 reg = <0x0 0x81e00000 0x0 0x200000>; 572 no-map; 573 }; 574 575 oobdaretag_mem: oobdaretag@86e10000 { 576 reg = <0x0 0x86e10000 0x0 0x360000>; 577 no-map; 578 }; 579 580 oob_secure_mem: oob-secure@87170000 { 581 reg = <0x0 0x87170000 0x0 0xbc0000>; 582 no-map; 583 }; 584 585 oobdtbqc_mem: oobdtbqc@87d30000 { 586 reg = <0x0 0x87d30000 0x0 0x20000>; 587 no-map; 588 }; 589 590 oobdtboem_mem: oobdtboem@87d50000 { 591 reg = <0x0 0x87d50000 0x0 0x20000>; 592 no-map; 593 }; 594 595 oob_nonsecure_mem: oob-nonsecure@87e00000 { 596 reg = <0x0 0x87e00000 0x0 0xc00000>; 597 no-map; 598 }; 599 600 spss_region_mem: spss@88a00000 { 601 reg = <0x0 0x88a00000 0x0 0x400000>; 602 no-map; 603 }; 604 605 soccpdtb_mem: soccpdtb@892e0000 { 606 reg = <0x0 0x892e0000 0x0 0x20000>; 607 no-map; 608 }; 609 610 soccp_mem: soccp@89300000 { 611 reg = <0x0 0x89300000 0x0 0x400000>; 612 no-map; 613 }; 614 615 cvp_mem: cvp@89700000 { 616 reg = <0x0 0x89700000 0x0 0x700000>; 617 no-map; 618 }; 619 620 adspslpi_mem: adspslpi@89e00000 { 621 reg = <0x0 0x89e00000 0x0 0x3a00000>; 622 no-map; 623 }; 624 625 q6_adsp_dtb_mem: q6-adsp-dtb@8d800000 { 626 reg = <0x0 0x8d800000 0x0 0x80000>; 627 no-map; 628 }; 629 630 cdsp_mem: cdsp@8d900000 { 631 reg = <0x0 0x8d900000 0x0 0x4000000>; 632 no-map; 633 }; 634 635 q6_cdsp_dtb_mem: q6-cdsp-dtb@91900000 { 636 reg = <0x0 0x91900000 0x0 0x80000>; 637 no-map; 638 }; 639 640 gpu_microcode_mem: gpu-microcode@919fe000 { 641 reg = <0x0 0x919fe000 0x0 0x2000>; 642 no-map; 643 }; 644 645 camera_mem: camera@91a00000 { 646 reg = <0x0 0x91a00000 0x0 0x800000>; 647 no-map; 648 }; 649 650 av1_encoder_mem: av1-encoder@92200000 { 651 reg = <0x0 0x92200000 0x0 0x700000>; 652 no-map; 653 }; 654 655 video_mem: video@92900000 { 656 reg = <0x0 0x92900000 0x0 0xc00000>; 657 no-map; 658 }; 659 660 smem_mem: smem@ffe00000 { 661 compatible = "qcom,smem"; 662 reg = <0x0 0xffe00000 0x0 0x200000>; 663 hwlocks = <&tcsr_mutex 3>; 664 no-map; 665 }; 666 }; 667 668 smp2p-adsp { 669 compatible = "qcom,smp2p"; 670 671 interrupts-extended = <&ipcc IPCC_MPROC_LPASS 672 IPCC_MPROC_SIGNAL_SMP2P 673 IRQ_TYPE_EDGE_RISING>; 674 675 mboxes = <&ipcc IPCC_MPROC_LPASS IPCC_MPROC_SIGNAL_SMP2P>; 676 677 qcom,smem = <443>, <429>; 678 qcom,local-pid = <0>; 679 qcom,remote-pid = <2>; 680 681 smp2p_adsp_out: master-kernel { 682 qcom,entry-name = "master-kernel"; 683 #qcom,smem-state-cells = <1>; 684 }; 685 686 smp2p_adsp_in: slave-kernel { 687 qcom,entry-name = "slave-kernel"; 688 interrupt-controller; 689 #interrupt-cells = <2>; 690 }; 691 }; 692 693 smp2p-cdsp { 694 compatible = "qcom,smp2p"; 695 696 interrupts-extended = <&ipcc IPCC_MPROC_CDSP 697 IPCC_MPROC_SIGNAL_SMP2P 698 IRQ_TYPE_EDGE_RISING>; 699 700 mboxes = <&ipcc IPCC_MPROC_CDSP IPCC_MPROC_SIGNAL_SMP2P>; 701 702 qcom,smem = <94>, <432>; 703 qcom,local-pid = <0>; 704 qcom,remote-pid = <5>; 705 706 smp2p_cdsp_out: master-kernel { 707 qcom,entry-name = "master-kernel"; 708 #qcom,smem-state-cells = <1>; 709 }; 710 711 smp2p_cdsp_in: slave-kernel { 712 qcom,entry-name = "slave-kernel"; 713 interrupt-controller; 714 #interrupt-cells = <2>; 715 }; 716 }; 717 718 smp2p-soccp { 719 compatible = "qcom,smp2p"; 720 721 interrupts-extended = <&ipcc IPCC_MPROC_SOCCP 722 IPCC_MPROC_SIGNAL_SMP2P 723 IRQ_TYPE_EDGE_RISING>; 724 725 mboxes = <&ipcc IPCC_MPROC_SOCCP 726 IPCC_MPROC_SIGNAL_SMP2P>; 727 728 qcom,smem = <617>, <616>; 729 qcom,local-pid = <0>; 730 qcom,remote-pid = <19>; 731 732 soccp_smp2p_out: master-kernel { 733 qcom,entry-name = "master-kernel"; 734 #qcom,smem-state-cells = <1>; 735 }; 736 737 soccp_smp2p_in: slave-kernel { 738 qcom,entry-name = "slave-kernel"; 739 interrupt-controller; 740 #interrupt-cells = <2>; 741 }; 742 }; 743 744 soc: soc@0 { 745 compatible = "simple-bus"; 746 #address-cells = <2>; 747 #size-cells = <2>; 748 ranges = <0x0 0x0 0x0 0x0 0x100 0x0>; 749 dma-ranges = <0x0 0x0 0x0 0x0 0x100 0x0>; 750 751 gcc: clock-controller@100000 { 752 compatible = "qcom,glymur-gcc"; 753 reg = <0x0 0x00100000 0x0 0x1f9000>; 754 clocks = <&rpmhcc RPMH_CXO_CLK>, /* Board XO source */ 755 <&rpmhcc RPMH_CXO_CLK_A>, /* Board XO_A source */ 756 <&sleep_clk>, /* Sleep */ 757 <0>, /* USB 0 Phy DP0 GMUX */ 758 <0>, /* USB 0 Phy DP1 GMUX */ 759 <0>, /* USB 0 Phy PCIE PIPEGMUX */ 760 <0>, /* USB 0 Phy PIPEGMUX */ 761 <0>, /* USB 0 Phy SYS PCIE PIPEGMUX */ 762 <0>, /* USB 1 Phy DP0 GMUX 2 */ 763 <0>, /* USB 1 Phy DP1 GMUX 2 */ 764 <0>, /* USB 1 Phy PCIE PIPEGMUX */ 765 <0>, /* USB 1 Phy PIPEGMUX */ 766 <0>, /* USB 1 Phy SYS PCIE PIPEGMUX */ 767 <0>, /* USB 2 Phy DP0 GMUX 2 */ 768 <0>, /* USB 2 Phy DP1 GMUX 2 */ 769 <0>, /* USB 2 Phy PCIE PIPEGMUX */ 770 <0>, /* USB 2 Phy PIPEGMUX */ 771 <0>, /* USB 2 Phy SYS PCIE PIPEGMUX */ 772 <0>, /* PCIe 3a */ 773 <&pcie3b_phy>, /* PCIe 3b */ 774 <&pcie4_phy>, /* PCIe 4 */ 775 <&pcie5_phy>, /* PCIe 5 */ 776 <&pcie6_phy>, /* PCIe 6 */ 777 <0>, /* QUSB4 0 PHY RX 0 */ 778 <0>, /* QUSB4 0 PHY RX 1 */ 779 <0>, /* QUSB4 1 PHY RX 0 */ 780 <0>, /* QUSB4 1 PHY RX 1 */ 781 <0>, /* QUSB4 2 PHY RX 0 */ 782 <0>, /* QUSB4 2 PHY RX 1 */ 783 <0>, /* UFS PHY RX Symbol 0 */ 784 <0>, /* UFS PHY RX Symbol 1 */ 785 <0>, /* UFS PHY TX Symbol 0 */ 786 <&usb_0_qmpphy QMP_USB43DP_USB3_PIPE_CLK>, 787 <&usb_1_qmpphy QMP_USB43DP_USB3_PIPE_CLK>, 788 <&usb_2_qmpphy QMP_USB43DP_USB3_PIPE_CLK>, 789 <&usb_mp_qmpphy0 QMP_USB43DP_USB3_PIPE_CLK>, 790 <&usb_mp_qmpphy1 QMP_USB43DP_USB3_PIPE_CLK>, 791 <0>, /* USB4 PHY 0 pcie pipe */ 792 <0>, /* USB4 PHY 0 Max pipe */ 793 <0>, /* USB4 PHY 1 pcie pipe */ 794 <0>, /* USB4 PHY 1 Max pipe */ 795 <0>, /* USB4 PHY 2 pcie */ 796 <0>; /* USB4 PHY 2 Max */ 797 #clock-cells = <1>; 798 #reset-cells = <1>; 799 #power-domain-cells = <1>; 800 }; 801 802 gpi_dma2: dma-controller@800000 { 803 compatible = "qcom,glymur-gpi-dma", "qcom,sm6350-gpi-dma"; 804 reg = <0x0 0x00800000 0x0 0x60000>; 805 interrupts = <GIC_SPI 588 IRQ_TYPE_LEVEL_HIGH>, 806 <GIC_SPI 589 IRQ_TYPE_LEVEL_HIGH>, 807 <GIC_SPI 590 IRQ_TYPE_LEVEL_HIGH>, 808 <GIC_SPI 591 IRQ_TYPE_LEVEL_HIGH>, 809 <GIC_SPI 592 IRQ_TYPE_LEVEL_HIGH>, 810 <GIC_SPI 593 IRQ_TYPE_LEVEL_HIGH>, 811 <GIC_SPI 594 IRQ_TYPE_LEVEL_HIGH>, 812 <GIC_SPI 595 IRQ_TYPE_LEVEL_HIGH>, 813 <GIC_SPI 596 IRQ_TYPE_LEVEL_HIGH>, 814 <GIC_SPI 597 IRQ_TYPE_LEVEL_HIGH>, 815 <GIC_SPI 598 IRQ_TYPE_LEVEL_HIGH>, 816 <GIC_SPI 599 IRQ_TYPE_LEVEL_HIGH>, 817 <GIC_ESPI 129 IRQ_TYPE_LEVEL_HIGH>, 818 <GIC_ESPI 130 IRQ_TYPE_LEVEL_HIGH>, 819 <GIC_ESPI 131 IRQ_TYPE_LEVEL_HIGH>, 820 <GIC_ESPI 132 IRQ_TYPE_LEVEL_HIGH>; 821 dma-channels = <16>; 822 dma-channel-mask = <0x3f>; 823 #dma-cells = <3>; 824 iommus = <&apps_smmu 0xd76 0x0>; 825 }; 826 827 qupv3_2: geniqup@8c0000 { 828 compatible = "qcom,geni-se-qup"; 829 reg = <0x0 0x008c0000 0x0 0x3000>; 830 clocks = <&gcc GCC_QUPV3_WRAP_2_M_AHB_CLK>, 831 <&gcc GCC_QUPV3_WRAP_2_S_AHB_CLK>; 832 clock-names = "m-ahb", 833 "s-ahb"; 834 iommus = <&apps_smmu 0xd63 0x0>; 835 #address-cells = <2>; 836 #size-cells = <2>; 837 ranges; 838 839 i2c16: i2c@880000 { 840 compatible = "qcom,geni-i2c"; 841 reg = <0x0 0x00880000 0x0 0x4000>; 842 interrupts = <GIC_SPI 373 IRQ_TYPE_LEVEL_HIGH>; 843 clocks = <&gcc GCC_QUPV3_WRAP2_S0_CLK>; 844 clock-names = "se"; 845 interconnects = <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS 846 &clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>, 847 <&hsc_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 848 &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ALWAYS>, 849 <&aggre3_noc MASTER_QUP_2 QCOM_ICC_TAG_ALWAYS 850 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 851 interconnect-names = "qup-core", 852 "qup-config", 853 "qup-memory"; 854 dmas = <&gpi_dma2 0 0 QCOM_GPI_I2C>, 855 <&gpi_dma2 1 0 QCOM_GPI_I2C>; 856 dma-names = "tx", 857 "rx"; 858 pinctrl-0 = <&qup_i2c16_data_clk>; 859 pinctrl-names = "default"; 860 #address-cells = <1>; 861 #size-cells = <0>; 862 863 status = "disabled"; 864 }; 865 866 spi16: spi@880000 { 867 compatible = "qcom,geni-spi"; 868 reg = <0x0 0x00880000 0x0 0x4000>; 869 interrupts = <GIC_SPI 373 IRQ_TYPE_LEVEL_HIGH>; 870 clocks = <&gcc GCC_QUPV3_WRAP2_S0_CLK>; 871 clock-names = "se"; 872 interconnects = <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS 873 &clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>, 874 <&hsc_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 875 &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ALWAYS>, 876 <&aggre3_noc MASTER_QUP_2 QCOM_ICC_TAG_ALWAYS 877 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 878 interconnect-names = "qup-core", 879 "qup-config", 880 "qup-memory"; 881 dmas = <&gpi_dma2 0 0 QCOM_GPI_SPI>, 882 <&gpi_dma2 1 0 QCOM_GPI_SPI>; 883 dma-names = "tx", 884 "rx"; 885 pinctrl-0 = <&qup_spi16_data_clk>, <&qup_spi16_cs>; 886 pinctrl-names = "default"; 887 #address-cells = <1>; 888 #size-cells = <0>; 889 890 status = "disabled"; 891 }; 892 893 i2c17: i2c@884000 { 894 compatible = "qcom,geni-i2c"; 895 reg = <0x0 0x00884000 0x0 0x4000>; 896 interrupts = <GIC_SPI 583 IRQ_TYPE_LEVEL_HIGH>; 897 clocks = <&gcc GCC_QUPV3_WRAP2_S1_CLK>; 898 clock-names = "se"; 899 interconnects = <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS 900 &clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>, 901 <&hsc_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 902 &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ALWAYS>, 903 <&aggre3_noc MASTER_QUP_2 QCOM_ICC_TAG_ALWAYS 904 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 905 interconnect-names = "qup-core", 906 "qup-config", 907 "qup-memory"; 908 dmas = <&gpi_dma2 0 1 QCOM_GPI_I2C>, 909 <&gpi_dma2 1 1 QCOM_GPI_I2C>; 910 dma-names = "tx", 911 "rx"; 912 pinctrl-0 = <&qup_i2c17_data_clk>; 913 pinctrl-names = "default"; 914 #address-cells = <1>; 915 #size-cells = <0>; 916 917 status = "disabled"; 918 }; 919 920 spi17: spi@884000 { 921 compatible = "qcom,geni-spi"; 922 reg = <0x0 0x00884000 0x0 0x4000>; 923 interrupts = <GIC_SPI 583 IRQ_TYPE_LEVEL_HIGH>; 924 clocks = <&gcc GCC_QUPV3_WRAP2_S1_CLK>; 925 clock-names = "se"; 926 interconnects = <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS 927 &clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>, 928 <&hsc_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 929 &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ALWAYS>, 930 <&aggre3_noc MASTER_QUP_2 QCOM_ICC_TAG_ALWAYS 931 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 932 interconnect-names = "qup-core", 933 "qup-config", 934 "qup-memory"; 935 dmas = <&gpi_dma2 0 1 QCOM_GPI_SPI>, 936 <&gpi_dma2 1 1 QCOM_GPI_SPI>; 937 dma-names = "tx", 938 "rx"; 939 pinctrl-0 = <&qup_spi17_data_clk>, <&qup_spi17_cs>; 940 pinctrl-names = "default"; 941 #address-cells = <1>; 942 #size-cells = <0>; 943 944 status = "disabled"; 945 }; 946 947 i2c18: i2c@888000 { 948 compatible = "qcom,geni-i2c"; 949 reg = <0x0 0x00888000 0x0 0x4000>; 950 interrupts = <GIC_SPI 584 IRQ_TYPE_LEVEL_HIGH>; 951 clocks = <&gcc GCC_QUPV3_WRAP2_S2_CLK>; 952 clock-names = "se"; 953 interconnects = <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS 954 &clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>, 955 <&hsc_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 956 &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ALWAYS>, 957 <&aggre3_noc MASTER_QUP_2 QCOM_ICC_TAG_ALWAYS 958 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 959 interconnect-names = "qup-core", 960 "qup-config", 961 "qup-memory"; 962 dmas = <&gpi_dma2 0 2 QCOM_GPI_I2C>, 963 <&gpi_dma2 1 2 QCOM_GPI_I2C>; 964 dma-names = "tx", 965 "rx"; 966 pinctrl-0 = <&qup_i2c18_data_clk>; 967 pinctrl-names = "default"; 968 #address-cells = <1>; 969 #size-cells = <0>; 970 971 status = "disabled"; 972 }; 973 974 spi18: spi@888000 { 975 compatible = "qcom,geni-spi"; 976 reg = <0x0 0x00888000 0x0 0x4000>; 977 interrupts = <GIC_SPI 584 IRQ_TYPE_LEVEL_HIGH>; 978 clocks = <&gcc GCC_QUPV3_WRAP2_S2_CLK>; 979 clock-names = "se"; 980 interconnects = <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS 981 &clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>, 982 <&hsc_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 983 &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ALWAYS>, 984 <&aggre3_noc MASTER_QUP_2 QCOM_ICC_TAG_ALWAYS 985 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 986 interconnect-names = "qup-core", 987 "qup-config", 988 "qup-memory"; 989 dmas = <&gpi_dma2 0 2 QCOM_GPI_SPI>, 990 <&gpi_dma2 1 2 QCOM_GPI_SPI>; 991 dma-names = "tx", 992 "rx"; 993 pinctrl-0 = <&qup_spi18_data_clk>, <&qup_spi18_cs>; 994 pinctrl-names = "default"; 995 #address-cells = <1>; 996 #size-cells = <0>; 997 998 status = "disabled"; 999 }; 1000 1001 i2c19: i2c@88c000 { 1002 compatible = "qcom,geni-i2c"; 1003 reg = <0x0 0x0088c000 0x0 0x4000>; 1004 interrupts = <GIC_SPI 585 IRQ_TYPE_LEVEL_HIGH>; 1005 clocks = <&gcc GCC_QUPV3_WRAP2_S3_CLK>; 1006 clock-names = "se"; 1007 interconnects = <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS 1008 &clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>, 1009 <&hsc_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 1010 &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ALWAYS>, 1011 <&aggre3_noc MASTER_QUP_2 QCOM_ICC_TAG_ALWAYS 1012 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 1013 interconnect-names = "qup-core", 1014 "qup-config", 1015 "qup-memory"; 1016 dmas = <&gpi_dma2 0 3 QCOM_GPI_I2C>, 1017 <&gpi_dma2 1 3 QCOM_GPI_I2C>; 1018 dma-names = "tx", 1019 "rx"; 1020 pinctrl-0 = <&qup_i2c19_data_clk>; 1021 pinctrl-names = "default"; 1022 #address-cells = <1>; 1023 #size-cells = <0>; 1024 1025 status = "disabled"; 1026 }; 1027 1028 spi19: spi@88c000 { 1029 compatible = "qcom,geni-spi"; 1030 reg = <0x0 0x0088c000 0x0 0x4000>; 1031 interrupts = <GIC_SPI 585 IRQ_TYPE_LEVEL_HIGH>; 1032 clocks = <&gcc GCC_QUPV3_WRAP2_S3_CLK>; 1033 clock-names = "se"; 1034 interconnects = <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS 1035 &clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>, 1036 <&hsc_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 1037 &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ALWAYS>, 1038 <&aggre3_noc MASTER_QUP_2 QCOM_ICC_TAG_ALWAYS 1039 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 1040 interconnect-names = "qup-core", 1041 "qup-config", 1042 "qup-memory"; 1043 dmas = <&gpi_dma2 0 3 QCOM_GPI_SPI>, 1044 <&gpi_dma2 1 3 QCOM_GPI_SPI>; 1045 dma-names = "tx", 1046 "rx"; 1047 pinctrl-0 = <&qup_spi19_data_clk>, <&qup_spi19_cs>; 1048 pinctrl-names = "default"; 1049 #address-cells = <1>; 1050 #size-cells = <0>; 1051 1052 status = "disabled"; 1053 }; 1054 1055 uart19: serial@88c000 { 1056 compatible = "qcom,geni-uart"; 1057 reg = <0x0 0x0088c000 0x0 0x4000>; 1058 interrupts = <GIC_SPI 585 IRQ_TYPE_LEVEL_HIGH>; 1059 clocks = <&gcc GCC_QUPV3_WRAP2_S3_CLK>; 1060 clock-names = "se"; 1061 interconnects = <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS 1062 &clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>, 1063 <&hsc_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 1064 &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ALWAYS>; 1065 interconnect-names = "qup-core", 1066 "qup-config"; 1067 pinctrl-0 = <&qup_uart19_default>; 1068 pinctrl-names = "default"; 1069 1070 status = "disabled"; 1071 }; 1072 1073 i2c20: i2c@890000 { 1074 compatible = "qcom,geni-i2c"; 1075 reg = <0x0 0x00890000 0x0 0x4000>; 1076 interrupts = <GIC_SPI 586 IRQ_TYPE_LEVEL_HIGH>; 1077 clocks = <&gcc GCC_QUPV3_WRAP2_S4_CLK>; 1078 clock-names = "se"; 1079 interconnects = <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS 1080 &clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>, 1081 <&hsc_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 1082 &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ALWAYS>, 1083 <&aggre3_noc MASTER_QUP_2 QCOM_ICC_TAG_ALWAYS 1084 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 1085 interconnect-names = "qup-core", 1086 "qup-config", 1087 "qup-memory"; 1088 dmas = <&gpi_dma2 0 4 QCOM_GPI_I2C>, 1089 <&gpi_dma2 1 4 QCOM_GPI_I2C>; 1090 dma-names = "tx", 1091 "rx"; 1092 pinctrl-0 = <&qup_i2c20_data_clk>; 1093 pinctrl-names = "default"; 1094 #address-cells = <1>; 1095 #size-cells = <0>; 1096 1097 status = "disabled"; 1098 }; 1099 1100 spi20: spi@890000 { 1101 compatible = "qcom,geni-spi"; 1102 reg = <0x0 0x00890000 0x0 0x4000>; 1103 interrupts = <GIC_SPI 586 IRQ_TYPE_LEVEL_HIGH>; 1104 clocks = <&gcc GCC_QUPV3_WRAP2_S4_CLK>; 1105 clock-names = "se"; 1106 interconnects = <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS 1107 &clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>, 1108 <&hsc_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 1109 &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ALWAYS>, 1110 <&aggre3_noc MASTER_QUP_2 QCOM_ICC_TAG_ALWAYS 1111 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 1112 interconnect-names = "qup-core", 1113 "qup-config", 1114 "qup-memory"; 1115 dmas = <&gpi_dma2 0 4 QCOM_GPI_SPI>, 1116 <&gpi_dma2 1 4 QCOM_GPI_SPI>; 1117 dma-names = "tx", 1118 "rx"; 1119 pinctrl-0 = <&qup_spi20_data_clk>, <&qup_spi20_cs>; 1120 pinctrl-names = "default"; 1121 #address-cells = <1>; 1122 #size-cells = <0>; 1123 1124 status = "disabled"; 1125 }; 1126 1127 i2c21: i2c@894000 { 1128 compatible = "qcom,geni-i2c"; 1129 reg = <0x0 0x00894000 0x0 0x4000>; 1130 interrupts = <GIC_SPI 587 IRQ_TYPE_LEVEL_HIGH>; 1131 clocks = <&gcc GCC_QUPV3_WRAP2_S5_CLK>; 1132 clock-names = "se"; 1133 interconnects = <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS 1134 &clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>, 1135 <&hsc_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 1136 &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ALWAYS>, 1137 <&aggre3_noc MASTER_QUP_2 QCOM_ICC_TAG_ALWAYS 1138 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 1139 interconnect-names = "qup-core", 1140 "qup-config", 1141 "qup-memory"; 1142 dmas = <&gpi_dma2 0 5 QCOM_GPI_I2C>, 1143 <&gpi_dma2 1 5 QCOM_GPI_I2C>; 1144 dma-names = "tx", 1145 "rx"; 1146 pinctrl-0 = <&qup_i2c21_data_clk>; 1147 pinctrl-names = "default"; 1148 #address-cells = <1>; 1149 #size-cells = <0>; 1150 1151 status = "disabled"; 1152 }; 1153 1154 spi21: spi@894000 { 1155 compatible = "qcom,geni-spi"; 1156 reg = <0x0 0x00894000 0x0 0x4000>; 1157 interrupts = <GIC_SPI 587 IRQ_TYPE_LEVEL_HIGH>; 1158 clocks = <&gcc GCC_QUPV3_WRAP2_S5_CLK>; 1159 clock-names = "se"; 1160 interconnects = <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS 1161 &clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>, 1162 <&hsc_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 1163 &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ALWAYS>, 1164 <&aggre3_noc MASTER_QUP_2 QCOM_ICC_TAG_ALWAYS 1165 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 1166 interconnect-names = "qup-core", 1167 "qup-config", 1168 "qup-memory"; 1169 dmas = <&gpi_dma2 0 5 QCOM_GPI_SPI>, 1170 <&gpi_dma2 1 5 QCOM_GPI_SPI>; 1171 dma-names = "tx", 1172 "rx"; 1173 pinctrl-0 = <&qup_spi21_data_clk>, <&qup_spi21_cs>; 1174 pinctrl-names = "default"; 1175 #address-cells = <1>; 1176 #size-cells = <0>; 1177 1178 status = "disabled"; 1179 }; 1180 1181 uart21: serial@894000 { 1182 compatible = "qcom,geni-debug-uart"; 1183 reg = <0x0 0x00894000 0x0 0x4000>; 1184 interrupts = <GIC_SPI 587 IRQ_TYPE_LEVEL_HIGH>; 1185 clocks = <&gcc GCC_QUPV3_WRAP2_S5_CLK>; 1186 clock-names = "se"; 1187 interconnects = <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS 1188 &clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>, 1189 <&hsc_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 1190 &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ALWAYS>; 1191 interconnect-names = "qup-core", 1192 "qup-config"; 1193 pinctrl-0 = <&qup_uart21_default>; 1194 pinctrl-names = "default"; 1195 }; 1196 1197 i2c22: i2c@898000 { 1198 compatible = "qcom,geni-i2c"; 1199 reg = <0x0 0x00898000 0x0 0x4000>; 1200 interrupts = <GIC_SPI 461 IRQ_TYPE_LEVEL_HIGH>; 1201 clocks = <&gcc GCC_QUPV3_WRAP2_S6_CLK>; 1202 clock-names = "se"; 1203 interconnects = <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS 1204 &clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>, 1205 <&hsc_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 1206 &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ALWAYS>, 1207 <&aggre3_noc MASTER_QUP_2 QCOM_ICC_TAG_ALWAYS 1208 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 1209 interconnect-names = "qup-core", 1210 "qup-config", 1211 "qup-memory"; 1212 dmas = <&gpi_dma2 0 6 QCOM_GPI_I2C>, 1213 <&gpi_dma2 1 6 QCOM_GPI_I2C>; 1214 dma-names = "tx", 1215 "rx"; 1216 pinctrl-0 = <&qup_i2c22_data_clk>; 1217 pinctrl-names = "default"; 1218 #address-cells = <1>; 1219 #size-cells = <0>; 1220 1221 status = "disabled"; 1222 }; 1223 1224 spi22: spi@898000 { 1225 compatible = "qcom,geni-spi"; 1226 reg = <0x0 0x00898000 0x0 0x4000>; 1227 interrupts = <GIC_SPI 461 IRQ_TYPE_LEVEL_HIGH>; 1228 clocks = <&gcc GCC_QUPV3_WRAP2_S6_CLK>; 1229 clock-names = "se"; 1230 interconnects = <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS 1231 &clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>, 1232 <&hsc_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 1233 &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ALWAYS>, 1234 <&aggre3_noc MASTER_QUP_2 QCOM_ICC_TAG_ALWAYS 1235 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 1236 interconnect-names = "qup-core", 1237 "qup-config", 1238 "qup-memory"; 1239 dmas = <&gpi_dma2 0 6 QCOM_GPI_SPI>, 1240 <&gpi_dma2 1 6 QCOM_GPI_SPI>; 1241 dma-names = "tx", 1242 "rx"; 1243 pinctrl-0 = <&qup_spi22_data_clk>, <&qup_spi22_cs>; 1244 pinctrl-names = "default"; 1245 #address-cells = <1>; 1246 #size-cells = <0>; 1247 1248 status = "disabled"; 1249 }; 1250 1251 uart22: serial@898000 { 1252 compatible = "qcom,geni-uart"; 1253 reg = <0x0 0x00898000 0x0 0x4000>; 1254 interrupts = <GIC_SPI 461 IRQ_TYPE_LEVEL_HIGH>; 1255 clocks = <&gcc GCC_QUPV3_WRAP2_S6_CLK>; 1256 clock-names = "se"; 1257 interconnects = <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS 1258 &clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>, 1259 <&hsc_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 1260 &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ALWAYS>; 1261 interconnect-names = "qup-core", 1262 "qup-config"; 1263 pinctrl-0 = <&qup_uart22_default>; 1264 pinctrl-names = "default"; 1265 1266 status = "disabled"; 1267 }; 1268 1269 i2c23: i2c@89c000 { 1270 compatible = "qcom,geni-i2c"; 1271 reg = <0x0 0x0089c000 0x0 0x4000>; 1272 interrupts = <GIC_SPI 462 IRQ_TYPE_LEVEL_HIGH>; 1273 clocks = <&gcc GCC_QUPV3_WRAP2_S7_CLK>; 1274 clock-names = "se"; 1275 interconnects = <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS 1276 &clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>, 1277 <&hsc_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 1278 &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ALWAYS>, 1279 <&aggre3_noc MASTER_QUP_2 QCOM_ICC_TAG_ALWAYS 1280 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 1281 interconnect-names = "qup-core", 1282 "qup-config", 1283 "qup-memory"; 1284 dmas = <&gpi_dma2 0 7 QCOM_GPI_I2C>, 1285 <&gpi_dma2 1 7 QCOM_GPI_I2C>; 1286 dma-names = "tx", 1287 "rx"; 1288 pinctrl-0 = <&qup_i2c23_data_clk>; 1289 pinctrl-names = "default"; 1290 #address-cells = <1>; 1291 #size-cells = <0>; 1292 1293 status = "disabled"; 1294 }; 1295 1296 spi23: spi@89c000 { 1297 compatible = "qcom,geni-spi"; 1298 reg = <0x0 0x0089c000 0x0 0x4000>; 1299 interrupts = <GIC_SPI 462 IRQ_TYPE_LEVEL_HIGH>; 1300 clocks = <&gcc GCC_QUPV3_WRAP2_S7_CLK>; 1301 clock-names = "se"; 1302 interconnects = <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS 1303 &clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>, 1304 <&hsc_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 1305 &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ALWAYS>, 1306 <&aggre3_noc MASTER_QUP_2 QCOM_ICC_TAG_ALWAYS 1307 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 1308 interconnect-names = "qup-core", 1309 "qup-config", 1310 "qup-memory"; 1311 dmas = <&gpi_dma2 0 7 QCOM_GPI_SPI>, 1312 <&gpi_dma2 1 7 QCOM_GPI_SPI>; 1313 dma-names = "tx", 1314 "rx"; 1315 pinctrl-0 = <&qup_spi23_data_clk>, <&qup_spi23_cs>; 1316 pinctrl-names = "default"; 1317 #address-cells = <1>; 1318 #size-cells = <0>; 1319 1320 status = "disabled"; 1321 }; 1322 }; 1323 1324 gpi_dma1: dma-controller@a00000 { 1325 compatible = "qcom,glymur-gpi-dma", "qcom,sm6350-gpi-dma"; 1326 reg = <0x0 0x00a00000 0x0 0x60000>; 1327 interrupts = <GIC_SPI 279 IRQ_TYPE_LEVEL_HIGH>, 1328 <GIC_SPI 280 IRQ_TYPE_LEVEL_HIGH>, 1329 <GIC_SPI 281 IRQ_TYPE_LEVEL_HIGH>, 1330 <GIC_SPI 282 IRQ_TYPE_LEVEL_HIGH>, 1331 <GIC_SPI 283 IRQ_TYPE_LEVEL_HIGH>, 1332 <GIC_SPI 284 IRQ_TYPE_LEVEL_HIGH>, 1333 <GIC_SPI 293 IRQ_TYPE_LEVEL_HIGH>, 1334 <GIC_SPI 294 IRQ_TYPE_LEVEL_HIGH>, 1335 <GIC_SPI 295 IRQ_TYPE_LEVEL_HIGH>, 1336 <GIC_SPI 296 IRQ_TYPE_LEVEL_HIGH>, 1337 <GIC_SPI 297 IRQ_TYPE_LEVEL_HIGH>, 1338 <GIC_SPI 298 IRQ_TYPE_LEVEL_HIGH>, 1339 <GIC_ESPI 124 IRQ_TYPE_LEVEL_HIGH>, 1340 <GIC_ESPI 125 IRQ_TYPE_LEVEL_HIGH>, 1341 <GIC_ESPI 126 IRQ_TYPE_LEVEL_HIGH>, 1342 <GIC_ESPI 127 IRQ_TYPE_LEVEL_HIGH>; 1343 dma-channels = <16>; 1344 dma-channel-mask = <0x3f>; 1345 #dma-cells = <3>; 1346 iommus = <&apps_smmu 0xcb6 0x0>; 1347 }; 1348 1349 qupv3_1: geniqup@ac0000 { 1350 compatible = "qcom,geni-se-qup"; 1351 reg = <0x0 0x00ac0000 0x0 0x3000>; 1352 clocks = <&gcc GCC_QUPV3_WRAP_1_M_AHB_CLK>, 1353 <&gcc GCC_QUPV3_WRAP_1_S_AHB_CLK>; 1354 clock-names = "m-ahb", 1355 "s-ahb"; 1356 iommus = <&apps_smmu 0xca3 0x0>; 1357 #address-cells = <2>; 1358 #size-cells = <2>; 1359 ranges; 1360 1361 i2c8: i2c@a80000 { 1362 compatible = "qcom,geni-i2c"; 1363 reg = <0x0 0x00a80000 0x0 0x4000>; 1364 interrupts = <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>; 1365 clocks = <&gcc GCC_QUPV3_WRAP1_S0_CLK>; 1366 clock-names = "se"; 1367 interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS 1368 &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>, 1369 <&hsc_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 1370 &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ALWAYS>, 1371 <&aggre3_noc MASTER_QUP_1 QCOM_ICC_TAG_ALWAYS 1372 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 1373 interconnect-names = "qup-core", 1374 "qup-config", 1375 "qup-memory"; 1376 dmas = <&gpi_dma1 0 0 QCOM_GPI_I2C>, 1377 <&gpi_dma1 1 0 QCOM_GPI_I2C>; 1378 dma-names = "tx", 1379 "rx"; 1380 pinctrl-0 = <&qup_i2c8_data_clk>; 1381 pinctrl-names = "default"; 1382 #address-cells = <1>; 1383 #size-cells = <0>; 1384 1385 status = "disabled"; 1386 }; 1387 1388 spi8: spi@a80000 { 1389 compatible = "qcom,geni-spi"; 1390 reg = <0x0 0x00a80000 0x0 0x4000>; 1391 interrupts = <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>; 1392 clocks = <&gcc GCC_QUPV3_WRAP1_S0_CLK>; 1393 clock-names = "se"; 1394 interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS 1395 &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>, 1396 <&hsc_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 1397 &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ALWAYS>, 1398 <&aggre3_noc MASTER_QUP_1 QCOM_ICC_TAG_ALWAYS 1399 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 1400 interconnect-names = "qup-core", 1401 "qup-config", 1402 "qup-memory"; 1403 dmas = <&gpi_dma1 0 0 QCOM_GPI_SPI>, 1404 <&gpi_dma1 1 0 QCOM_GPI_SPI>; 1405 dma-names = "tx", 1406 "rx"; 1407 pinctrl-0 = <&qup_spi8_data_clk>, <&qup_spi8_cs>; 1408 pinctrl-names = "default"; 1409 #address-cells = <1>; 1410 #size-cells = <0>; 1411 1412 status = "disabled"; 1413 }; 1414 1415 i2c9: i2c@a84000 { 1416 compatible = "qcom,geni-i2c"; 1417 reg = <0x0 0x00a84000 0x0 0x4000>; 1418 interrupts = <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>; 1419 clocks = <&gcc GCC_QUPV3_WRAP1_S1_CLK>; 1420 clock-names = "se"; 1421 interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS 1422 &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>, 1423 <&hsc_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 1424 &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ALWAYS>, 1425 <&aggre3_noc MASTER_QUP_1 QCOM_ICC_TAG_ALWAYS 1426 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 1427 interconnect-names = "qup-core", 1428 "qup-config", 1429 "qup-memory"; 1430 dmas = <&gpi_dma1 0 1 QCOM_GPI_I2C>, 1431 <&gpi_dma1 1 1 QCOM_GPI_I2C>; 1432 dma-names = "tx", 1433 "rx"; 1434 pinctrl-0 = <&qup_i2c9_data_clk>; 1435 pinctrl-names = "default"; 1436 #address-cells = <1>; 1437 #size-cells = <0>; 1438 1439 status = "disabled"; 1440 }; 1441 1442 spi9: spi@a84000 { 1443 compatible = "qcom,geni-spi"; 1444 reg = <0x0 0x00a84000 0x0 0x4000>; 1445 interrupts = <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>; 1446 clocks = <&gcc GCC_QUPV3_WRAP1_S1_CLK>; 1447 clock-names = "se"; 1448 interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS 1449 &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>, 1450 <&hsc_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 1451 &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ALWAYS>, 1452 <&aggre3_noc MASTER_QUP_1 QCOM_ICC_TAG_ALWAYS 1453 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 1454 interconnect-names = "qup-core", 1455 "qup-config", 1456 "qup-memory"; 1457 dmas = <&gpi_dma1 0 1 QCOM_GPI_SPI>, 1458 <&gpi_dma1 1 1 QCOM_GPI_SPI>; 1459 dma-names = "tx", 1460 "rx"; 1461 pinctrl-0 = <&qup_spi9_data_clk>, <&qup_spi9_cs>; 1462 pinctrl-names = "default"; 1463 #address-cells = <1>; 1464 #size-cells = <0>; 1465 1466 status = "disabled"; 1467 }; 1468 1469 i2c10: i2c@a88000 { 1470 compatible = "qcom,geni-i2c"; 1471 reg = <0x0 0x00a88000 0x0 0x4000>; 1472 interrupts = <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>; 1473 clocks = <&gcc GCC_QUPV3_WRAP1_S2_CLK>; 1474 clock-names = "se"; 1475 interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS 1476 &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>, 1477 <&hsc_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 1478 &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ALWAYS>, 1479 <&aggre3_noc MASTER_QUP_1 QCOM_ICC_TAG_ALWAYS 1480 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 1481 interconnect-names = "qup-core", 1482 "qup-config", 1483 "qup-memory"; 1484 dmas = <&gpi_dma1 0 2 QCOM_GPI_I2C>, 1485 <&gpi_dma1 1 2 QCOM_GPI_I2C>; 1486 dma-names = "tx", 1487 "rx"; 1488 pinctrl-0 = <&qup_i2c10_data_clk>; 1489 pinctrl-names = "default"; 1490 #address-cells = <1>; 1491 #size-cells = <0>; 1492 1493 status = "disabled"; 1494 }; 1495 1496 spi10: spi@a88000 { 1497 compatible = "qcom,geni-spi"; 1498 reg = <0x0 0x00a88000 0x0 0x4000>; 1499 interrupts = <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>; 1500 clocks = <&gcc GCC_QUPV3_WRAP1_S2_CLK>; 1501 clock-names = "se"; 1502 interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS 1503 &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>, 1504 <&hsc_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 1505 &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ALWAYS>, 1506 <&aggre3_noc MASTER_QUP_1 QCOM_ICC_TAG_ALWAYS 1507 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 1508 interconnect-names = "qup-core", 1509 "qup-config", 1510 "qup-memory"; 1511 dmas = <&gpi_dma1 0 2 QCOM_GPI_SPI>, 1512 <&gpi_dma1 1 2 QCOM_GPI_SPI>; 1513 dma-names = "tx", 1514 "rx"; 1515 pinctrl-0 = <&qup_spi10_data_clk>, <&qup_spi10_cs>; 1516 pinctrl-names = "default"; 1517 #address-cells = <1>; 1518 #size-cells = <0>; 1519 1520 status = "disabled"; 1521 }; 1522 1523 i2c11: i2c@a8c000 { 1524 compatible = "qcom,geni-i2c"; 1525 reg = <0x0 0x00a8c000 0x0 0x4000>; 1526 interrupts = <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>; 1527 clocks = <&gcc GCC_QUPV3_WRAP1_S3_CLK>; 1528 clock-names = "se"; 1529 interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS 1530 &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>, 1531 <&hsc_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 1532 &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ALWAYS>, 1533 <&aggre3_noc MASTER_QUP_1 QCOM_ICC_TAG_ALWAYS 1534 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 1535 interconnect-names = "qup-core", 1536 "qup-config", 1537 "qup-memory"; 1538 dmas = <&gpi_dma1 0 3 QCOM_GPI_I2C>, 1539 <&gpi_dma1 1 3 QCOM_GPI_I2C>; 1540 dma-names = "tx", 1541 "rx"; 1542 pinctrl-0 = <&qup_i2c11_data_clk>; 1543 pinctrl-names = "default"; 1544 #address-cells = <1>; 1545 #size-cells = <0>; 1546 1547 status = "disabled"; 1548 }; 1549 1550 spi11: spi@a8c000 { 1551 compatible = "qcom,geni-spi"; 1552 reg = <0x0 0x00a8c000 0x0 0x4000>; 1553 interrupts = <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>; 1554 clocks = <&gcc GCC_QUPV3_WRAP1_S3_CLK>; 1555 clock-names = "se"; 1556 interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS 1557 &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>, 1558 <&hsc_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 1559 &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ALWAYS>, 1560 <&aggre3_noc MASTER_QUP_1 QCOM_ICC_TAG_ALWAYS 1561 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 1562 interconnect-names = "qup-core", 1563 "qup-config", 1564 "qup-memory"; 1565 dmas = <&gpi_dma1 0 3 QCOM_GPI_SPI>, 1566 <&gpi_dma1 1 3 QCOM_GPI_SPI>; 1567 dma-names = "tx", 1568 "rx"; 1569 pinctrl-0 = <&qup_spi11_data_clk>, <&qup_spi11_cs>; 1570 pinctrl-names = "default"; 1571 #address-cells = <1>; 1572 #size-cells = <0>; 1573 1574 status = "disabled"; 1575 }; 1576 1577 i2c12: i2c@a90000 { 1578 compatible = "qcom,geni-i2c"; 1579 reg = <0x0 0x00a90000 0x0 0x4000>; 1580 interrupts = <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>; 1581 clocks = <&gcc GCC_QUPV3_WRAP1_S4_CLK>; 1582 clock-names = "se"; 1583 interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS 1584 &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>, 1585 <&hsc_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 1586 &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ALWAYS>, 1587 <&aggre3_noc MASTER_QUP_1 QCOM_ICC_TAG_ALWAYS 1588 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 1589 interconnect-names = "qup-core", 1590 "qup-config", 1591 "qup-memory"; 1592 dmas = <&gpi_dma1 0 4 QCOM_GPI_I2C>, 1593 <&gpi_dma1 1 4 QCOM_GPI_I2C>; 1594 dma-names = "tx", 1595 "rx"; 1596 pinctrl-0 = <&qup_i2c12_data_clk>; 1597 pinctrl-names = "default"; 1598 #address-cells = <1>; 1599 #size-cells = <0>; 1600 1601 status = "disabled"; 1602 }; 1603 1604 spi12: spi@a90000 { 1605 compatible = "qcom,geni-spi"; 1606 reg = <0x0 0x00a90000 0x0 0x4000>; 1607 interrupts = <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>; 1608 clocks = <&gcc GCC_QUPV3_WRAP1_S4_CLK>; 1609 clock-names = "se"; 1610 interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS 1611 &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>, 1612 <&hsc_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 1613 &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ALWAYS>, 1614 <&aggre3_noc MASTER_QUP_1 QCOM_ICC_TAG_ALWAYS 1615 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 1616 interconnect-names = "qup-core", 1617 "qup-config", 1618 "qup-memory"; 1619 dmas = <&gpi_dma1 0 4 QCOM_GPI_SPI>, 1620 <&gpi_dma1 1 4 QCOM_GPI_SPI>; 1621 dma-names = "tx", 1622 "rx"; 1623 pinctrl-0 = <&qup_spi12_data_clk>, <&qup_spi12_cs>; 1624 pinctrl-names = "default"; 1625 #address-cells = <1>; 1626 #size-cells = <0>; 1627 1628 status = "disabled"; 1629 }; 1630 1631 i2c13: i2c@a94000 { 1632 compatible = "qcom,geni-i2c"; 1633 reg = <0x0 0x00a94000 0x0 0x4000>; 1634 interrupts = <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>; 1635 clocks = <&gcc GCC_QUPV3_WRAP1_S5_CLK>; 1636 clock-names = "se"; 1637 interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS 1638 &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>, 1639 <&hsc_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 1640 &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ALWAYS>, 1641 <&aggre3_noc MASTER_QUP_1 QCOM_ICC_TAG_ALWAYS 1642 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 1643 interconnect-names = "qup-core", 1644 "qup-config", 1645 "qup-memory"; 1646 dmas = <&gpi_dma1 0 5 QCOM_GPI_I2C>, 1647 <&gpi_dma1 1 5 QCOM_GPI_I2C>; 1648 dma-names = "tx", 1649 "rx"; 1650 pinctrl-0 = <&qup_i2c13_data_clk>; 1651 pinctrl-names = "default"; 1652 #address-cells = <1>; 1653 #size-cells = <0>; 1654 1655 status = "disabled"; 1656 }; 1657 1658 spi13: spi@a94000 { 1659 compatible = "qcom,geni-spi"; 1660 reg = <0x0 0x00a94000 0x0 0x4000>; 1661 interrupts = <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>; 1662 clocks = <&gcc GCC_QUPV3_WRAP1_S5_CLK>; 1663 clock-names = "se"; 1664 interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS 1665 &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>, 1666 <&hsc_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 1667 &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ALWAYS>, 1668 <&aggre3_noc MASTER_QUP_1 QCOM_ICC_TAG_ALWAYS 1669 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 1670 interconnect-names = "qup-core", 1671 "qup-config", 1672 "qup-memory"; 1673 dmas = <&gpi_dma1 0 5 QCOM_GPI_SPI>, 1674 <&gpi_dma1 1 5 QCOM_GPI_SPI>; 1675 dma-names = "tx", 1676 "rx"; 1677 pinctrl-0 = <&qup_spi13_data_clk>, <&qup_spi13_cs>; 1678 pinctrl-names = "default"; 1679 #address-cells = <1>; 1680 #size-cells = <0>; 1681 1682 status = "disabled"; 1683 }; 1684 1685 i2c14: i2c@a98000 { 1686 compatible = "qcom,geni-i2c"; 1687 reg = <0x0 0x00a98000 0x0 0x4000>; 1688 interrupts = <GIC_SPI 363 IRQ_TYPE_LEVEL_HIGH>; 1689 clocks = <&gcc GCC_QUPV3_WRAP1_S6_CLK>; 1690 clock-names = "se"; 1691 interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS 1692 &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>, 1693 <&hsc_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 1694 &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ALWAYS>, 1695 <&aggre3_noc MASTER_QUP_1 QCOM_ICC_TAG_ALWAYS 1696 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 1697 interconnect-names = "qup-core", 1698 "qup-config", 1699 "qup-memory"; 1700 dmas = <&gpi_dma1 0 6 QCOM_GPI_I2C>, 1701 <&gpi_dma1 1 6 QCOM_GPI_I2C>; 1702 dma-names = "tx", 1703 "rx"; 1704 pinctrl-0 = <&qup_i2c14_data_clk>; 1705 pinctrl-names = "default"; 1706 #address-cells = <1>; 1707 #size-cells = <0>; 1708 1709 status = "disabled"; 1710 }; 1711 1712 spi14: spi@a98000 { 1713 compatible = "qcom,geni-spi"; 1714 reg = <0x0 0x00a98000 0x0 0x4000>; 1715 interrupts = <GIC_SPI 363 IRQ_TYPE_LEVEL_HIGH>; 1716 clocks = <&gcc GCC_QUPV3_WRAP1_S6_CLK>; 1717 clock-names = "se"; 1718 interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS 1719 &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>, 1720 <&hsc_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 1721 &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ALWAYS>, 1722 <&aggre3_noc MASTER_QUP_1 QCOM_ICC_TAG_ALWAYS 1723 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 1724 interconnect-names = "qup-core", 1725 "qup-config", 1726 "qup-memory"; 1727 dmas = <&gpi_dma1 0 6 QCOM_GPI_SPI>, 1728 <&gpi_dma1 1 6 QCOM_GPI_SPI>; 1729 dma-names = "tx", 1730 "rx"; 1731 pinctrl-0 = <&qup_spi14_data_clk>, <&qup_spi14_cs>; 1732 pinctrl-names = "default"; 1733 #address-cells = <1>; 1734 #size-cells = <0>; 1735 1736 status = "disabled"; 1737 }; 1738 1739 uart14: serial@a98000 { 1740 compatible = "qcom,geni-uart"; 1741 reg = <0x0 0x00a98000 0x0 0x4000>; 1742 interrupts = <GIC_SPI 363 IRQ_TYPE_LEVEL_HIGH>; 1743 clocks = <&gcc GCC_QUPV3_WRAP1_S6_CLK>; 1744 clock-names = "se"; 1745 interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS 1746 &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>, 1747 <&hsc_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 1748 &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ALWAYS>; 1749 interconnect-names = "qup-core", 1750 "qup-config"; 1751 pinctrl-0 = <&qup_uart14_default>; 1752 pinctrl-names = "default"; 1753 1754 status = "disabled"; 1755 }; 1756 1757 i2c15: i2c@a9c000 { 1758 compatible = "qcom,geni-i2c"; 1759 reg = <0x0 0x00a9c000 0x0 0x4000>; 1760 interrupts = <GIC_SPI 579 IRQ_TYPE_LEVEL_HIGH>; 1761 clocks = <&gcc GCC_QUPV3_WRAP1_S7_CLK>; 1762 clock-names = "se"; 1763 interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS 1764 &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>, 1765 <&hsc_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 1766 &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ALWAYS>, 1767 <&aggre3_noc MASTER_QUP_1 QCOM_ICC_TAG_ALWAYS 1768 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 1769 interconnect-names = "qup-core", 1770 "qup-config", 1771 "qup-memory"; 1772 dmas = <&gpi_dma1 0 7 QCOM_GPI_I2C>, 1773 <&gpi_dma1 1 7 QCOM_GPI_I2C>; 1774 dma-names = "tx", 1775 "rx"; 1776 pinctrl-0 = <&qup_i2c15_data_clk>; 1777 pinctrl-names = "default"; 1778 #address-cells = <1>; 1779 #size-cells = <0>; 1780 1781 status = "disabled"; 1782 }; 1783 1784 spi15: spi@a9c000 { 1785 compatible = "qcom,geni-spi"; 1786 reg = <0x0 0x00a9c000 0x0 0x4000>; 1787 interrupts = <GIC_SPI 579 IRQ_TYPE_LEVEL_HIGH>; 1788 clocks = <&gcc GCC_QUPV3_WRAP1_S7_CLK>; 1789 clock-names = "se"; 1790 interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS 1791 &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>, 1792 <&hsc_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 1793 &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ALWAYS>, 1794 <&aggre3_noc MASTER_QUP_1 QCOM_ICC_TAG_ALWAYS 1795 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 1796 interconnect-names = "qup-core", 1797 "qup-config", 1798 "qup-memory"; 1799 dmas = <&gpi_dma1 0 7 QCOM_GPI_SPI>, 1800 <&gpi_dma1 1 7 QCOM_GPI_SPI>; 1801 dma-names = "tx", 1802 "rx"; 1803 pinctrl-0 = <&qup_spi15_data_clk>, <&qup_spi15_cs>; 1804 pinctrl-names = "default"; 1805 #address-cells = <1>; 1806 #size-cells = <0>; 1807 1808 status = "disabled"; 1809 }; 1810 }; 1811 1812 gpi_dma0: dma-controller@b00000 { 1813 compatible = "qcom,glymur-gpi-dma", "qcom,sm6350-gpi-dma"; 1814 reg = <0x0 0x00b00000 0x0 0x60000>; 1815 interrupts = <GIC_ESPI 76 IRQ_TYPE_LEVEL_HIGH>, 1816 <GIC_ESPI 77 IRQ_TYPE_LEVEL_HIGH>, 1817 <GIC_ESPI 78 IRQ_TYPE_LEVEL_HIGH>, 1818 <GIC_ESPI 79 IRQ_TYPE_LEVEL_HIGH>, 1819 <GIC_ESPI 80 IRQ_TYPE_LEVEL_HIGH>, 1820 <GIC_ESPI 81 IRQ_TYPE_LEVEL_HIGH>, 1821 <GIC_ESPI 82 IRQ_TYPE_LEVEL_HIGH>, 1822 <GIC_ESPI 83 IRQ_TYPE_LEVEL_HIGH>, 1823 <GIC_ESPI 84 IRQ_TYPE_LEVEL_HIGH>, 1824 <GIC_ESPI 85 IRQ_TYPE_LEVEL_HIGH>, 1825 <GIC_ESPI 86 IRQ_TYPE_LEVEL_HIGH>, 1826 <GIC_ESPI 87 IRQ_TYPE_LEVEL_HIGH>, 1827 <GIC_ESPI 88 IRQ_TYPE_LEVEL_HIGH>, 1828 <GIC_ESPI 89 IRQ_TYPE_LEVEL_HIGH>, 1829 <GIC_ESPI 90 IRQ_TYPE_LEVEL_HIGH>, 1830 <GIC_ESPI 91 IRQ_TYPE_LEVEL_HIGH>; 1831 dma-channels = <16>; 1832 dma-channel-mask = <0x3f>; 1833 #dma-cells = <3>; 1834 iommus = <&apps_smmu 0xd36 0x0>; 1835 }; 1836 1837 qupv3_0: geniqup@bc0000 { 1838 compatible = "qcom,geni-se-qup"; 1839 reg = <0x0 0x00bc0000 0x0 0x3000>; 1840 clocks = <&gcc GCC_QUPV3_WRAP_0_M_AHB_CLK>, 1841 <&gcc GCC_QUPV3_WRAP_0_S_AHB_CLK>; 1842 clock-names = "m-ahb", 1843 "s-ahb"; 1844 iommus = <&apps_smmu 0xd23 0x0>; 1845 #address-cells = <2>; 1846 #size-cells = <2>; 1847 ranges; 1848 1849 i2c0: i2c@b80000 { 1850 compatible = "qcom,geni-i2c"; 1851 reg = <0x0 0x00b80000 0x0 0x4000>; 1852 interrupts = <GIC_ESPI 92 IRQ_TYPE_LEVEL_HIGH>; 1853 clocks = <&gcc GCC_QUPV3_WRAP0_S0_CLK>; 1854 clock-names = "se"; 1855 interconnects = <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS 1856 &clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>, 1857 <&hsc_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 1858 &config_noc SLAVE_QUP_0 QCOM_ICC_TAG_ALWAYS>, 1859 <&aggre3_noc MASTER_QUP_0 QCOM_ICC_TAG_ALWAYS 1860 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 1861 interconnect-names = "qup-core", 1862 "qup-config", 1863 "qup-memory"; 1864 dmas = <&gpi_dma0 0 0 QCOM_GPI_I2C>, 1865 <&gpi_dma0 1 0 QCOM_GPI_I2C>; 1866 dma-names = "tx", 1867 "rx"; 1868 pinctrl-0 = <&qup_i2c0_data_clk>; 1869 pinctrl-names = "default"; 1870 #address-cells = <1>; 1871 #size-cells = <0>; 1872 1873 status = "disabled"; 1874 }; 1875 1876 spi0: spi@b80000 { 1877 compatible = "qcom,geni-spi"; 1878 reg = <0x0 0x00b80000 0x0 0x4000>; 1879 interrupts = <GIC_SPI 1052 IRQ_TYPE_LEVEL_HIGH>; 1880 clocks = <&gcc GCC_QUPV3_WRAP0_S0_CLK>; 1881 clock-names = "se"; 1882 interconnects = <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS 1883 &clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>, 1884 <&hsc_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 1885 &config_noc SLAVE_QUP_0 QCOM_ICC_TAG_ALWAYS>, 1886 <&aggre3_noc MASTER_QUP_0 QCOM_ICC_TAG_ALWAYS 1887 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 1888 interconnect-names = "qup-core", 1889 "qup-config", 1890 "qup-memory"; 1891 dmas = <&gpi_dma0 0 0 QCOM_GPI_SPI>, 1892 <&gpi_dma0 1 0 QCOM_GPI_SPI>; 1893 dma-names = "tx", 1894 "rx"; 1895 pinctrl-0 = <&qup_spi0_data_clk>, <&qup_spi0_cs>; 1896 pinctrl-names = "default"; 1897 #address-cells = <1>; 1898 #size-cells = <0>; 1899 1900 status = "disabled"; 1901 }; 1902 1903 i2c1: i2c@b84000 { 1904 compatible = "qcom,geni-i2c"; 1905 reg = <0x0 0x00b84000 0x0 0x4000>; 1906 interrupts = <GIC_SPI 1053 IRQ_TYPE_LEVEL_HIGH>; 1907 clocks = <&gcc GCC_QUPV3_WRAP0_S1_CLK>; 1908 clock-names = "se"; 1909 interconnects = <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS 1910 &clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>, 1911 <&hsc_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 1912 &config_noc SLAVE_QUP_0 QCOM_ICC_TAG_ALWAYS>, 1913 <&aggre3_noc MASTER_QUP_0 QCOM_ICC_TAG_ALWAYS 1914 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 1915 interconnect-names = "qup-core", 1916 "qup-config", 1917 "qup-memory"; 1918 dmas = <&gpi_dma0 0 1 QCOM_GPI_I2C>, 1919 <&gpi_dma0 1 1 QCOM_GPI_I2C>; 1920 dma-names = "tx", 1921 "rx"; 1922 pinctrl-0 = <&qup_i2c1_data_clk>; 1923 pinctrl-names = "default"; 1924 #address-cells = <1>; 1925 #size-cells = <0>; 1926 1927 status = "disabled"; 1928 }; 1929 1930 spi1: spi@b84000 { 1931 compatible = "qcom,geni-spi"; 1932 reg = <0x0 0x00b84000 0x0 0x4000>; 1933 interrupts = <GIC_SPI 1053 IRQ_TYPE_LEVEL_HIGH>; 1934 clocks = <&gcc GCC_QUPV3_WRAP0_S1_CLK>; 1935 clock-names = "se"; 1936 interconnects = <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS 1937 &clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>, 1938 <&hsc_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 1939 &config_noc SLAVE_QUP_0 QCOM_ICC_TAG_ALWAYS>, 1940 <&aggre3_noc MASTER_QUP_0 QCOM_ICC_TAG_ALWAYS 1941 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 1942 interconnect-names = "qup-core", 1943 "qup-config", 1944 "qup-memory"; 1945 dmas = <&gpi_dma0 0 1 QCOM_GPI_SPI>, 1946 <&gpi_dma0 1 1 QCOM_GPI_SPI>; 1947 dma-names = "tx", 1948 "rx"; 1949 pinctrl-0 = <&qup_spi1_data_clk>, <&qup_spi1_cs>; 1950 pinctrl-names = "default"; 1951 #address-cells = <1>; 1952 #size-cells = <0>; 1953 1954 status = "disabled"; 1955 }; 1956 1957 i2c2: i2c@b88000 { 1958 compatible = "qcom,geni-i2c"; 1959 reg = <0x0 0x00b88000 0x0 0x4000>; 1960 interrupts = <GIC_SPI 1054 IRQ_TYPE_LEVEL_HIGH>; 1961 clocks = <&gcc GCC_QUPV3_WRAP0_S2_CLK>; 1962 clock-names = "se"; 1963 interconnects = <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS 1964 &clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>, 1965 <&hsc_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 1966 &config_noc SLAVE_QUP_0 QCOM_ICC_TAG_ALWAYS>, 1967 <&aggre3_noc MASTER_QUP_0 QCOM_ICC_TAG_ALWAYS 1968 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 1969 interconnect-names = "qup-core", 1970 "qup-config", 1971 "qup-memory"; 1972 dmas = <&gpi_dma0 0 2 QCOM_GPI_I2C>, 1973 <&gpi_dma0 1 2 QCOM_GPI_I2C>; 1974 dma-names = "tx", 1975 "rx"; 1976 pinctrl-0 = <&qup_i2c2_data_clk>; 1977 pinctrl-names = "default"; 1978 #address-cells = <1>; 1979 #size-cells = <0>; 1980 1981 status = "disabled"; 1982 }; 1983 1984 spi2: spi@b88000 { 1985 compatible = "qcom,geni-spi"; 1986 reg = <0x0 0x00b88000 0x0 0x4000>; 1987 interrupts = <GIC_SPI 1054 IRQ_TYPE_LEVEL_HIGH>; 1988 clocks = <&gcc GCC_QUPV3_WRAP0_S2_CLK>; 1989 clock-names = "se"; 1990 interconnects = <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS 1991 &clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>, 1992 <&hsc_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 1993 &config_noc SLAVE_QUP_0 QCOM_ICC_TAG_ALWAYS>, 1994 <&aggre3_noc MASTER_QUP_0 QCOM_ICC_TAG_ALWAYS 1995 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 1996 interconnect-names = "qup-core", 1997 "qup-config", 1998 "qup-memory"; 1999 dmas = <&gpi_dma0 0 2 QCOM_GPI_SPI>, 2000 <&gpi_dma0 1 2 QCOM_GPI_SPI>; 2001 dma-names = "tx", 2002 "rx"; 2003 pinctrl-0 = <&qup_spi2_data_clk>, <&qup_spi2_cs>; 2004 pinctrl-names = "default"; 2005 #address-cells = <1>; 2006 #size-cells = <0>; 2007 2008 status = "disabled"; 2009 }; 2010 2011 uart2: serial@b88000 { 2012 compatible = "qcom,geni-uart"; 2013 reg = <0x0 0x00b88000 0x0 0x4000>; 2014 interrupts = <GIC_SPI 1054 IRQ_TYPE_LEVEL_HIGH>; 2015 clocks = <&gcc GCC_QUPV3_WRAP0_S2_CLK>; 2016 clock-names = "se"; 2017 interconnects = <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS 2018 &clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>, 2019 <&hsc_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 2020 &config_noc SLAVE_QUP_0 QCOM_ICC_TAG_ALWAYS>; 2021 interconnect-names = "qup-core", 2022 "qup-config"; 2023 pinctrl-0 = <&qup_uart2_default>; 2024 pinctrl-names = "default"; 2025 2026 status = "disabled"; 2027 }; 2028 2029 i2c3: i2c@b8c000 { 2030 compatible = "qcom,geni-i2c"; 2031 reg = <0x0 0x00b8c000 0x0 0x4000>; 2032 interrupts = <GIC_ESPI 95 IRQ_TYPE_LEVEL_HIGH>; 2033 clocks = <&gcc GCC_QUPV3_WRAP0_S3_CLK>; 2034 clock-names = "se"; 2035 interconnects = <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS 2036 &clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>, 2037 <&hsc_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 2038 &config_noc SLAVE_QUP_0 QCOM_ICC_TAG_ALWAYS>, 2039 <&aggre3_noc MASTER_QUP_0 QCOM_ICC_TAG_ALWAYS 2040 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 2041 interconnect-names = "qup-core", 2042 "qup-config", 2043 "qup-memory"; 2044 dmas = <&gpi_dma0 0 3 QCOM_GPI_I2C>, 2045 <&gpi_dma0 1 3 QCOM_GPI_I2C>; 2046 dma-names = "tx", 2047 "rx"; 2048 pinctrl-0 = <&qup_i2c3_data_clk>; 2049 pinctrl-names = "default"; 2050 #address-cells = <1>; 2051 #size-cells = <0>; 2052 2053 status = "disabled"; 2054 }; 2055 2056 spi3: spi@b8c000 { 2057 compatible = "qcom,geni-spi"; 2058 reg = <0x0 0x00b8c000 0x0 0x4000>; 2059 interrupts = <GIC_SPI 1055 IRQ_TYPE_LEVEL_HIGH>; 2060 clocks = <&gcc GCC_QUPV3_WRAP0_S3_CLK>; 2061 clock-names = "se"; 2062 interconnects = <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS 2063 &clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>, 2064 <&hsc_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 2065 &config_noc SLAVE_QUP_0 QCOM_ICC_TAG_ALWAYS>, 2066 <&aggre3_noc MASTER_QUP_0 QCOM_ICC_TAG_ALWAYS 2067 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 2068 interconnect-names = "qup-core", 2069 "qup-config", 2070 "qup-memory"; 2071 dmas = <&gpi_dma0 0 3 QCOM_GPI_SPI>, 2072 <&gpi_dma0 1 3 QCOM_GPI_SPI>; 2073 dma-names = "tx", 2074 "rx"; 2075 pinctrl-0 = <&qup_spi3_data_clk>, <&qup_spi3_cs>; 2076 pinctrl-names = "default"; 2077 #address-cells = <1>; 2078 #size-cells = <0>; 2079 2080 status = "disabled"; 2081 }; 2082 2083 i2c4: i2c@b90000 { 2084 compatible = "qcom,geni-i2c"; 2085 reg = <0x0 0x00b90000 0x0 0x4000>; 2086 interrupts = <GIC_ESPI 96 IRQ_TYPE_LEVEL_HIGH>; 2087 clocks = <&gcc GCC_QUPV3_WRAP0_S4_CLK>; 2088 clock-names = "se"; 2089 interconnects = <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS 2090 &clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>, 2091 <&hsc_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 2092 &config_noc SLAVE_QUP_0 QCOM_ICC_TAG_ALWAYS>, 2093 <&aggre3_noc MASTER_QUP_0 QCOM_ICC_TAG_ALWAYS 2094 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 2095 interconnect-names = "qup-core", 2096 "qup-config", 2097 "qup-memory"; 2098 dmas = <&gpi_dma0 0 4 QCOM_GPI_I2C>, 2099 <&gpi_dma0 1 4 QCOM_GPI_I2C>; 2100 dma-names = "tx", 2101 "rx"; 2102 pinctrl-0 = <&qup_i2c4_data_clk>; 2103 pinctrl-names = "default"; 2104 #address-cells = <1>; 2105 #size-cells = <0>; 2106 2107 status = "disabled"; 2108 }; 2109 2110 spi4: spi@b90000 { 2111 compatible = "qcom,geni-spi"; 2112 reg = <0x0 0x00b90000 0x0 0x4000>; 2113 interrupts = <GIC_SPI 1056 IRQ_TYPE_LEVEL_HIGH>; 2114 clocks = <&gcc GCC_QUPV3_WRAP0_S4_CLK>; 2115 clock-names = "se"; 2116 interconnects = <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS 2117 &clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>, 2118 <&hsc_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 2119 &config_noc SLAVE_QUP_0 QCOM_ICC_TAG_ALWAYS>, 2120 <&aggre3_noc MASTER_QUP_0 QCOM_ICC_TAG_ALWAYS 2121 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 2122 interconnect-names = "qup-core", 2123 "qup-config", 2124 "qup-memory"; 2125 dmas = <&gpi_dma0 0 4 QCOM_GPI_SPI>, 2126 <&gpi_dma0 1 4 QCOM_GPI_SPI>; 2127 dma-names = "tx", 2128 "rx"; 2129 pinctrl-0 = <&qup_spi4_data_clk>, <&qup_spi4_cs>; 2130 pinctrl-names = "default"; 2131 #address-cells = <1>; 2132 #size-cells = <0>; 2133 2134 status = "disabled"; 2135 }; 2136 2137 i2c5: i2c@b94000 { 2138 compatible = "qcom,geni-i2c"; 2139 reg = <0x0 0x00b94000 0x0 0x4000>; 2140 interrupts = <GIC_ESPI 97 IRQ_TYPE_LEVEL_HIGH>; 2141 clocks = <&gcc GCC_QUPV3_WRAP0_S5_CLK>; 2142 clock-names = "se"; 2143 interconnects = <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS 2144 &clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>, 2145 <&hsc_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 2146 &config_noc SLAVE_QUP_0 QCOM_ICC_TAG_ALWAYS>, 2147 <&aggre3_noc MASTER_QUP_0 QCOM_ICC_TAG_ALWAYS 2148 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 2149 interconnect-names = "qup-core", 2150 "qup-config", 2151 "qup-memory"; 2152 dmas = <&gpi_dma0 0 5 QCOM_GPI_I2C>, 2153 <&gpi_dma0 1 5 QCOM_GPI_I2C>; 2154 dma-names = "tx", 2155 "rx"; 2156 pinctrl-0 = <&qup_i2c5_data_clk>; 2157 pinctrl-names = "default"; 2158 #address-cells = <1>; 2159 #size-cells = <0>; 2160 2161 status = "disabled"; 2162 }; 2163 2164 spi5: spi@b94000 { 2165 compatible = "qcom,geni-spi"; 2166 reg = <0x0 0x00b94000 0x0 0x4000>; 2167 interrupts = <GIC_SPI 1057 IRQ_TYPE_LEVEL_HIGH>; 2168 clocks = <&gcc GCC_QUPV3_WRAP0_S5_CLK>; 2169 clock-names = "se"; 2170 interconnects = <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS 2171 &clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>, 2172 <&hsc_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 2173 &config_noc SLAVE_QUP_0 QCOM_ICC_TAG_ALWAYS>, 2174 <&aggre3_noc MASTER_QUP_0 QCOM_ICC_TAG_ALWAYS 2175 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 2176 interconnect-names = "qup-core", 2177 "qup-config", 2178 "qup-memory"; 2179 dmas = <&gpi_dma0 0 5 QCOM_GPI_SPI>, 2180 <&gpi_dma0 1 5 QCOM_GPI_SPI>; 2181 dma-names = "tx", 2182 "rx"; 2183 pinctrl-0 = <&qup_spi5_data_clk>, <&qup_spi5_cs>; 2184 pinctrl-names = "default"; 2185 #address-cells = <1>; 2186 #size-cells = <0>; 2187 2188 status = "disabled"; 2189 }; 2190 2191 i2c6: i2c@b98000 { 2192 compatible = "qcom,geni-i2c"; 2193 reg = <0x0 0x00b98000 0x0 0x4000>; 2194 interrupts = <GIC_SPI 1058 IRQ_TYPE_LEVEL_HIGH>; 2195 clocks = <&gcc GCC_QUPV3_WRAP0_S6_CLK>; 2196 clock-names = "se"; 2197 interconnects = <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS 2198 &clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>, 2199 <&hsc_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 2200 &config_noc SLAVE_QUP_0 QCOM_ICC_TAG_ALWAYS>, 2201 <&aggre3_noc MASTER_QUP_0 QCOM_ICC_TAG_ALWAYS 2202 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 2203 interconnect-names = "qup-core", 2204 "qup-config", 2205 "qup-memory"; 2206 dmas = <&gpi_dma0 0 6 QCOM_GPI_I2C>, 2207 <&gpi_dma0 1 6 QCOM_GPI_I2C>; 2208 dma-names = "tx", 2209 "rx"; 2210 pinctrl-0 = <&qup_i2c6_data_clk>; 2211 pinctrl-names = "default"; 2212 #address-cells = <1>; 2213 #size-cells = <0>; 2214 2215 status = "disabled"; 2216 }; 2217 2218 spi6: spi@b98000 { 2219 compatible = "qcom,geni-spi"; 2220 reg = <0x0 0x00b98000 0x0 0x4000>; 2221 interrupts = <GIC_SPI 1058 IRQ_TYPE_LEVEL_HIGH>; 2222 clocks = <&gcc GCC_QUPV3_WRAP0_S6_CLK>; 2223 clock-names = "se"; 2224 interconnects = <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS 2225 &clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>, 2226 <&hsc_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 2227 &config_noc SLAVE_QUP_0 QCOM_ICC_TAG_ALWAYS>, 2228 <&aggre3_noc MASTER_QUP_0 QCOM_ICC_TAG_ALWAYS 2229 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 2230 interconnect-names = "qup-core", 2231 "qup-config", 2232 "qup-memory"; 2233 dmas = <&gpi_dma0 0 6 QCOM_GPI_SPI>, 2234 <&gpi_dma0 1 6 QCOM_GPI_SPI>; 2235 dma-names = "tx", 2236 "rx"; 2237 pinctrl-0 = <&qup_spi6_data_clk>, <&qup_spi6_cs>; 2238 pinctrl-names = "default"; 2239 #address-cells = <1>; 2240 #size-cells = <0>; 2241 2242 status = "disabled"; 2243 }; 2244 2245 i2c7: i2c@b9c000 { 2246 compatible = "qcom,geni-i2c"; 2247 reg = <0x0 0x00b9c000 0x0 0x4000>; 2248 interrupts = <GIC_SPI 1059 IRQ_TYPE_LEVEL_HIGH>; 2249 clocks = <&gcc GCC_QUPV3_WRAP0_S7_CLK>; 2250 clock-names = "se"; 2251 interconnects = <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS 2252 &clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>, 2253 <&hsc_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 2254 &config_noc SLAVE_QUP_0 QCOM_ICC_TAG_ALWAYS>, 2255 <&aggre3_noc MASTER_QUP_0 QCOM_ICC_TAG_ALWAYS 2256 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 2257 interconnect-names = "qup-core", 2258 "qup-config", 2259 "qup-memory"; 2260 dmas = <&gpi_dma0 0 7 QCOM_GPI_I2C>, 2261 <&gpi_dma0 1 7 QCOM_GPI_I2C>; 2262 dma-names = "tx", 2263 "rx"; 2264 pinctrl-0 = <&qup_i2c7_data_clk>; 2265 pinctrl-names = "default"; 2266 #address-cells = <1>; 2267 #size-cells = <0>; 2268 2269 status = "disabled"; 2270 }; 2271 2272 spi7: spi@b9c000 { 2273 compatible = "qcom,geni-spi"; 2274 reg = <0x0 0x00b9c000 0x0 0x4000>; 2275 interrupts = <GIC_SPI 1059 IRQ_TYPE_LEVEL_HIGH>; 2276 clocks = <&gcc GCC_QUPV3_WRAP0_S7_CLK>; 2277 clock-names = "se"; 2278 interconnects = <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS 2279 &clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>, 2280 <&hsc_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 2281 &config_noc SLAVE_QUP_0 QCOM_ICC_TAG_ALWAYS>, 2282 <&aggre3_noc MASTER_QUP_0 QCOM_ICC_TAG_ALWAYS 2283 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 2284 interconnect-names = "qup-core", 2285 "qup-config", 2286 "qup-memory"; 2287 dmas = <&gpi_dma0 0 7 QCOM_GPI_SPI>, 2288 <&gpi_dma0 1 7 QCOM_GPI_SPI>; 2289 dma-names = "tx", 2290 "rx"; 2291 pinctrl-0 = <&qup_spi7_data_clk>, <&qup_spi7_cs>; 2292 pinctrl-names = "default"; 2293 #address-cells = <1>; 2294 #size-cells = <0>; 2295 2296 status = "disabled"; 2297 }; 2298 }; 2299 2300 usb_hs_phy: phy@fa0000 { 2301 compatible = "qcom,glymur-m31-eusb2-phy", 2302 "qcom,sm8750-m31-eusb2-phy"; 2303 reg = <0x0 0x00fa0000 0x0 0x154>; 2304 #phy-cells = <0>; 2305 2306 clocks = <&tcsr TCSR_USB2_1_CLKREF_EN>; 2307 clock-names = "ref"; 2308 2309 resets = <&gcc GCC_QUSB2PHY_USB20_HS_BCR>; 2310 2311 status = "disabled"; 2312 }; 2313 2314 usb_mp_hsphy0: phy@fa1000 { 2315 compatible = "qcom,glymur-m31-eusb2-phy", 2316 "qcom,sm8750-m31-eusb2-phy"; 2317 2318 reg = <0x0 0x00fa1000 0x0 0x29c>; 2319 #phy-cells = <0>; 2320 2321 clocks = <&tcsr TCSR_USB2_1_CLKREF_EN>; 2322 clock-names = "ref"; 2323 2324 resets = <&gcc GCC_QUSB2PHY_HS0_MP_BCR>; 2325 2326 status = "disabled"; 2327 }; 2328 2329 usb_mp_hsphy1: phy@fa2000 { 2330 compatible = "qcom,glymur-m31-eusb2-phy", 2331 "qcom,sm8750-m31-eusb2-phy"; 2332 2333 reg = <0x0 0x00fa2000 0x0 0x29c>; 2334 #phy-cells = <0>; 2335 2336 clocks = <&tcsr TCSR_USB2_2_CLKREF_EN>; 2337 clock-names = "ref"; 2338 2339 resets = <&gcc GCC_QUSB2PHY_HS1_MP_BCR>; 2340 2341 status = "disabled"; 2342 }; 2343 2344 usb_mp_qmpphy0: phy@fa3000 { 2345 compatible = "qcom,glymur-qmp-usb3-uni-phy"; 2346 reg = <0x0 0x00fa3000 0x0 0x2000>; 2347 2348 clocks = <&gcc GCC_USB3_MP_PHY_AUX_CLK>, 2349 <&tcsr TCSR_USB3_0_CLKREF_EN>, 2350 <&gcc GCC_USB3_MP_PHY_COM_AUX_CLK>, 2351 <&gcc GCC_USB3_MP_PHY_PIPE_0_CLK>; 2352 clock-names = "aux", 2353 "ref", 2354 "com_aux", 2355 "pipe"; 2356 2357 power-domains = <&gcc GCC_USB3_MP_SS0_PHY_GDSC>; 2358 2359 resets = <&gcc GCC_USB3_MP_SS0_PHY_BCR>, 2360 <&gcc GCC_USB3UNIPHY_PHY_MP0_BCR>; 2361 reset-names = "phy", 2362 "phy_phy"; 2363 2364 clock-output-names = "usb3_uni_phy_0_pipe_clk_src"; 2365 #clock-cells = <0>; 2366 #phy-cells = <0>; 2367 2368 status = "disabled"; 2369 }; 2370 2371 usb_mp_qmpphy1: phy@fa5000 { 2372 compatible = "qcom,glymur-qmp-usb3-uni-phy"; 2373 reg = <0x0 0x00fa5000 0x0 0x2000>; 2374 2375 clocks = <&gcc GCC_USB3_MP_PHY_AUX_CLK>, 2376 <&tcsr TCSR_USB3_1_CLKREF_EN>, 2377 <&gcc GCC_USB3_MP_PHY_COM_AUX_CLK>, 2378 <&gcc GCC_USB3_MP_PHY_PIPE_1_CLK>; 2379 clock-names = "aux", 2380 "ref", 2381 "com_aux", 2382 "pipe"; 2383 2384 power-domains = <&gcc GCC_USB3_MP_SS1_PHY_GDSC>; 2385 2386 resets = <&gcc GCC_USB3_MP_SS1_PHY_BCR>, 2387 <&gcc GCC_USB3UNIPHY_PHY_MP1_BCR>; 2388 reset-names = "phy", 2389 "phy_phy"; 2390 2391 clock-output-names = "usb3_uni_phy_1_pipe_clk_src"; 2392 2393 #clock-cells = <0>; 2394 #phy-cells = <0>; 2395 2396 status = "disabled"; 2397 }; 2398 2399 mdss_dp3_phy: phy@faac00 { 2400 compatible = "qcom,glymur-dp-phy"; 2401 reg = <0x0 0x00faac00 0x0 0x1d0>, 2402 <0x0 0x00faa400 0x0 0x128>, 2403 <0x0 0x00faa800 0x0 0x128>, 2404 <0x0 0x00faa000 0x0 0x358>; 2405 2406 clocks = <&dispcc DISP_CC_MDSS_DPTX3_AUX_CLK>, 2407 <&dispcc DISP_CC_MDSS_AHB_CLK>, 2408 <&tcsr TCSR_EDP_CLKREF_EN>; 2409 clock-names = "aux", 2410 "cfg_ahb", 2411 "ref"; 2412 2413 power-domains = <&rpmhpd RPMHPD_MX>; 2414 2415 #clock-cells = <1>; 2416 #phy-cells = <0>; 2417 2418 status = "disabled"; 2419 }; 2420 2421 usb_0_hsphy: phy@fd3000 { 2422 compatible = "qcom,glymur-m31-eusb2-phy", 2423 "qcom,sm8750-m31-eusb2-phy"; 2424 2425 reg = <0x0 0x00fd3000 0x0 0x29c>; 2426 #phy-cells = <0>; 2427 2428 clocks = <&rpmhcc RPMH_CXO_CLK>; 2429 clock-names = "ref"; 2430 2431 resets = <&gcc GCC_QUSB2PHY_PRIM_BCR>; 2432 2433 status = "disabled"; 2434 }; 2435 2436 usb_0_qmpphy: phy@fd5000 { 2437 compatible = "qcom,glymur-qmp-usb3-dp-phy"; 2438 reg = <0x0 0x00fd5000 0x0 0x8000>; 2439 2440 clocks = <&gcc GCC_USB3_PRIM_PHY_AUX_CLK>, 2441 <&rpmhcc RPMH_CXO_CLK>, 2442 <&gcc GCC_USB3_PRIM_PHY_COM_AUX_CLK>, 2443 <&gcc GCC_USB3_PRIM_PHY_PIPE_CLK>; 2444 clock-names = "aux", 2445 "ref", 2446 "com_aux", 2447 "usb3_pipe"; 2448 2449 resets = <&gcc GCC_USB3_PHY_PRIM_BCR>, 2450 <&gcc GCC_USB3PHY_PHY_PRIM_BCR>; 2451 2452 reset-names = "phy", 2453 "common"; 2454 2455 power-domains = <&gcc GCC_USB_0_PHY_GDSC>; 2456 2457 #clock-cells = <1>; 2458 #phy-cells = <1>; 2459 2460 mode-switch; 2461 orientation-switch; 2462 2463 status = "disabled"; 2464 2465 ports { 2466 #address-cells = <1>; 2467 #size-cells = <0>; 2468 2469 port@0 { 2470 reg = <0>; 2471 2472 usb_0_qmpphy_out: endpoint { 2473 }; 2474 }; 2475 2476 port@1 { 2477 reg = <1>; 2478 2479 usb_0_qmpphy_usb_ss_in: endpoint { 2480 remote-endpoint = <&usb_0_dwc3_ss>; 2481 }; 2482 }; 2483 2484 port@2 { 2485 reg = <2>; 2486 2487 usb_dp_qmpphy_dp_in: endpoint { 2488 remote-endpoint = <&mdss_dp0_out>; 2489 }; 2490 }; 2491 }; 2492 }; 2493 2494 usb_1_hsphy: phy@fdd000 { 2495 compatible = "qcom,glymur-m31-eusb2-phy", 2496 "qcom,sm8750-m31-eusb2-phy"; 2497 2498 reg = <0x0 0x00fdd000 0x0 0x29c>; 2499 #phy-cells = <0>; 2500 2501 clocks = <&rpmhcc RPMH_CXO_CLK>; 2502 clock-names = "ref"; 2503 2504 resets = <&gcc GCC_QUSB2PHY_SEC_BCR>; 2505 2506 status = "disabled"; 2507 }; 2508 2509 usb_1_qmpphy: phy@fde000 { 2510 compatible = "qcom,glymur-qmp-usb3-dp-phy"; 2511 reg = <0x0 0x00fde000 0x0 0x8000>; 2512 2513 clocks = <&gcc GCC_USB3_SEC_PHY_AUX_CLK>, 2514 <&tcsr TCSR_USB4_1_CLKREF_EN>, 2515 <&gcc GCC_USB3_SEC_PHY_COM_AUX_CLK>, 2516 <&gcc GCC_USB3_SEC_PHY_PIPE_CLK>; 2517 clock-names = "aux", 2518 "ref", 2519 "com_aux", 2520 "usb3_pipe"; 2521 2522 power-domains = <&gcc GCC_USB_1_PHY_GDSC>; 2523 2524 resets = <&gcc GCC_USB3_PHY_SEC_BCR>, 2525 <&gcc GCC_USB3PHY_PHY_SEC_BCR>; 2526 reset-names = "phy", 2527 "common"; 2528 2529 #clock-cells = <1>; 2530 #phy-cells = <1>; 2531 2532 mode-switch; 2533 orientation-switch; 2534 2535 status = "disabled"; 2536 2537 ports { 2538 #address-cells = <1>; 2539 #size-cells = <0>; 2540 2541 port@0 { 2542 reg = <0>; 2543 2544 usb_1_qmpphy_out: endpoint { 2545 }; 2546 }; 2547 2548 port@1 { 2549 reg = <1>; 2550 2551 usb_1_qmpphy_usb_ss_in: endpoint { 2552 remote-endpoint = <&usb_1_dwc3_ss>; 2553 }; 2554 }; 2555 2556 port@2 { 2557 reg = <2>; 2558 2559 usb_1_qmpphy_dp_in: endpoint { 2560 remote-endpoint = <&mdss_dp1_out>; 2561 }; 2562 }; 2563 }; 2564 }; 2565 2566 2567 /* cluster0 */ 2568 bwmon_cluster0: pmu@100c400 { 2569 compatible = "qcom,glymur-cpu-bwmon", "qcom,sdm845-bwmon"; 2570 reg = <0x0 0x0100c400 0x0 0x600>; 2571 2572 interrupts = <GIC_SPI 903 IRQ_TYPE_LEVEL_HIGH>; 2573 2574 interconnects = <&hsc_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY 2575 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ACTIVE_ONLY>; 2576 2577 operating-points-v2 = <&cpu_bwmon_opp_table>; 2578 2579 cpu_bwmon_opp_table: opp-table { 2580 compatible = "operating-points-v2"; 2581 2582 opp-0 { 2583 opp-peak-kBps = <800000>; 2584 }; 2585 2586 opp-1 { 2587 opp-peak-kBps = <2188800>; 2588 }; 2589 2590 opp-2 { 2591 opp-peak-kBps = <5414400>; 2592 }; 2593 2594 opp-3 { 2595 opp-peak-kBps = <6220800>; 2596 }; 2597 2598 opp-4 { 2599 opp-peak-kBps = <6835200>; 2600 }; 2601 2602 opp-5 { 2603 opp-peak-kBps = <8371200>; 2604 }; 2605 2606 opp-6 { 2607 opp-peak-kBps = <10944000>; 2608 }; 2609 2610 opp-7 { 2611 opp-peak-kBps = <12748800>; 2612 }; 2613 2614 opp-8 { 2615 opp-peak-kBps = <14745600>; 2616 }; 2617 2618 opp-9 { 2619 opp-peak-kBps = <16896000>; 2620 }; 2621 2622 opp-10 { 2623 opp-peak-kBps = <19046400>; 2624 }; 2625 2626 opp-11 { 2627 opp-peak-kBps = <21332000>; 2628 }; 2629 }; 2630 }; 2631 2632 /* cluster1 */ 2633 bwmon_cluster1: pmu@100d400 { 2634 compatible = "qcom,glymur-cpu-bwmon", "qcom,sdm845-bwmon"; 2635 reg = <0x0 0x0100d400 0x0 0x600>; 2636 2637 interrupts = <GIC_SPI 901 IRQ_TYPE_LEVEL_HIGH>; 2638 2639 interconnects = <&hsc_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY 2640 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ACTIVE_ONLY>; 2641 2642 operating-points-v2 = <&cpu_bwmon_opp_table>; 2643 }; 2644 2645 /* cluster2 */ 2646 bwmon_cluster2: pmu@100e400 { 2647 compatible = "qcom,glymur-cpu-bwmon", "qcom,sdm845-bwmon"; 2648 reg = <0x0 0x0100e400 0x0 0x600>; 2649 2650 interrupts = <GIC_SPI 902 IRQ_TYPE_LEVEL_HIGH>; 2651 2652 interconnects = <&hsc_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY 2653 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ACTIVE_ONLY>; 2654 2655 operating-points-v2 = <&cpu_bwmon_opp_table>; 2656 }; 2657 cnoc_main: interconnect@1500000 { 2658 compatible = "qcom,glymur-cnoc-main"; 2659 reg = <0x0 0x01500000 0x0 0x17080>; 2660 qcom,bcm-voters = <&apps_bcm_voter>; 2661 #interconnect-cells = <2>; 2662 }; 2663 2664 config_noc: interconnect@1600000 { 2665 compatible = "qcom,glymur-cnoc-cfg"; 2666 reg = <0x0 0x01600000 0x0 0x6600>; 2667 qcom,bcm-voters = <&apps_bcm_voter>; 2668 #interconnect-cells = <2>; 2669 }; 2670 2671 system_noc: interconnect@1680000 { 2672 compatible = "qcom,glymur-system-noc"; 2673 reg = <0x0 0x01680000 0x0 0x1c080>; 2674 qcom,bcm-voters = <&apps_bcm_voter>; 2675 #interconnect-cells = <2>; 2676 }; 2677 2678 pcie_west_anoc: interconnect@16c0000 { 2679 compatible = "qcom,glymur-pcie-west-anoc"; 2680 reg = <0x0 0x016c0000 0x0 0xf580>; 2681 qcom,bcm-voters = <&apps_bcm_voter>; 2682 #interconnect-cells = <2>; 2683 clocks = <&gcc GCC_AGGRE_NOC_PCIE_3A_WEST_SF_AXI_CLK>, 2684 <&gcc GCC_AGGRE_NOC_PCIE_3B_WEST_SF_AXI_CLK>, 2685 <&gcc GCC_AGGRE_NOC_PCIE_4_WEST_SF_AXI_CLK>, 2686 <&gcc GCC_AGGRE_NOC_PCIE_6_WEST_SF_AXI_CLK>; 2687 }; 2688 2689 pcie_east_anoc: interconnect@16d0000 { 2690 compatible = "qcom,glymur-pcie-east-anoc"; 2691 reg = <0x0 0x016d0000 0x0 0xf300>; 2692 qcom,bcm-voters = <&apps_bcm_voter>; 2693 #interconnect-cells = <2>; 2694 clocks = <&gcc GCC_AGGRE_NOC_PCIE_5_EAST_SF_AXI_CLK>; 2695 }; 2696 2697 aggre1_noc: interconnect@16e0000 { 2698 compatible = "qcom,glymur-aggre1-noc"; 2699 reg = <0x0 0x016e0000 0x0 0x14400>; 2700 qcom,bcm-voters = <&apps_bcm_voter>; 2701 #interconnect-cells = <2>; 2702 }; 2703 2704 aggre2_noc: interconnect@1720000 { 2705 compatible = "qcom,glymur-aggre2-noc"; 2706 reg = <0x0 0x01720000 0x0 0x14400>; 2707 qcom,bcm-voters = <&apps_bcm_voter>; 2708 #interconnect-cells = <2>; 2709 clocks = <&gcc GCC_AGGRE_USB3_TERT_AXI_CLK>, 2710 <&gcc GCC_AGGRE_USB4_2_AXI_CLK>, 2711 <&gcc GCC_AGGRE_UFS_PHY_AXI_CLK>; 2712 }; 2713 2714 aggre3_noc: interconnect@1700000 { 2715 compatible = "qcom,glymur-aggre3-noc"; 2716 reg = <0x0 0x01700000 0x0 0x1d400>; 2717 qcom,bcm-voters = <&apps_bcm_voter>; 2718 #interconnect-cells = <2>; 2719 }; 2720 2721 aggre4_noc: interconnect@1740000 { 2722 compatible = "qcom,glymur-aggre4-noc"; 2723 reg = <0x0 0x01740000 0x0 0x14400>; 2724 qcom,bcm-voters = <&apps_bcm_voter>; 2725 #interconnect-cells = <2>; 2726 clocks = <&gcc GCC_AGGRE_USB3_PRIM_AXI_CLK>, 2727 <&gcc GCC_AGGRE_USB3_SEC_AXI_CLK>, 2728 <&gcc GCC_AGGRE_USB4_0_AXI_CLK>, 2729 <&gcc GCC_AGGRE_USB4_1_AXI_CLK>; 2730 }; 2731 2732 mmss_noc: interconnect@1780000 { 2733 compatible = "qcom,glymur-mmss-noc"; 2734 reg = <0x0 0x01780000 0x0 0x5b800>; 2735 qcom,bcm-voters = <&apps_bcm_voter>; 2736 #interconnect-cells = <2>; 2737 }; 2738 2739 pcie_east_slv_noc: interconnect@1900000 { 2740 compatible = "qcom,glymur-pcie-east-slv-noc"; 2741 reg = <0x0 0x01900000 0x0 0xe080>; 2742 qcom,bcm-voters = <&apps_bcm_voter>; 2743 #interconnect-cells = <2>; 2744 }; 2745 2746 pcie_west_slv_noc: interconnect@1920000 { 2747 compatible = "qcom,glymur-pcie-west-slv-noc"; 2748 reg = <0x0 0x01920000 0x0 0xf180>; 2749 qcom,bcm-voters = <&apps_bcm_voter>; 2750 #interconnect-cells = <2>; 2751 }; 2752 2753 pcie4: pci@1bf0000 { 2754 device_type = "pci"; 2755 compatible = "qcom,glymur-pcie", "qcom,pcie-x1e80100"; 2756 reg = <0x0 0x01bf0000 0x0 0x3000>, 2757 <0x0 0x78000000 0x0 0xf20>, 2758 <0x0 0x78000f40 0x0 0xa8>, 2759 <0x0 0x78001000 0x0 0x4000>, 2760 <0x0 0x78005000 0x0 0x100000>, 2761 <0x0 0x01bf3000 0x0 0x1000>; 2762 reg-names = "parf", 2763 "dbi", 2764 "elbi", 2765 "atu", 2766 "config", 2767 "mhi"; 2768 #address-cells = <3>; 2769 #size-cells = <2>; 2770 ranges = <0x01000000 0x0 0x00000000 0x0 0x78105000 0x0 0x100000>, 2771 <0x02000000 0x0 0x78205000 0x0 0x78205000 0x0 0x1dfb000>, 2772 <0x03000000 0x7 0x80000000 0x7 0x80000000 0x0 0x20000000>; 2773 bus-range = <0x00 0xff>; 2774 2775 dma-coherent; 2776 2777 linux,pci-domain = <4>; 2778 num-lanes = <2>; 2779 2780 operating-points-v2 = <&pcie4_opp_table>; 2781 2782 msi-map = <0x0 &gic_its 0xc0000 0x10000>; 2783 iommu-map = <0x0 &pcie_smmu 0x40000 0x10000>; 2784 2785 interrupts = <GIC_SPI 505 IRQ_TYPE_LEVEL_HIGH>, 2786 <GIC_SPI 506 IRQ_TYPE_LEVEL_HIGH>, 2787 <GIC_SPI 507 IRQ_TYPE_LEVEL_HIGH>, 2788 <GIC_SPI 508 IRQ_TYPE_LEVEL_HIGH>, 2789 <GIC_SPI 509 IRQ_TYPE_LEVEL_HIGH>, 2790 <GIC_SPI 510 IRQ_TYPE_LEVEL_HIGH>, 2791 <GIC_SPI 511 IRQ_TYPE_LEVEL_HIGH>, 2792 <GIC_SPI 512 IRQ_TYPE_LEVEL_HIGH>, 2793 <GIC_SPI 944 IRQ_TYPE_LEVEL_HIGH>; 2794 interrupt-names = "msi0", 2795 "msi1", 2796 "msi2", 2797 "msi3", 2798 "msi4", 2799 "msi5", 2800 "msi6", 2801 "msi7", 2802 "global"; 2803 2804 #interrupt-cells = <1>; 2805 interrupt-map-mask = <0 0 0 0x7>; 2806 interrupt-map = <0 0 0 1 &intc 0 0 GIC_SPI 513 IRQ_TYPE_LEVEL_HIGH>, 2807 <0 0 0 2 &intc 0 0 GIC_SPI 514 IRQ_TYPE_LEVEL_HIGH>, 2808 <0 0 0 3 &intc 0 0 GIC_SPI 515 IRQ_TYPE_LEVEL_HIGH>, 2809 <0 0 0 4 &intc 0 0 GIC_SPI 516 IRQ_TYPE_LEVEL_HIGH>; 2810 2811 clocks = <&gcc GCC_PCIE_4_AUX_CLK>, 2812 <&gcc GCC_PCIE_4_CFG_AHB_CLK>, 2813 <&gcc GCC_PCIE_4_MSTR_AXI_CLK>, 2814 <&gcc GCC_PCIE_4_SLV_AXI_CLK>, 2815 <&gcc GCC_PCIE_4_SLV_Q2A_AXI_CLK>, 2816 <&gcc GCC_AGGRE_NOC_PCIE_4_WEST_SF_AXI_CLK>; 2817 clock-names = "aux", 2818 "cfg", 2819 "bus_master", 2820 "bus_slave", 2821 "slave_q2a", 2822 "noc_aggr"; 2823 2824 assigned-clocks = <&gcc GCC_PCIE_4_AUX_CLK>; 2825 assigned-clock-rates = <19200000>; 2826 2827 interconnects = <&pcie_west_anoc MASTER_PCIE_4 QCOM_ICC_TAG_ALWAYS 2828 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>, 2829 <&hsc_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 2830 &pcie_west_slv_noc SLAVE_PCIE_4 QCOM_ICC_TAG_ALWAYS>; 2831 interconnect-names = "pcie-mem", 2832 "cpu-pcie"; 2833 2834 resets = <&gcc GCC_PCIE_4_BCR>, 2835 <&gcc GCC_PCIE_4_LINK_DOWN_BCR>; 2836 reset-names = "pci", 2837 "link_down"; 2838 2839 power-domains = <&gcc GCC_PCIE_4_GDSC>; 2840 2841 eq-presets-8gts = /bits/ 16 <0x5555 0x5555>; 2842 eq-presets-16gts = /bits/ 8 <0x55 0x55>; 2843 2844 status = "disabled"; 2845 2846 pcie4_opp_table: opp-table { 2847 compatible = "operating-points-v2"; 2848 2849 /* GEN 1 x1 */ 2850 opp-2500000-1 { 2851 opp-hz = /bits/ 64 <2500000>; 2852 required-opps = <&rpmhpd_opp_low_svs>; 2853 opp-peak-kBps = <250000 1>; 2854 opp-level = <1>; 2855 }; 2856 2857 /* GEN 1 x2 */ 2858 opp-5000000-1 { 2859 opp-hz = /bits/ 64 <5000000>; 2860 required-opps = <&rpmhpd_opp_low_svs>; 2861 opp-peak-kBps = <500000 1>; 2862 opp-level = <1>; 2863 }; 2864 2865 /* GEN 2 x1 */ 2866 opp-5000000-2 { 2867 opp-hz = /bits/ 64 <5000000>; 2868 required-opps = <&rpmhpd_opp_low_svs>; 2869 opp-peak-kBps = <500000 1>; 2870 opp-level = <2>; 2871 }; 2872 2873 /* GEN 2 x2 */ 2874 opp-10000000-2 { 2875 opp-hz = /bits/ 64 <10000000>; 2876 required-opps = <&rpmhpd_opp_low_svs>; 2877 opp-peak-kBps = <1000000 1>; 2878 opp-level = <2>; 2879 }; 2880 2881 /* GEN 3 x1 */ 2882 opp-8000000-3 { 2883 opp-hz = /bits/ 64 <8000000>; 2884 required-opps = <&rpmhpd_opp_low_svs>; 2885 opp-peak-kBps = <984500 1>; 2886 opp-level = <3>; 2887 }; 2888 2889 /* GEN 3 x2 */ 2890 opp-16000000-3 { 2891 opp-hz = /bits/ 64 <16000000>; 2892 required-opps = <&rpmhpd_opp_low_svs>; 2893 opp-peak-kBps = <1969000 1>; 2894 opp-level = <3>; 2895 }; 2896 2897 /* GEN 4 x1 */ 2898 opp-16000000-4 { 2899 opp-hz = /bits/ 64 <16000000>; 2900 required-opps = <&rpmhpd_opp_low_svs>; 2901 opp-peak-kBps = <1969000 1>; 2902 opp-level = <4>; 2903 }; 2904 2905 /* GEN 4 x2 */ 2906 opp-32000000-4 { 2907 opp-hz = /bits/ 64 <32000000>; 2908 required-opps = <&rpmhpd_opp_low_svs>; 2909 opp-peak-kBps = <3938000 1>; 2910 opp-level = <4>; 2911 }; 2912 2913 }; 2914 2915 pcie4_port0: pcie@0 { 2916 device_type = "pci"; 2917 reg = <0x0 0x0 0x0 0x0 0x0>; 2918 bus-range = <0x01 0xff>; 2919 2920 phys = <&pcie4_phy>; 2921 2922 #address-cells = <3>; 2923 #size-cells = <2>; 2924 ranges; 2925 }; 2926 }; 2927 2928 pcie4_phy: phy@1bf6000 { 2929 compatible = "qcom,glymur-qmp-gen4x2-pcie-phy"; 2930 reg = <0x0 0x01bf6000 0x0 0x2000>; 2931 2932 clocks = <&gcc GCC_PCIE_PHY_4_AUX_CLK>, 2933 <&gcc GCC_PCIE_4_CFG_AHB_CLK>, 2934 <&tcsr TCSR_PCIE_2_CLKREF_EN>, 2935 <&gcc GCC_PCIE_4_PHY_RCHNG_CLK>, 2936 <&gcc GCC_PCIE_4_PIPE_CLK>, 2937 <&gcc GCC_PCIE_4_PIPE_DIV2_CLK>; 2938 clock-names = "aux", 2939 "cfg_ahb", 2940 "ref", 2941 "rchng", 2942 "pipe", 2943 "pipediv2"; 2944 2945 resets = <&gcc GCC_PCIE_4_PHY_BCR>, 2946 <&gcc GCC_PCIE_4_NOCSR_COM_PHY_BCR>; 2947 reset-names = "phy", 2948 "phy_nocsr"; 2949 2950 assigned-clocks = <&gcc GCC_PCIE_4_PHY_RCHNG_CLK>; 2951 assigned-clock-rates = <100000000>; 2952 2953 power-domains = <&gcc GCC_PCIE_4_PHY_GDSC>; 2954 2955 #clock-cells = <0>; 2956 clock-output-names = "pcie4_pipe_clk"; 2957 2958 #phy-cells = <0>; 2959 2960 status = "disabled"; 2961 }; 2962 2963 pcie5: pci@1b40000 { 2964 device_type = "pci"; 2965 compatible = "qcom,glymur-pcie", "qcom,pcie-x1e80100"; 2966 reg = <0x0 0x01b40000 0x0 0x3000>, 2967 <0x0 0x7a000000 0x0 0xf20>, 2968 <0x0 0x7a000f40 0x0 0xa8>, 2969 <0x0 0x7a001000 0x0 0x4000>, 2970 <0x0 0x7a100000 0x0 0x100000>, 2971 <0x0 0x01b43000 0x0 0x1000>; 2972 reg-names = "parf", 2973 "dbi", 2974 "elbi", 2975 "atu", 2976 "config", 2977 "mhi"; 2978 #address-cells = <3>; 2979 #size-cells = <2>; 2980 ranges = <0x01000000 0x0 0x00000000 0x0 0x7a200000 0x0 0x100000>, 2981 <0x02000000 0x0 0x7a300000 0x0 0x7a300000 0x0 0x3d00000>, 2982 <0x03000000 0x7 0xa0000000 0x7 0xa0000000 0x0 0x40000000>; 2983 bus-range = <0x00 0xff>; 2984 2985 dma-coherent; 2986 2987 linux,pci-domain = <5>; 2988 num-lanes = <4>; 2989 2990 operating-points-v2 = <&pcie5_opp_table>; 2991 2992 msi-map = <0x0 &gic_its 0xd0000 0x10000>; 2993 iommu-map = <0x0 &pcie_smmu 0x50000 0x10000>; 2994 2995 interrupts = <GIC_SPI 518 IRQ_TYPE_LEVEL_HIGH>, 2996 <GIC_SPI 519 IRQ_TYPE_LEVEL_HIGH>, 2997 <GIC_SPI 520 IRQ_TYPE_LEVEL_HIGH>, 2998 <GIC_SPI 521 IRQ_TYPE_LEVEL_HIGH>, 2999 <GIC_SPI 522 IRQ_TYPE_LEVEL_HIGH>, 3000 <GIC_SPI 523 IRQ_TYPE_LEVEL_HIGH>, 3001 <GIC_SPI 524 IRQ_TYPE_LEVEL_HIGH>, 3002 <GIC_SPI 525 IRQ_TYPE_LEVEL_HIGH>, 3003 <GIC_SPI 945 IRQ_TYPE_LEVEL_HIGH>; 3004 interrupt-names = "msi0", 3005 "msi1", 3006 "msi2", 3007 "msi3", 3008 "msi4", 3009 "msi5", 3010 "msi6", 3011 "msi7", 3012 "global"; 3013 3014 #interrupt-cells = <1>; 3015 interrupt-map-mask = <0 0 0 0x7>; 3016 interrupt-map = <0 0 0 1 &intc 0 0 GIC_SPI 526 IRQ_TYPE_LEVEL_HIGH>, 3017 <0 0 0 2 &intc 0 0 GIC_SPI 428 IRQ_TYPE_LEVEL_HIGH>, 3018 <0 0 0 3 &intc 0 0 GIC_SPI 429 IRQ_TYPE_LEVEL_HIGH>, 3019 <0 0 0 4 &intc 0 0 GIC_SPI 435 IRQ_TYPE_LEVEL_HIGH>; 3020 3021 clocks = <&gcc GCC_PCIE_5_AUX_CLK>, 3022 <&gcc GCC_PCIE_5_CFG_AHB_CLK>, 3023 <&gcc GCC_PCIE_5_MSTR_AXI_CLK>, 3024 <&gcc GCC_PCIE_5_SLV_AXI_CLK>, 3025 <&gcc GCC_PCIE_5_SLV_Q2A_AXI_CLK>, 3026 <&gcc GCC_AGGRE_NOC_PCIE_5_EAST_SF_AXI_CLK>; 3027 clock-names = "aux", 3028 "cfg", 3029 "bus_master", 3030 "bus_slave", 3031 "slave_q2a", 3032 "noc_aggr"; 3033 3034 assigned-clocks = <&gcc GCC_PCIE_5_AUX_CLK>; 3035 assigned-clock-rates = <19200000>; 3036 3037 interconnects = <&pcie_east_anoc MASTER_PCIE_5 QCOM_ICC_TAG_ALWAYS 3038 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>, 3039 <&hsc_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 3040 &pcie_east_slv_noc SLAVE_PCIE_5 QCOM_ICC_TAG_ALWAYS>; 3041 interconnect-names = "pcie-mem", 3042 "cpu-pcie"; 3043 3044 resets = <&gcc GCC_PCIE_5_BCR>, 3045 <&gcc GCC_PCIE_5_LINK_DOWN_BCR>; 3046 reset-names = "pci", 3047 "link_down"; 3048 3049 power-domains = <&gcc GCC_PCIE_5_GDSC>; 3050 3051 eq-presets-8gts = /bits/ 16 <0x5555 0x5555 0x5555 0x5555>; 3052 eq-presets-16gts = /bits/ 8 <0x55 0x55 0x55 0x55>; 3053 eq-presets-32gts = /bits/ 8 <0x55 0x55 0x55 0x55>; 3054 3055 status = "disabled"; 3056 3057 pcie5_opp_table: opp-table { 3058 compatible = "operating-points-v2"; 3059 3060 /* GEN 1 x1 */ 3061 opp-2500000-1 { 3062 opp-hz = /bits/ 64 <2500000>; 3063 required-opps = <&rpmhpd_opp_low_svs>; 3064 opp-peak-kBps = <250000 1>; 3065 opp-level = <1>; 3066 }; 3067 3068 /* GEN 1 x2 */ 3069 opp-5000000-1 { 3070 opp-hz = /bits/ 64 <5000000>; 3071 required-opps = <&rpmhpd_opp_low_svs>; 3072 opp-peak-kBps = <500000 1>; 3073 opp-level = <1>; 3074 }; 3075 3076 /* GEN 1 x4 */ 3077 opp-10000000-1 { 3078 opp-hz = /bits/ 64 <10000000>; 3079 required-opps = <&rpmhpd_opp_low_svs>; 3080 opp-peak-kBps = <1000000 1>; 3081 opp-level = <1>; 3082 }; 3083 3084 /* GEN 2 x1 */ 3085 opp-5000000-2 { 3086 opp-hz = /bits/ 64 <5000000>; 3087 required-opps = <&rpmhpd_opp_low_svs>; 3088 opp-peak-kBps = <500000 1>; 3089 opp-level = <2>; 3090 }; 3091 3092 /* GEN 2 x2 */ 3093 opp-10000000-2 { 3094 opp-hz = /bits/ 64 <10000000>; 3095 required-opps = <&rpmhpd_opp_low_svs>; 3096 opp-peak-kBps = <1000000 1>; 3097 opp-level = <2>; 3098 }; 3099 3100 /* GEN 2 x4 */ 3101 opp-20000000-2 { 3102 opp-hz = /bits/ 64 <20000000>; 3103 required-opps = <&rpmhpd_opp_low_svs>; 3104 opp-peak-kBps = <2000000 1>; 3105 opp-level = <2>; 3106 }; 3107 3108 /* GEN 3 x1 */ 3109 opp-8000000-3 { 3110 opp-hz = /bits/ 64 <8000000>; 3111 required-opps = <&rpmhpd_opp_low_svs>; 3112 opp-peak-kBps = <984500 1>; 3113 opp-level = <3>; 3114 }; 3115 3116 /* GEN 3 x2 */ 3117 opp-16000000-3 { 3118 opp-hz = /bits/ 64 <16000000>; 3119 required-opps = <&rpmhpd_opp_low_svs>; 3120 opp-peak-kBps = <1969000 1>; 3121 opp-level = <3>; 3122 }; 3123 3124 /* GEN 3 x4 */ 3125 opp-32000000-3 { 3126 opp-hz = /bits/ 64 <32000000>; 3127 required-opps = <&rpmhpd_opp_low_svs>; 3128 opp-peak-kBps = <3938000 1>; 3129 opp-level = <3>; 3130 }; 3131 3132 /* GEN 4 x1 */ 3133 opp-16000000-4 { 3134 opp-hz = /bits/ 64 <16000000>; 3135 required-opps = <&rpmhpd_opp_svs>; 3136 opp-peak-kBps = <1969000 1>; 3137 opp-level = <4>; 3138 }; 3139 3140 /* GEN 4 x2 */ 3141 opp-32000000-4 { 3142 opp-hz = /bits/ 64 <32000000>; 3143 required-opps = <&rpmhpd_opp_svs>; 3144 opp-peak-kBps = <3938000 1>; 3145 opp-level = <4>; 3146 }; 3147 3148 /* GEN 4 x4 */ 3149 opp-64000000-4 { 3150 opp-hz = /bits/ 64 <64000000>; 3151 required-opps = <&rpmhpd_opp_svs>; 3152 opp-peak-kBps = <7876000 1>; 3153 opp-level = <4>; 3154 }; 3155 3156 /* GEN 5 x1 */ 3157 opp-32000000-5 { 3158 opp-hz = /bits/ 64 <32000000>; 3159 required-opps = <&rpmhpd_opp_nom>; 3160 opp-peak-kBps = <3938000 1>; 3161 opp-level = <5>; 3162 }; 3163 3164 /* GEN 5 x2 */ 3165 opp-64000000-5 { 3166 opp-hz = /bits/ 64 <64000000>; 3167 required-opps = <&rpmhpd_opp_nom>; 3168 opp-peak-kBps = <7876000 1>; 3169 opp-level = <5>; 3170 }; 3171 3172 /* GEN 5 x4 */ 3173 opp-128000000-5 { 3174 opp-hz = /bits/ 64 <128000000>; 3175 required-opps = <&rpmhpd_opp_nom>; 3176 opp-peak-kBps = <15753000 1>; 3177 opp-level = <5>; 3178 }; 3179 }; 3180 3181 pcie5_port0: pcie@0 { 3182 device_type = "pci"; 3183 reg = <0x0 0x0 0x0 0x0 0x0>; 3184 bus-range = <0x01 0xff>; 3185 3186 phys = <&pcie5_phy>; 3187 3188 #address-cells = <3>; 3189 #size-cells = <2>; 3190 ranges; 3191 }; 3192 }; 3193 3194 pcie5_phy: phy@1b50000 { 3195 compatible = "qcom,glymur-qmp-gen5x4-pcie-phy"; 3196 reg = <0x0 0x01b50000 0x0 0x10000>; 3197 3198 clocks = <&gcc GCC_PCIE_PHY_5_AUX_CLK>, 3199 <&gcc GCC_PCIE_5_CFG_AHB_CLK>, 3200 <&tcsr TCSR_PCIE_1_CLKREF_EN>, 3201 <&gcc GCC_PCIE_5_PHY_RCHNG_CLK>, 3202 <&gcc GCC_PCIE_5_PIPE_CLK>, 3203 <&gcc GCC_PCIE_5_PIPE_DIV2_CLK>; 3204 clock-names = "aux", 3205 "cfg_ahb", 3206 "ref", 3207 "rchng", 3208 "pipe", 3209 "pipediv2"; 3210 3211 resets = <&gcc GCC_PCIE_5_PHY_BCR>, 3212 <&gcc GCC_PCIE_5_NOCSR_COM_PHY_BCR>; 3213 reset-names = "phy", 3214 "phy_nocsr"; 3215 3216 assigned-clocks = <&gcc GCC_PCIE_5_PHY_RCHNG_CLK>; 3217 assigned-clock-rates = <100000000>; 3218 3219 power-domains = <&gcc GCC_PCIE_5_PHY_GDSC>; 3220 3221 #clock-cells = <0>; 3222 clock-output-names = "pcie5_pipe_clk"; 3223 3224 #phy-cells = <0>; 3225 3226 status = "disabled"; 3227 }; 3228 3229 pcie6: pci@1c00000 { 3230 device_type = "pci"; 3231 compatible = "qcom,glymur-pcie", "qcom,pcie-x1e80100"; 3232 reg = <0x0 0x01c00000 0x0 0x3000>, 3233 <0x0 0x7e000000 0x0 0xf20>, 3234 <0x0 0x7e000f40 0x0 0xa8>, 3235 <0x0 0x7e001000 0x0 0x4000>, 3236 <0x0 0x7e100000 0x0 0x100000>, 3237 <0x0 0x01c03000 0x0 0x1000>; 3238 reg-names = "parf", 3239 "dbi", 3240 "elbi", 3241 "atu", 3242 "config", 3243 "mhi"; 3244 #address-cells = <3>; 3245 #size-cells = <2>; 3246 ranges = <0x01000000 0x0 0x00000000 0x0 0x7e200000 0x0 0x100000>, 3247 <0x02000000 0x0 0x7e300000 0x0 0x7e300000 0x0 0x1d00000>, 3248 <0x03000000 0x7 0xe0000000 0x7 0xe0000000 0x0 0x20000000>; 3249 bus-range = <0x00 0xff>; 3250 3251 dma-coherent; 3252 3253 linux,pci-domain = <6>; 3254 num-lanes = <2>; 3255 3256 operating-points-v2 = <&pcie6_opp_table>; 3257 3258 msi-map = <0x0 &gic_its 0xe0000 0x10000>; 3259 iommu-map = <0x0 &pcie_smmu 0x60000 0x10000>; 3260 3261 interrupts = <GIC_SPI 464 IRQ_TYPE_LEVEL_HIGH>, 3262 <GIC_SPI 465 IRQ_TYPE_LEVEL_HIGH>, 3263 <GIC_SPI 466 IRQ_TYPE_LEVEL_HIGH>, 3264 <GIC_SPI 467 IRQ_TYPE_LEVEL_HIGH>, 3265 <GIC_SPI 468 IRQ_TYPE_LEVEL_HIGH>, 3266 <GIC_SPI 469 IRQ_TYPE_LEVEL_HIGH>, 3267 <GIC_SPI 470 IRQ_TYPE_LEVEL_HIGH>, 3268 <GIC_SPI 471 IRQ_TYPE_LEVEL_HIGH>, 3269 <GIC_SPI 946 IRQ_TYPE_LEVEL_HIGH>; 3270 interrupt-names = "msi0", 3271 "msi1", 3272 "msi2", 3273 "msi3", 3274 "msi4", 3275 "msi5", 3276 "msi6", 3277 "msi7", 3278 "global"; 3279 3280 #interrupt-cells = <1>; 3281 interrupt-map-mask = <0 0 0 0x7>; 3282 interrupt-map = <0 0 0 1 &intc 0 0 GIC_SPI 472 IRQ_TYPE_LEVEL_HIGH>, 3283 <0 0 0 2 &intc 0 0 GIC_SPI 473 IRQ_TYPE_LEVEL_HIGH>, 3284 <0 0 0 3 &intc 0 0 GIC_SPI 474 IRQ_TYPE_LEVEL_HIGH>, 3285 <0 0 0 4 &intc 0 0 GIC_SPI 475 IRQ_TYPE_LEVEL_HIGH>; 3286 3287 clocks = <&gcc GCC_PCIE_6_AUX_CLK>, 3288 <&gcc GCC_PCIE_6_CFG_AHB_CLK>, 3289 <&gcc GCC_PCIE_6_MSTR_AXI_CLK>, 3290 <&gcc GCC_PCIE_6_SLV_AXI_CLK>, 3291 <&gcc GCC_PCIE_6_SLV_Q2A_AXI_CLK>, 3292 <&gcc GCC_AGGRE_NOC_PCIE_6_WEST_SF_AXI_CLK>; 3293 clock-names = "aux", 3294 "cfg", 3295 "bus_master", 3296 "bus_slave", 3297 "slave_q2a", 3298 "noc_aggr"; 3299 3300 assigned-clocks = <&gcc GCC_PCIE_6_AUX_CLK>; 3301 assigned-clock-rates = <19200000>; 3302 3303 interconnects = <&pcie_west_anoc MASTER_PCIE_6 QCOM_ICC_TAG_ALWAYS 3304 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>, 3305 <&hsc_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 3306 &pcie_west_slv_noc SLAVE_PCIE_6 QCOM_ICC_TAG_ALWAYS>; 3307 interconnect-names = "pcie-mem", 3308 "cpu-pcie"; 3309 3310 resets = <&gcc GCC_PCIE_6_BCR>, 3311 <&gcc GCC_PCIE_6_LINK_DOWN_BCR>; 3312 reset-names = "pci", 3313 "link_down"; 3314 3315 power-domains = <&gcc GCC_PCIE_6_GDSC>; 3316 3317 eq-presets-8gts = /bits/ 16 <0x5555 0x5555>; 3318 eq-presets-16gts = /bits/ 8 <0x55 0x55>; 3319 3320 status = "disabled"; 3321 3322 pcie6_opp_table: opp-table { 3323 compatible = "operating-points-v2"; 3324 3325 /* GEN 1 x1 */ 3326 opp-2500000-1 { 3327 opp-hz = /bits/ 64 <2500000>; 3328 required-opps = <&rpmhpd_opp_low_svs>; 3329 opp-peak-kBps = <250000 1>; 3330 opp-level = <1>; 3331 }; 3332 3333 /* GEN 1 x2 */ 3334 opp-5000000-1 { 3335 opp-hz = /bits/ 64 <5000000>; 3336 required-opps = <&rpmhpd_opp_low_svs>; 3337 opp-peak-kBps = <500000 1>; 3338 opp-level = <1>; 3339 }; 3340 3341 /* GEN 2 x1 */ 3342 opp-5000000-2 { 3343 opp-hz = /bits/ 64 <5000000>; 3344 required-opps = <&rpmhpd_opp_low_svs>; 3345 opp-peak-kBps = <500000 1>; 3346 opp-level = <2>; 3347 }; 3348 3349 /* GEN 2 x2 */ 3350 opp-10000000-2 { 3351 opp-hz = /bits/ 64 <10000000>; 3352 required-opps = <&rpmhpd_opp_low_svs>; 3353 opp-peak-kBps = <1000000 1>; 3354 opp-level = <2>; 3355 }; 3356 3357 /* GEN 3 x1 */ 3358 opp-8000000-3 { 3359 opp-hz = /bits/ 64 <8000000>; 3360 required-opps = <&rpmhpd_opp_low_svs>; 3361 opp-peak-kBps = <984500 1>; 3362 opp-level = <3>; 3363 }; 3364 3365 /* GEN 3 x2 */ 3366 opp-16000000-3 { 3367 opp-hz = /bits/ 64 <16000000>; 3368 required-opps = <&rpmhpd_opp_low_svs>; 3369 opp-peak-kBps = <1969000 1>; 3370 opp-level = <3>; 3371 }; 3372 3373 /* GEN 4 x1 */ 3374 opp-16000000-4 { 3375 opp-hz = /bits/ 64 <16000000>; 3376 required-opps = <&rpmhpd_opp_low_svs>; 3377 opp-peak-kBps = <1969000 1>; 3378 opp-level = <4>; 3379 }; 3380 3381 /* GEN 4 x2 */ 3382 opp-32000000-4 { 3383 opp-hz = /bits/ 64 <32000000>; 3384 required-opps = <&rpmhpd_opp_low_svs>; 3385 opp-peak-kBps = <3938000 1>; 3386 opp-level = <4>; 3387 }; 3388 3389 }; 3390 3391 pcie6_port0: pcie@0 { 3392 device_type = "pci"; 3393 reg = <0x0 0x0 0x0 0x0 0x0>; 3394 bus-range = <0x01 0xff>; 3395 3396 phys = <&pcie6_phy>; 3397 3398 #address-cells = <3>; 3399 #size-cells = <2>; 3400 ranges; 3401 }; 3402 }; 3403 3404 pcie6_phy: phy@1c06000 { 3405 compatible = "qcom,glymur-qmp-gen4x2-pcie-phy"; 3406 reg = <0x0 0x01c06000 0x0 0x2000>; 3407 3408 clocks = <&gcc GCC_PCIE_PHY_6_AUX_CLK>, 3409 <&gcc GCC_PCIE_6_CFG_AHB_CLK>, 3410 <&tcsr TCSR_PCIE_4_CLKREF_EN>, 3411 <&gcc GCC_PCIE_6_PHY_RCHNG_CLK>, 3412 <&gcc GCC_PCIE_6_PIPE_CLK>, 3413 <&gcc GCC_PCIE_6_PIPE_DIV2_CLK>; 3414 clock-names = "aux", 3415 "cfg_ahb", 3416 "ref", 3417 "rchng", 3418 "pipe", 3419 "pipediv2"; 3420 3421 resets = <&gcc GCC_PCIE_6_PHY_BCR>, 3422 <&gcc GCC_PCIE_6_NOCSR_COM_PHY_BCR>; 3423 reset-names = "phy", 3424 "phy_nocsr"; 3425 3426 assigned-clocks = <&gcc GCC_PCIE_6_PHY_RCHNG_CLK>; 3427 assigned-clock-rates = <100000000>; 3428 3429 power-domains = <&gcc GCC_PCIE_6_PHY_GDSC>; 3430 3431 #clock-cells = <0>; 3432 clock-output-names = "pcie6_pipe_clk"; 3433 3434 #phy-cells = <0>; 3435 3436 status = "disabled"; 3437 }; 3438 3439 pcie3b: pci@1b80000 { 3440 device_type = "pci"; 3441 compatible = "qcom,glymur-pcie", "qcom,pcie-x1e80100"; 3442 reg = <0x0 0x01b80000 0x0 0x3000>, 3443 <0x0 0x74000000 0x0 0xf20>, 3444 <0x0 0x74000f40 0x0 0xa8>, 3445 <0x0 0x74001000 0x0 0x4000>, 3446 <0x0 0x74100000 0x0 0x100000>, 3447 <0x0 0x01b83000 0x0 0x1000>; 3448 reg-names = "parf", 3449 "dbi", 3450 "elbi", 3451 "atu", 3452 "config", 3453 "mhi"; 3454 #address-cells = <3>; 3455 #size-cells = <2>; 3456 ranges = <0x01000000 0x0 0x00000000 0x0 0x74200000 0x0 0x100000>, 3457 <0x02000000 0x0 0x74300000 0x0 0x74300000 0x0 0x3d00000>, 3458 <0x03000000 0x7 0x40000000 0x7 0x40000000 0x0 0x40000000>; 3459 bus-range = <0x00 0xff>; 3460 3461 dma-coherent; 3462 3463 linux,pci-domain = <7>; 3464 num-lanes = <4>; 3465 3466 operating-points-v2 = <&pcie3b_opp_table>; 3467 3468 msi-map = <0x0 &gic_its 0xf0000 0x10000>; 3469 iommu-map = <0x0 &pcie_smmu 0x70000 0x10000>; 3470 3471 interrupts = <GIC_SPI 950 IRQ_TYPE_LEVEL_HIGH>, 3472 <GIC_SPI 951 IRQ_TYPE_LEVEL_HIGH>, 3473 <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>, 3474 <GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH>, 3475 <GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>, 3476 <GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>, 3477 <GIC_SPI 147 IRQ_TYPE_LEVEL_HIGH>, 3478 <GIC_SPI 169 IRQ_TYPE_LEVEL_HIGH>, 3479 <GIC_SPI 943 IRQ_TYPE_LEVEL_HIGH>; 3480 interrupt-names = "msi0", 3481 "msi1", 3482 "msi2", 3483 "msi3", 3484 "msi4", 3485 "msi5", 3486 "msi6", 3487 "msi7", 3488 "global"; 3489 3490 #interrupt-cells = <1>; 3491 interrupt-map-mask = <0 0 0 0x7>; 3492 interrupt-map = <0 0 0 1 &intc 0 0 GIC_SPI 831 IRQ_TYPE_LEVEL_HIGH>, 3493 <0 0 0 2 &intc 0 0 GIC_SPI 832 IRQ_TYPE_LEVEL_HIGH>, 3494 <0 0 0 3 &intc 0 0 GIC_SPI 833 IRQ_TYPE_LEVEL_HIGH>, 3495 <0 0 0 4 &intc 0 0 GIC_SPI 834 IRQ_TYPE_LEVEL_HIGH>; 3496 3497 clocks = <&gcc GCC_PCIE_3B_AUX_CLK>, 3498 <&gcc GCC_PCIE_3B_CFG_AHB_CLK>, 3499 <&gcc GCC_PCIE_3B_MSTR_AXI_CLK>, 3500 <&gcc GCC_PCIE_3B_SLV_AXI_CLK>, 3501 <&gcc GCC_PCIE_3B_SLV_Q2A_AXI_CLK>, 3502 <&gcc GCC_AGGRE_NOC_PCIE_3B_WEST_SF_AXI_CLK>; 3503 clock-names = "aux", 3504 "cfg", 3505 "bus_master", 3506 "bus_slave", 3507 "slave_q2a", 3508 "noc_aggr"; 3509 3510 assigned-clocks = <&gcc GCC_PCIE_3B_AUX_CLK>; 3511 assigned-clock-rates = <19200000>; 3512 3513 interconnects = <&pcie_west_anoc MASTER_PCIE_3B QCOM_ICC_TAG_ALWAYS 3514 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>, 3515 <&hsc_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 3516 &pcie_west_slv_noc SLAVE_PCIE_3B QCOM_ICC_TAG_ALWAYS>; 3517 interconnect-names = "pcie-mem", 3518 "cpu-pcie"; 3519 3520 resets = <&gcc GCC_PCIE_3B_BCR>, 3521 <&gcc GCC_PCIE_3B_LINK_DOWN_BCR>; 3522 reset-names = "pci", 3523 "link_down"; 3524 3525 power-domains = <&gcc GCC_PCIE_3B_GDSC>; 3526 3527 eq-presets-8gts = /bits/ 16 <0x5555 0x5555 0x5555 0x5555>; 3528 eq-presets-16gts = /bits/ 8 <0x55 0x55 0x55 0x55>; 3529 eq-presets-32gts = /bits/ 8 <0x55 0x55 0x55 0x55>; 3530 3531 status = "disabled"; 3532 3533 pcie3b_opp_table: opp-table { 3534 compatible = "operating-points-v2"; 3535 3536 /* GEN 1 x1 */ 3537 opp-2500000-1 { 3538 opp-hz = /bits/ 64 <2500000>; 3539 required-opps = <&rpmhpd_opp_low_svs>; 3540 opp-peak-kBps = <250000 1>; 3541 opp-level = <1>; 3542 }; 3543 3544 /* GEN 1 x2 */ 3545 opp-5000000-1 { 3546 opp-hz = /bits/ 64 <5000000>; 3547 required-opps = <&rpmhpd_opp_low_svs>; 3548 opp-peak-kBps = <500000 1>; 3549 opp-level = <1>; 3550 }; 3551 3552 /* GEN 1 x4 */ 3553 opp-10000000-1 { 3554 opp-hz = /bits/ 64 <10000000>; 3555 required-opps = <&rpmhpd_opp_low_svs>; 3556 opp-peak-kBps = <1000000 1>; 3557 opp-level = <1>; 3558 }; 3559 3560 /* GEN 2 x1 */ 3561 opp-5000000-2 { 3562 opp-hz = /bits/ 64 <5000000>; 3563 required-opps = <&rpmhpd_opp_low_svs>; 3564 opp-peak-kBps = <500000 1>; 3565 opp-level = <2>; 3566 }; 3567 3568 /* GEN 2 x2 */ 3569 opp-10000000-2 { 3570 opp-hz = /bits/ 64 <10000000>; 3571 required-opps = <&rpmhpd_opp_low_svs>; 3572 opp-peak-kBps = <1000000 1>; 3573 opp-level = <2>; 3574 }; 3575 3576 /* GEN 2 x4 */ 3577 opp-20000000-2 { 3578 opp-hz = /bits/ 64 <20000000>; 3579 required-opps = <&rpmhpd_opp_low_svs>; 3580 opp-peak-kBps = <2000000 1>; 3581 opp-level = <2>; 3582 }; 3583 3584 /* GEN 3 x1 */ 3585 opp-8000000-3 { 3586 opp-hz = /bits/ 64 <8000000>; 3587 required-opps = <&rpmhpd_opp_low_svs>; 3588 opp-peak-kBps = <984500 1>; 3589 opp-level = <3>; 3590 }; 3591 3592 /* GEN 3 x2 */ 3593 opp-16000000-3 { 3594 opp-hz = /bits/ 64 <16000000>; 3595 required-opps = <&rpmhpd_opp_low_svs>; 3596 opp-peak-kBps = <1969000 1>; 3597 opp-level = <3>; 3598 }; 3599 3600 /* GEN 3 x4 */ 3601 opp-32000000-3 { 3602 opp-hz = /bits/ 64 <32000000>; 3603 required-opps = <&rpmhpd_opp_low_svs>; 3604 opp-peak-kBps = <3938000 1>; 3605 opp-level = <3>; 3606 }; 3607 3608 /* GEN 4 x1 */ 3609 opp-16000000-4 { 3610 opp-hz = /bits/ 64 <16000000>; 3611 required-opps = <&rpmhpd_opp_svs>; 3612 opp-peak-kBps = <1969000 1>; 3613 opp-level = <4>; 3614 }; 3615 3616 /* GEN 4 x2 */ 3617 opp-32000000-4 { 3618 opp-hz = /bits/ 64 <32000000>; 3619 required-opps = <&rpmhpd_opp_svs>; 3620 opp-peak-kBps = <3938000 1>; 3621 opp-level = <4>; 3622 }; 3623 3624 /* GEN 4 x4 */ 3625 opp-64000000-4 { 3626 opp-hz = /bits/ 64 <64000000>; 3627 required-opps = <&rpmhpd_opp_svs>; 3628 opp-peak-kBps = <7876000 1>; 3629 opp-level = <4>; 3630 }; 3631 3632 /* GEN 5 x1 */ 3633 opp-32000000-5 { 3634 opp-hz = /bits/ 64 <32000000>; 3635 required-opps = <&rpmhpd_opp_nom>; 3636 opp-peak-kBps = <3938000 1>; 3637 opp-level = <5>; 3638 }; 3639 3640 /* GEN 5 x2 */ 3641 opp-64000000-5 { 3642 opp-hz = /bits/ 64 <64000000>; 3643 required-opps = <&rpmhpd_opp_nom>; 3644 opp-peak-kBps = <7876000 1>; 3645 opp-level = <5>; 3646 }; 3647 3648 /* GEN 5 x4 */ 3649 opp-128000000-5 { 3650 opp-hz = /bits/ 64 <128000000>; 3651 required-opps = <&rpmhpd_opp_nom>; 3652 opp-peak-kBps = <15753000 1>; 3653 opp-level = <5>; 3654 }; 3655 }; 3656 3657 pcie3b_port0: pcie@0 { 3658 device_type = "pci"; 3659 reg = <0x0 0x0 0x0 0x0 0x0>; 3660 bus-range = <0x01 0xff>; 3661 3662 phys = <&pcie3b_phy>; 3663 3664 #address-cells = <3>; 3665 #size-cells = <2>; 3666 ranges; 3667 }; 3668 }; 3669 3670 pcie3b_phy: phy@f10000 { 3671 compatible = "qcom,glymur-qmp-gen5x4-pcie-phy"; 3672 reg = <0x0 0x00f10000 0x0 0x10000>; 3673 3674 clocks = <&gcc GCC_PCIE_PHY_3B_AUX_CLK>, 3675 <&gcc GCC_PCIE_3B_CFG_AHB_CLK>, 3676 <&tcsr TCSR_PCIE_3_CLKREF_EN>, 3677 <&gcc GCC_PCIE_3B_PHY_RCHNG_CLK>, 3678 <&gcc GCC_PCIE_3B_PIPE_CLK>, 3679 <&gcc GCC_PCIE_3B_PIPE_DIV2_CLK>; 3680 clock-names = "aux", 3681 "cfg_ahb", 3682 "ref", 3683 "rchng", 3684 "pipe", 3685 "pipediv2"; 3686 3687 resets = <&gcc GCC_PCIE_3B_PHY_BCR>, 3688 <&gcc GCC_PCIE_3B_NOCSR_COM_PHY_BCR>; 3689 reset-names = "phy", 3690 "phy_nocsr"; 3691 3692 assigned-clocks = <&gcc GCC_PCIE_3B_PHY_RCHNG_CLK>; 3693 assigned-clock-rates = <100000000>; 3694 3695 power-domains = <&gcc GCC_PCIE_3B_PHY_GDSC>; 3696 3697 #clock-cells = <0>; 3698 clock-output-names = "pcie3b_pipe_clk"; 3699 3700 #phy-cells = <0>; 3701 3702 status = "disabled"; 3703 }; 3704 3705 cryptobam: dma-controller@1dc4000 { 3706 compatible = "qcom,bam-v1.7.4", "qcom,bam-v1.7.0"; 3707 reg = <0x0 0x01dc4000 0x0 0x28000>; 3708 interrupts = <GIC_SPI 272 IRQ_TYPE_LEVEL_HIGH>; 3709 #dma-cells = <1>; 3710 iommus = <&apps_smmu 0x80 0x0>, 3711 <&apps_smmu 0x81 0x0>; 3712 qcom,ee = <0>; 3713 qcom,controlled-remotely; 3714 num-channels = <20>; 3715 qcom,num-ees = <4>; 3716 }; 3717 3718 crypto: crypto@1dfa000 { 3719 compatible = "qcom,glymur-qce", "qcom,sm8150-qce", "qcom,qce"; 3720 reg = <0x0 0x01dfa000 0x0 0x6000>; 3721 dmas = <&cryptobam 4>, <&cryptobam 5>; 3722 dma-names = "rx", 3723 "tx"; 3724 iommus = <&apps_smmu 0x80 0x0>, 3725 <&apps_smmu 0x81 0x0>; 3726 interconnects = <&aggre1_noc MASTER_CRYPTO QCOM_ICC_TAG_ALWAYS 3727 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 3728 interconnect-names = "memory"; 3729 }; 3730 3731 tcsr_mutex: hwlock@1f40000 { 3732 compatible = "qcom,tcsr-mutex"; 3733 reg = <0x0 0x01f40000 0x0 0x20000>; 3734 3735 #hwlock-cells = <1>; 3736 }; 3737 3738 tcsr: clock-controller@1fd5000 { 3739 compatible = "qcom,glymur-tcsr", 3740 "syscon"; 3741 reg = <0x0 0x1fd5000 0x0 0x21000>; 3742 clocks = <&rpmhcc RPMH_CXO_CLK>; 3743 #clock-cells = <1>; 3744 #reset-cells = <1>; 3745 }; 3746 3747 hsc_noc: interconnect@2000000 { 3748 compatible = "qcom,glymur-hscnoc"; 3749 reg = <0x0 0x02000000 0x0 0x93a080>; 3750 qcom,bcm-voters = <&apps_bcm_voter>; 3751 #interconnect-cells = <2>; 3752 }; 3753 3754 gxclkctl: clock-controller@3d64000 { 3755 compatible = "qcom,glymur-gxclkctl"; 3756 reg = <0x0 0x03d64000 0x0 0x6000>; 3757 3758 power-domains = <&rpmhpd RPMHPD_GFX>, 3759 <&rpmhpd RPMHPD_GMXC>, 3760 <&gpucc GPU_CC_CX_GDSC>; 3761 3762 #power-domain-cells = <1>; 3763 }; 3764 3765 gpucc: clock-controller@3d90000 { 3766 compatible = "qcom,glymur-gpucc"; 3767 reg = <0x0 0x03d90000 0x0 0x9800>; 3768 clocks = <&rpmhcc RPMH_CXO_CLK>, 3769 <&gcc GCC_GPU_GPLL0_CLK_SRC>, 3770 <&gcc GCC_GPU_GPLL0_DIV_CLK_SRC>; 3771 3772 power-domains = <&rpmhpd RPMHPD_MX>, 3773 <&rpmhpd RPMHPD_CX>; 3774 required-opps = <&rpmhpd_opp_low_svs>, 3775 <&rpmhpd_opp_low_svs>; 3776 3777 #clock-cells = <1>; 3778 #reset-cells = <1>; 3779 #power-domain-cells = <1>; 3780 }; 3781 3782 ipcc: mailbox@3e04000 { 3783 compatible = "qcom,glymur-ipcc", "qcom,ipcc"; 3784 reg = <0x0 0x03e04000 0x0 0x1000>; 3785 3786 interrupts = <GIC_SPI 229 IRQ_TYPE_LEVEL_HIGH>; 3787 interrupt-controller; 3788 #interrupt-cells = <3>; 3789 3790 #mbox-cells = <2>; 3791 }; 3792 3793 remoteproc_adsp: remoteproc@6800000 { 3794 compatible = "qcom,glymur-adsp-pas", "qcom,sm8550-adsp-pas"; 3795 reg = <0x0 0x06800000 0x0 0x10000>; 3796 3797 iommus = <&apps_smmu 0x1000 0x0>; 3798 3799 interrupts-extended = <&pdc 6 IRQ_TYPE_EDGE_RISING>, 3800 <&smp2p_adsp_in 0 IRQ_TYPE_EDGE_RISING>, 3801 <&smp2p_adsp_in 1 IRQ_TYPE_EDGE_RISING>, 3802 <&smp2p_adsp_in 2 IRQ_TYPE_EDGE_RISING>, 3803 <&smp2p_adsp_in 3 IRQ_TYPE_EDGE_RISING>, 3804 <&smp2p_adsp_in 7 IRQ_TYPE_EDGE_RISING>; 3805 interrupt-names = "wdog", 3806 "fatal", 3807 "ready", 3808 "handover", 3809 "stop-ack", 3810 "shutdown-ack"; 3811 3812 clocks = <&rpmhcc RPMH_CXO_CLK>; 3813 clock-names = "xo"; 3814 3815 interconnects = <&lpass_lpicx_noc MASTER_LPASS_PROC QCOM_ICC_TAG_ALWAYS 3816 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 3817 3818 power-domains = <&rpmhpd RPMHPD_LCX>, 3819 <&rpmhpd RPMHPD_LMX>; 3820 power-domain-names = "lcx", 3821 "lmx"; 3822 3823 memory-region = <&adspslpi_mem>, <&q6_adsp_dtb_mem>; 3824 3825 qcom,qmp = <&aoss_qmp>; 3826 3827 qcom,smem-states = <&smp2p_adsp_out 0>; 3828 qcom,smem-state-names = "stop"; 3829 3830 status = "disabled"; 3831 3832 remoteproc_adsp_glink: glink-edge { 3833 interrupts-extended = <&ipcc IPCC_MPROC_LPASS 3834 IPCC_MPROC_SIGNAL_GLINK_QMP 3835 IRQ_TYPE_EDGE_RISING>; 3836 3837 mboxes = <&ipcc IPCC_MPROC_LPASS 3838 IPCC_MPROC_SIGNAL_GLINK_QMP>; 3839 3840 qcom,remote-pid = <2>; 3841 3842 label = "lpass"; 3843 3844 fastrpc { 3845 compatible = "qcom,glymur-fastrpc", "qcom,kaanapali-fastrpc"; 3846 qcom,glink-channels = "fastrpcglink-apps-dsp"; 3847 label = "adsp"; 3848 #address-cells = <1>; 3849 #size-cells = <0>; 3850 3851 compute-cb@3 { 3852 compatible = "qcom,fastrpc-compute-cb"; 3853 reg = <3>; 3854 3855 iommus = <&apps_smmu 0x1003 0x80>, 3856 <&apps_smmu 0x1063 0x20>; 3857 dma-coherent; 3858 }; 3859 3860 compute-cb@4 { 3861 compatible = "qcom,fastrpc-compute-cb"; 3862 reg = <4>; 3863 3864 iommus = <&apps_smmu 0x1004 0x80>, 3865 <&apps_smmu 0x1064 0x20>; 3866 dma-coherent; 3867 }; 3868 3869 compute-cb@5 { 3870 compatible = "qcom,fastrpc-compute-cb"; 3871 reg = <5>; 3872 3873 iommus = <&apps_smmu 0x1005 0x80>, 3874 <&apps_smmu 0x1065 0x20>; 3875 dma-coherent; 3876 }; 3877 3878 compute-cb@6 { 3879 compatible = "qcom,fastrpc-compute-cb"; 3880 reg = <6>; 3881 3882 iommus = <&apps_smmu 0x1006 0x80>, 3883 <&apps_smmu 0x1066 0x20>; 3884 dma-coherent; 3885 }; 3886 3887 compute-cb@7 { 3888 compatible = "qcom,fastrpc-compute-cb"; 3889 reg = <7>; 3890 3891 iommus = <&apps_smmu 0x1007 0x40>, 3892 <&apps_smmu 0x1067 0x0>, 3893 <&apps_smmu 0x1087 0x0>; 3894 dma-coherent; 3895 }; 3896 3897 compute-cb@8 { 3898 compatible = "qcom,fastrpc-compute-cb"; 3899 reg = <8>; 3900 3901 iommus = <&apps_smmu 0x1008 0x80>, 3902 <&apps_smmu 0x1068 0x20>; 3903 dma-coherent; 3904 }; 3905 }; 3906 }; 3907 }; 3908 3909 lpass_lpiaon_noc: interconnect@7400000 { 3910 compatible = "qcom,glymur-lpass-lpiaon-noc"; 3911 reg = <0x0 0x07400000 0x0 0x19080>; 3912 qcom,bcm-voters = <&apps_bcm_voter>; 3913 #interconnect-cells = <2>; 3914 }; 3915 3916 lpass_lpicx_noc: interconnect@7420000 { 3917 compatible = "qcom,glymur-lpass-lpicx-noc"; 3918 reg = <0x0 0x07420000 0x0 0x44080>; 3919 qcom,bcm-voters = <&apps_bcm_voter>; 3920 #interconnect-cells = <2>; 3921 }; 3922 3923 lpass_ag_noc: interconnect@7e40000 { 3924 compatible = "qcom,glymur-lpass-ag-noc"; 3925 reg = <0x0 0x07e40000 0x0 0xe080>; 3926 qcom,bcm-voters = <&apps_bcm_voter>; 3927 #interconnect-cells = <2>; 3928 }; 3929 3930 usb_2_hsphy: phy@88e0000 { 3931 compatible = "qcom,glymur-m31-eusb2-phy", 3932 "qcom,sm8750-m31-eusb2-phy"; 3933 3934 reg = <0x0 0x088e0000 0x0 0x29c>; 3935 #phy-cells = <0>; 3936 3937 clocks = <&tcsr TCSR_USB2_4_CLKREF_EN>; 3938 clock-names = "ref"; 3939 3940 resets = <&gcc GCC_QUSB2PHY_TERT_BCR>; 3941 3942 status = "disabled"; 3943 }; 3944 3945 usb_2_qmpphy: phy@88e1000 { 3946 compatible = "qcom,glymur-qmp-usb3-dp-phy"; 3947 reg = <0x0 0x088e1000 0x0 0x8000>; 3948 3949 clocks = <&gcc GCC_USB3_TERT_PHY_AUX_CLK>, 3950 <&tcsr TCSR_USB4_2_CLKREF_EN>, 3951 <&gcc GCC_USB3_TERT_PHY_COM_AUX_CLK>, 3952 <&gcc GCC_USB3_TERT_PHY_PIPE_CLK>; 3953 clock-names = "aux", 3954 "ref", 3955 "com_aux", 3956 "usb3_pipe"; 3957 3958 power-domains = <&gcc GCC_USB_2_PHY_GDSC>; 3959 3960 resets = <&gcc GCC_USB3_PHY_TERT_BCR>, 3961 <&gcc GCC_USB3PHY_PHY_TERT_BCR>; 3962 reset-names = "phy", 3963 "common"; 3964 3965 #clock-cells = <1>; 3966 #phy-cells = <1>; 3967 3968 mode-switch; 3969 orientation-switch; 3970 3971 status = "disabled"; 3972 3973 ports { 3974 #address-cells = <1>; 3975 #size-cells = <0>; 3976 3977 port@0 { 3978 reg = <0>; 3979 3980 usb_2_qmpphy_out: endpoint { 3981 }; 3982 }; 3983 3984 port@1 { 3985 reg = <1>; 3986 3987 usb_2_qmpphy_usb_ss_in: endpoint { 3988 remote-endpoint = <&usb_2_dwc3_ss>; 3989 }; 3990 }; 3991 3992 port@2 { 3993 reg = <2>; 3994 3995 usb_2_qmpphy_dp_in: endpoint { 3996 remote-endpoint = <&mdss_dp2_out>; 3997 }; 3998 }; 3999 }; 4000 }; 4001 4002 usb_0: usb@a600000 { 4003 compatible = "qcom,glymur-dwc3", "qcom,snps-dwc3"; 4004 reg = <0x0 0x0a600000 0x0 0xfc100>; 4005 4006 clocks = <&gcc GCC_CFG_NOC_USB3_PRIM_AXI_CLK>, 4007 <&gcc GCC_USB30_PRIM_MASTER_CLK>, 4008 <&gcc GCC_AGGRE_USB3_PRIM_AXI_CLK>, 4009 <&gcc GCC_USB30_PRIM_SLEEP_CLK>, 4010 <&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>, 4011 <&gcc GCC_CFG_NOC_USB_ANOC_AHB_CLK>, 4012 <&gcc GCC_CFG_NOC_USB_ANOC_SOUTH_AHB_CLK>; 4013 clock-names = "cfg_noc", 4014 "core", 4015 "iface", 4016 "sleep", 4017 "mock_utmi", 4018 "noc_aggr_north", 4019 "noc_aggr_south"; 4020 4021 interrupts-extended = <&intc GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>, 4022 <&intc GIC_SPI 371 IRQ_TYPE_LEVEL_HIGH>, 4023 <&pdc 90 IRQ_TYPE_EDGE_BOTH>, 4024 <&pdc 60 IRQ_TYPE_EDGE_BOTH>, 4025 <&pdc 17 IRQ_TYPE_EDGE_BOTH>; 4026 interrupt-names = "dwc_usb3", 4027 "pwr_event", 4028 "dp_hs_phy_irq", 4029 "dm_hs_phy_irq", 4030 "ss_phy_irq"; 4031 4032 power-domains = <&gcc GCC_USB30_PRIM_GDSC>; 4033 resets = <&gcc GCC_USB30_PRIM_BCR>; 4034 4035 iommus = <&apps_smmu 0x1420 0x0>; 4036 phys = <&usb_0_hsphy>, 4037 <&usb_0_qmpphy QMP_USB43DP_USB3_PHY>; 4038 phy-names = "usb2-phy", 4039 "usb3-phy"; 4040 4041 snps,hird-threshold = /bits/ 8 <0x0>; 4042 snps,dis-u1-entry-quirk; 4043 snps,dis-u2-entry-quirk; 4044 snps,is-utmi-l1-suspend; 4045 snps,usb3_lpm_capable; 4046 snps,has-lpm-erratum; 4047 tx-fifo-resize; 4048 snps,dis_u2_susphy_quirk; 4049 snps,dis_enblslpm_quirk; 4050 4051 usb-role-switch; 4052 4053 status = "disabled"; 4054 4055 ports { 4056 #address-cells = <1>; 4057 #size-cells = <0>; 4058 4059 port@0 { 4060 reg = <0>; 4061 4062 usb_0_dwc3_hs: endpoint { 4063 }; 4064 }; 4065 4066 port@1 { 4067 reg = <1>; 4068 4069 usb_0_dwc3_ss: endpoint { 4070 remote-endpoint = <&usb_0_qmpphy_usb_ss_in>; 4071 }; 4072 }; 4073 }; 4074 }; 4075 4076 usb_1: usb@a800000 { 4077 compatible = "qcom,glymur-dwc3", "qcom,snps-dwc3"; 4078 reg = <0x0 0x0a800000 0x0 0xfc100>; 4079 4080 clocks = <&gcc GCC_CFG_NOC_USB3_SEC_AXI_CLK>, 4081 <&gcc GCC_USB30_SEC_MASTER_CLK>, 4082 <&gcc GCC_AGGRE_USB3_SEC_AXI_CLK>, 4083 <&gcc GCC_USB30_SEC_SLEEP_CLK>, 4084 <&gcc GCC_USB30_SEC_MOCK_UTMI_CLK>, 4085 <&gcc GCC_CFG_NOC_USB_ANOC_AHB_CLK>, 4086 <&gcc GCC_CFG_NOC_USB_ANOC_SOUTH_AHB_CLK>; 4087 clock-names = "cfg_noc", 4088 "core", 4089 "iface", 4090 "sleep", 4091 "mock_utmi", 4092 "noc_aggr_north", 4093 "noc_aggr_south"; 4094 4095 interrupts-extended = <&intc GIC_SPI 875 IRQ_TYPE_LEVEL_HIGH>, 4096 <&intc GIC_SPI 369 IRQ_TYPE_LEVEL_HIGH>, 4097 <&pdc 88 IRQ_TYPE_EDGE_BOTH>, 4098 <&pdc 87 IRQ_TYPE_EDGE_BOTH>, 4099 <&pdc 76 IRQ_TYPE_EDGE_BOTH>; 4100 interrupt-names = "dwc_usb3", 4101 "pwr_event", 4102 "dp_hs_phy_irq", 4103 "dm_hs_phy_irq", 4104 "ss_phy_irq"; 4105 4106 resets = <&gcc GCC_USB30_SEC_BCR>; 4107 power-domains = <&gcc GCC_USB30_SEC_GDSC>; 4108 4109 iommus = <&apps_smmu 0x1460 0x0>; 4110 4111 phys = <&usb_1_hsphy>, 4112 <&usb_1_qmpphy QMP_USB43DP_USB3_PHY>; 4113 phy-names = "usb2-phy", 4114 "usb3-phy"; 4115 4116 snps,hird-threshold = /bits/ 8 <0x0>; 4117 snps,dis-u1-entry-quirk; 4118 snps,dis-u2-entry-quirk; 4119 snps,is-utmi-l1-suspend; 4120 snps,usb3_lpm_capable; 4121 snps,has-lpm-erratum; 4122 tx-fifo-resize; 4123 snps,dis_u2_susphy_quirk; 4124 snps,dis_enblslpm_quirk; 4125 4126 usb-role-switch; 4127 4128 status = "disabled"; 4129 4130 ports { 4131 #address-cells = <1>; 4132 #size-cells = <0>; 4133 4134 port@0 { 4135 reg = <0>; 4136 4137 usb_1_dwc3_hs: endpoint { 4138 }; 4139 }; 4140 4141 port@1 { 4142 reg = <1>; 4143 4144 usb_1_dwc3_ss: endpoint { 4145 remote-endpoint = <&usb_1_qmpphy_usb_ss_in>; 4146 }; 4147 }; 4148 }; 4149 }; 4150 4151 usb_2: usb@a000000 { 4152 compatible = "qcom,glymur-dwc3", "qcom,snps-dwc3"; 4153 reg = <0x0 0x0a000000 0x0 0xfc100>; 4154 4155 clocks = <&gcc GCC_CFG_NOC_USB3_TERT_AXI_CLK>, 4156 <&gcc GCC_USB30_TERT_MASTER_CLK>, 4157 <&gcc GCC_AGGRE_USB3_TERT_AXI_CLK>, 4158 <&gcc GCC_USB30_TERT_SLEEP_CLK>, 4159 <&gcc GCC_USB30_TERT_MOCK_UTMI_CLK>, 4160 <&gcc GCC_CFG_NOC_USB_ANOC_AHB_CLK>, 4161 <&gcc GCC_CFG_NOC_USB_ANOC_SOUTH_AHB_CLK>; 4162 clock-names = "cfg_noc", 4163 "core", 4164 "iface", 4165 "sleep", 4166 "mock_utmi", 4167 "noc_aggr_north", 4168 "noc_aggr_south"; 4169 4170 interrupts-extended = <&intc GIC_SPI 871 IRQ_TYPE_LEVEL_HIGH>, 4171 <&intc GIC_SPI 370 IRQ_TYPE_LEVEL_HIGH>, 4172 <&pdc 89 IRQ_TYPE_EDGE_BOTH>, 4173 <&pdc 81 IRQ_TYPE_EDGE_BOTH>, 4174 <&pdc 75 IRQ_TYPE_EDGE_BOTH>; 4175 interrupt-names = "dwc_usb3", 4176 "pwr_event", 4177 "dp_hs_phy_irq", 4178 "dm_hs_phy_irq", 4179 "ss_phy_irq"; 4180 4181 resets = <&gcc GCC_USB30_TERT_BCR>; 4182 power-domains = <&gcc GCC_USB30_TERT_GDSC>; 4183 4184 iommus = <&apps_smmu 0x420 0x0>; 4185 4186 phys = <&usb_2_hsphy>, 4187 <&usb_2_qmpphy QMP_USB43DP_USB3_PHY>; 4188 phy-names = "usb2-phy", 4189 "usb3-phy"; 4190 4191 snps,hird-threshold = /bits/ 8 <0x0>; 4192 snps,dis-u1-entry-quirk; 4193 snps,dis-u2-entry-quirk; 4194 snps,is-utmi-l1-suspend; 4195 snps,usb3_lpm_capable; 4196 snps,has-lpm-erratum; 4197 tx-fifo-resize; 4198 snps,dis_u2_susphy_quirk; 4199 snps,dis_enblslpm_quirk; 4200 4201 usb-role-switch; 4202 4203 status = "disabled"; 4204 4205 ports { 4206 #address-cells = <1>; 4207 #size-cells = <0>; 4208 4209 port@0 { 4210 reg = <0>; 4211 4212 usb_2_dwc3_hs: endpoint { 4213 }; 4214 }; 4215 4216 port@1 { 4217 reg = <1>; 4218 4219 usb_2_dwc3_ss: endpoint { 4220 remote-endpoint = <&usb_2_qmpphy_usb_ss_in>; 4221 }; 4222 }; 4223 }; 4224 }; 4225 4226 usb_hs: usb@a200000 { 4227 compatible = "qcom,glymur-dwc3", "qcom,snps-dwc3"; 4228 reg = <0x0 0x0a200000 0x0 0xfc100>; 4229 4230 clocks = <&gcc GCC_CFG_NOC_USB2_PRIM_AXI_CLK>, 4231 <&gcc GCC_USB20_MASTER_CLK>, 4232 <&gcc GCC_AGGRE_USB2_PRIM_AXI_CLK>, 4233 <&gcc GCC_USB20_SLEEP_CLK>, 4234 <&gcc GCC_USB20_MOCK_UTMI_CLK>, 4235 <&gcc GCC_CFG_NOC_USB_ANOC_AHB_CLK>, 4236 <&gcc GCC_CFG_NOC_USB_ANOC_SOUTH_AHB_CLK>; 4237 clock-names = "cfg_noc", 4238 "core", 4239 "iface", 4240 "sleep", 4241 "mock_utmi", 4242 "noc_aggr_north", 4243 "noc_aggr_south"; 4244 4245 assigned-clocks = <&gcc GCC_USB20_MOCK_UTMI_CLK>, 4246 <&gcc GCC_USB20_MASTER_CLK>; 4247 assigned-clock-rates = <19200000>, <200000000>; 4248 4249 interrupts-extended = <&intc GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 4250 <&intc GIC_SPI 246 IRQ_TYPE_LEVEL_HIGH>, 4251 <&pdc 92 IRQ_TYPE_EDGE_BOTH>, 4252 <&pdc 57 IRQ_TYPE_EDGE_BOTH>, 4253 <&intc GIC_SPI 239 IRQ_TYPE_LEVEL_HIGH>; 4254 interrupt-names = "dwc_usb3", 4255 "pwr_event", 4256 "dp_hs_phy_irq", 4257 "dm_hs_phy_irq", 4258 "hs_phy_irq"; 4259 4260 resets = <&gcc GCC_USB20_PRIM_BCR>; 4261 4262 power-domains = <&gcc GCC_USB20_PRIM_GDSC>; 4263 required-opps = <&rpmhpd_opp_nom>; 4264 4265 iommus = <&apps_smmu 0x0ce0 0x0>; 4266 4267 interconnects = <&aggre3_noc MASTER_USB2 QCOM_ICC_TAG_ALWAYS 4268 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>, 4269 <&hsc_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY 4270 &config_noc SLAVE_USB2 QCOM_ICC_TAG_ACTIVE_ONLY>; 4271 interconnect-names = "usb-ddr", 4272 "apps-usb"; 4273 4274 phys = <&usb_hs_phy>; 4275 phy-names = "usb2-phy"; 4276 4277 snps,hird-threshold = /bits/ 8 <0x0>; 4278 snps,dis-u1-entry-quirk; 4279 snps,dis-u2-entry-quirk; 4280 snps,is-utmi-l1-suspend; 4281 snps,usb3_lpm_capable; 4282 snps,has-lpm-erratum; 4283 tx-fifo-resize; 4284 snps,dis_u2_susphy_quirk; 4285 snps,dis_enblslpm_quirk; 4286 4287 dr_mode = "host"; 4288 4289 maximum-speed = "high-speed"; 4290 4291 status = "disabled"; 4292 }; 4293 4294 usb_mp: usb@a400000 { 4295 compatible = "qcom,glymur-dwc3-mp", "qcom,snps-dwc3"; 4296 reg = <0x0 0x0a400000 0x0 0xfc100>; 4297 4298 clocks = <&gcc GCC_CFG_NOC_USB3_MP_AXI_CLK>, 4299 <&gcc GCC_USB30_MP_MASTER_CLK>, 4300 <&gcc GCC_AGGRE_USB3_MP_AXI_CLK>, 4301 <&gcc GCC_USB30_MP_SLEEP_CLK>, 4302 <&gcc GCC_USB30_MP_MOCK_UTMI_CLK>, 4303 <&gcc GCC_CFG_NOC_USB_ANOC_AHB_CLK>, 4304 <&gcc GCC_CFG_NOC_USB_ANOC_SOUTH_AHB_CLK>; 4305 clock-names = "cfg_noc", 4306 "core", 4307 "iface", 4308 "sleep", 4309 "mock_utmi", 4310 "noc_aggr_north", 4311 "noc_aggr_south"; 4312 4313 interrupts-extended = <&intc GIC_SPI 132 IRQ_TYPE_LEVEL_HIGH>, 4314 <&intc GIC_SPI 345 IRQ_TYPE_LEVEL_HIGH>, 4315 <&intc GIC_SPI 346 IRQ_TYPE_LEVEL_HIGH>, 4316 <&intc GIC_SPI 162 IRQ_TYPE_LEVEL_HIGH>, 4317 <&intc GIC_SPI 163 IRQ_TYPE_LEVEL_HIGH>, 4318 <&pdc 12 IRQ_TYPE_LEVEL_HIGH>, 4319 <&pdc 11 IRQ_TYPE_LEVEL_HIGH>, 4320 <&pdc 14 IRQ_TYPE_LEVEL_HIGH>, 4321 <&pdc 13 IRQ_TYPE_LEVEL_HIGH>, 4322 <&pdc 78 IRQ_TYPE_LEVEL_HIGH>, 4323 <&pdc 77 IRQ_TYPE_LEVEL_HIGH>; 4324 interrupt-names = "dwc_usb3", 4325 "pwr_event_1", 4326 "pwr_event_2", 4327 "hs_phy_1", 4328 "hs_phy_2", 4329 "dp_hs_phy_1", 4330 "dm_hs_phy_1", 4331 "dp_hs_phy_2", 4332 "dm_hs_phy_2", 4333 "ss_phy_1", 4334 "ss_phy_2"; 4335 4336 resets = <&gcc GCC_USB30_MP_BCR>; 4337 power-domains = <&gcc GCC_USB30_MP_GDSC>; 4338 4339 iommus = <&apps_smmu 0xda0 0x0>; 4340 4341 phys = <&usb_mp_hsphy0>, 4342 <&usb_mp_qmpphy0>, 4343 <&usb_mp_hsphy1>, 4344 <&usb_mp_qmpphy1>; 4345 phy-names = "usb2-0", 4346 "usb3-0", 4347 "usb2-1", 4348 "usb3-1"; 4349 4350 snps,hird-threshold = /bits/ 8 <0x0>; 4351 snps,dis-u1-entry-quirk; 4352 snps,dis-u2-entry-quirk; 4353 snps,is-utmi-l1-suspend; 4354 snps,usb3_lpm_capable; 4355 snps,has-lpm-erratum; 4356 tx-fifo-resize; 4357 snps,dis_u2_susphy_quirk; 4358 snps,dis_enblslpm_quirk; 4359 4360 dr_mode = "host"; 4361 4362 status = "disabled"; 4363 }; 4364 4365 mdss: display-subsystem@ae00000 { 4366 compatible = "qcom,glymur-mdss"; 4367 reg = <0x0 0x0ae00000 0x0 0x1000>; 4368 reg-names = "mdss"; 4369 4370 interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>; 4371 4372 clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>, 4373 <&gcc GCC_DISP_HF_AXI_CLK>, 4374 <&dispcc DISP_CC_MDSS_MDP_CLK>; 4375 4376 resets = <&dispcc DISP_CC_MDSS_CORE_BCR>; 4377 4378 interconnects = <&mmss_noc MASTER_MDP QCOM_ICC_TAG_ALWAYS 4379 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>, 4380 <&hsc_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY 4381 &config_noc SLAVE_DISPLAY_CFG QCOM_ICC_TAG_ACTIVE_ONLY>; 4382 interconnect-names = "mdp0-mem", 4383 "cpu-cfg"; 4384 4385 power-domains = <&dispcc DISP_CC_MDSS_CORE_GDSC>; 4386 4387 iommus = <&apps_smmu 0x1de0 0x2>; 4388 4389 interrupt-controller; 4390 #interrupt-cells = <1>; 4391 4392 #address-cells = <2>; 4393 #size-cells = <2>; 4394 ranges; 4395 4396 status = "disabled"; 4397 4398 mdss_mdp: display-controller@ae01000 { 4399 compatible = "qcom,glymur-dpu"; 4400 reg = <0x0 0x0ae01000 0x0 0x93000>, 4401 <0x0 0x0aeb0000 0x0 0x3000>; 4402 reg-names = "mdp", 4403 "vbif"; 4404 4405 interrupts-extended = <&mdss 0>; 4406 4407 clocks = <&gcc GCC_DISP_HF_AXI_CLK>, 4408 <&dispcc DISP_CC_MDSS_AHB_CLK>, 4409 <&dispcc DISP_CC_MDSS_MDP_LUT_CLK>, 4410 <&dispcc DISP_CC_MDSS_MDP_CLK>, 4411 <&dispcc DISP_CC_MDSS_VSYNC_CLK>; 4412 clock-names = "nrt_bus", 4413 "iface", 4414 "lut", 4415 "core", 4416 "vsync"; 4417 4418 operating-points-v2 = <&mdp_opp_table>; 4419 4420 power-domains = <&rpmhpd RPMHPD_MMCX>; 4421 4422 ports { 4423 #address-cells = <1>; 4424 #size-cells = <0>; 4425 4426 port@0 { 4427 reg = <0>; 4428 4429 dpu_intf0_out: endpoint { 4430 remote-endpoint = <&mdss_dp0_in>; 4431 }; 4432 }; 4433 4434 port@4 { 4435 reg = <4>; 4436 4437 mdss_intf4_out: endpoint { 4438 remote-endpoint = <&mdss_dp1_in>; 4439 }; 4440 }; 4441 4442 port@5 { 4443 reg = <5>; 4444 4445 mdss_intf5_out: endpoint { 4446 remote-endpoint = <&mdss_dp3_in>; 4447 }; 4448 }; 4449 4450 port@6 { 4451 reg = <6>; 4452 4453 mdss_intf6_out: endpoint { 4454 remote-endpoint = <&mdss_dp2_in>; 4455 }; 4456 }; 4457 }; 4458 4459 mdp_opp_table: opp-table { 4460 compatible = "operating-points-v2"; 4461 4462 opp-156000000 { 4463 opp-hz = /bits/ 64 <156000000>; 4464 required-opps = <&rpmhpd_opp_low_svs_d1>; 4465 }; 4466 4467 opp-205000000 { 4468 opp-hz = /bits/ 64 <205000000>; 4469 required-opps = <&rpmhpd_opp_low_svs>; 4470 }; 4471 4472 opp-337000000 { 4473 opp-hz = /bits/ 64 <337000000>; 4474 required-opps = <&rpmhpd_opp_svs>; 4475 }; 4476 4477 opp-417000000 { 4478 opp-hz = /bits/ 64 <417000000>; 4479 required-opps = <&rpmhpd_opp_svs_l1>; 4480 }; 4481 4482 opp-532000000 { 4483 opp-hz = /bits/ 64 <532000000>; 4484 required-opps = <&rpmhpd_opp_nom>; 4485 }; 4486 4487 opp-600000000 { 4488 opp-hz = /bits/ 64 <600000000>; 4489 required-opps = <&rpmhpd_opp_nom_l1>; 4490 }; 4491 4492 opp-660000000 { 4493 opp-hz = /bits/ 64 <660000000>; 4494 required-opps = <&rpmhpd_opp_turbo>; 4495 }; 4496 4497 opp-717000000 { 4498 opp-hz = /bits/ 64 <717000000>; 4499 required-opps = <&rpmhpd_opp_turbo_l1>; 4500 }; 4501 }; 4502 }; 4503 4504 mdss_dp0: displayport-controller@af54000 { 4505 compatible = "qcom,glymur-dp"; 4506 reg = <0x0 0xaf54000 0x0 0x200>, 4507 <0x0 0xaf54200 0x0 0x200>, 4508 <0x0 0xaf55000 0x0 0xc00>, 4509 <0x0 0xaf56000 0x0 0x400>, 4510 <0x0 0xaf57000 0x0 0x400>, 4511 <0x0 0xaf58000 0x0 0x400>, 4512 <0x0 0xaf59000 0x0 0x400>, 4513 <0x0 0xaf5a000 0x0 0x600>, 4514 <0x0 0xaf5b000 0x0 0x600>; 4515 4516 interrupts-extended = <&mdss 12>; 4517 4518 clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>, 4519 <&dispcc DISP_CC_MDSS_DPTX0_AUX_CLK>, 4520 <&dispcc DISP_CC_MDSS_DPTX0_LINK_CLK>, 4521 <&dispcc DISP_CC_MDSS_DPTX0_LINK_INTF_CLK>, 4522 <&dispcc DISP_CC_MDSS_DPTX0_PIXEL0_CLK>, 4523 <&dispcc DISP_CC_MDSS_DPTX0_PIXEL1_CLK>; 4524 clock-names = "core_iface", 4525 "core_aux", 4526 "ctrl_link", 4527 "ctrl_link_iface", 4528 "stream_pixel", 4529 "stream_1_pixel"; 4530 4531 assigned-clocks = <&dispcc DISP_CC_MDSS_DPTX0_LINK_CLK_SRC>, 4532 <&dispcc DISP_CC_MDSS_DPTX0_PIXEL0_CLK_SRC>, 4533 <&dispcc DISP_CC_MDSS_DPTX0_PIXEL1_CLK_SRC>; 4534 assigned-clock-parents = <&usb_0_qmpphy QMP_USB43DP_DP_LINK_CLK>, 4535 <&usb_0_qmpphy QMP_USB43DP_DP_VCO_DIV_CLK>, 4536 <&usb_0_qmpphy QMP_USB43DP_DP_VCO_DIV_CLK>; 4537 4538 operating-points-v2 = <&mdss_dp0_opp_table>; 4539 4540 power-domains = <&rpmhpd RPMHPD_MMCX>; 4541 4542 phys = <&usb_0_qmpphy QMP_USB43DP_DP_PHY>; 4543 phy-names = "dp"; 4544 4545 #sound-dai-cells = <0>; 4546 4547 status = "disabled"; 4548 4549 ports { 4550 #address-cells = <1>; 4551 #size-cells = <0>; 4552 4553 port@0 { 4554 reg = <0>; 4555 4556 mdss_dp0_in: endpoint { 4557 remote-endpoint = <&dpu_intf0_out>; 4558 }; 4559 }; 4560 4561 port@1 { 4562 reg = <1>; 4563 4564 mdss_dp0_out: endpoint { 4565 remote-endpoint = <&usb_dp_qmpphy_dp_in>; 4566 }; 4567 }; 4568 }; 4569 4570 mdss_dp0_opp_table: opp-table { 4571 compatible = "operating-points-v2"; 4572 4573 opp-270000000 { 4574 opp-hz = /bits/ 64 <270000000>; 4575 required-opps = <&rpmhpd_opp_low_svs>; 4576 }; 4577 4578 opp-540000000 { 4579 opp-hz = /bits/ 64 <540000000>; 4580 required-opps = <&rpmhpd_opp_svs>; 4581 }; 4582 4583 opp-675000000 { 4584 opp-hz = /bits/ 64 <675000000>; 4585 required-opps = <&rpmhpd_opp_svs_l1>; 4586 }; 4587 4588 opp-810000000 { 4589 opp-hz = /bits/ 64 <810000000>; 4590 required-opps = <&rpmhpd_opp_nom>; 4591 }; 4592 }; 4593 }; 4594 4595 mdss_dp1: displayport-controller@af5c000 { 4596 compatible = "qcom,glymur-dp"; 4597 reg = <0x0 0xaf5c000 0x0 0x200>, 4598 <0x0 0xaf5c200 0x0 0x200>, 4599 <0x0 0xaf5d000 0x0 0xc00>, 4600 <0x0 0xaf5e000 0x0 0x400>, 4601 <0x0 0xaf5f000 0x0 0x400>, 4602 <0x0 0xaf60000 0x0 0x400>, 4603 <0x0 0xaf61000 0x0 0x400>, 4604 <0x0 0xaf62000 0x0 0x600>, 4605 <0x0 0xaf63000 0x0 0x600>; 4606 4607 interrupts-extended = <&mdss 13>; 4608 4609 clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>, 4610 <&dispcc DISP_CC_MDSS_DPTX1_AUX_CLK>, 4611 <&dispcc DISP_CC_MDSS_DPTX1_LINK_CLK>, 4612 <&dispcc DISP_CC_MDSS_DPTX1_LINK_INTF_CLK>, 4613 <&dispcc DISP_CC_MDSS_DPTX1_PIXEL0_CLK>, 4614 <&dispcc DISP_CC_MDSS_DPTX1_PIXEL1_CLK>; 4615 clock-names = "core_iface", 4616 "core_aux", 4617 "ctrl_link", 4618 "ctrl_link_iface", 4619 "stream_pixel", 4620 "stream_1_pixel"; 4621 4622 assigned-clocks = <&dispcc DISP_CC_MDSS_DPTX1_LINK_CLK_SRC>, 4623 <&dispcc DISP_CC_MDSS_DPTX1_PIXEL0_CLK_SRC>, 4624 <&dispcc DISP_CC_MDSS_DPTX1_PIXEL1_CLK_SRC>; 4625 assigned-clock-parents = <&usb_1_qmpphy QMP_USB43DP_DP_LINK_CLK>, 4626 <&usb_1_qmpphy QMP_USB43DP_DP_VCO_DIV_CLK>, 4627 <&usb_1_qmpphy QMP_USB43DP_DP_VCO_DIV_CLK>; 4628 4629 operating-points-v2 = <&mdss_dp0_opp_table>; 4630 4631 power-domains = <&rpmhpd RPMHPD_MMCX>; 4632 4633 phys = <&usb_1_qmpphy QMP_USB43DP_DP_PHY>; 4634 phy-names = "dp"; 4635 4636 #sound-dai-cells = <0>; 4637 4638 status = "disabled"; 4639 4640 ports { 4641 #address-cells = <1>; 4642 #size-cells = <0>; 4643 4644 port@0 { 4645 reg = <0>; 4646 4647 mdss_dp1_in: endpoint { 4648 remote-endpoint = <&mdss_intf4_out>; 4649 }; 4650 }; 4651 4652 port@1 { 4653 reg = <1>; 4654 4655 mdss_dp1_out: endpoint { 4656 remote-endpoint = <&usb_1_qmpphy_dp_in>; 4657 }; 4658 }; 4659 }; 4660 }; 4661 4662 mdss_dp2: displayport-controller@af64000 { 4663 compatible = "qcom,glymur-dp"; 4664 reg = <0x0 0x0af64000 0x0 0x200>, 4665 <0x0 0x0af64200 0x0 0x200>, 4666 <0x0 0x0af65000 0x0 0xc00>, 4667 <0x0 0x0af66000 0x0 0x400>, 4668 <0x0 0x0af67000 0x0 0x400>, 4669 <0x0 0x0af68000 0x0 0x400>, 4670 <0x0 0x0af69000 0x0 0x400>, 4671 <0x0 0x0af6a000 0x0 0x600>, 4672 <0x0 0x0af6b000 0x0 0x600>; 4673 4674 interrupts-extended = <&mdss 14>; 4675 4676 clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>, 4677 <&dispcc DISP_CC_MDSS_DPTX2_AUX_CLK>, 4678 <&dispcc DISP_CC_MDSS_DPTX2_LINK_CLK>, 4679 <&dispcc DISP_CC_MDSS_DPTX2_LINK_INTF_CLK>, 4680 <&dispcc DISP_CC_MDSS_DPTX2_PIXEL0_CLK>, 4681 <&dispcc DISP_CC_MDSS_DPTX2_PIXEL1_CLK>; 4682 clock-names = "core_iface", 4683 "core_aux", 4684 "ctrl_link", 4685 "ctrl_link_iface", 4686 "stream_pixel", 4687 "stream_1_pixel"; 4688 4689 assigned-clocks = <&dispcc DISP_CC_MDSS_DPTX2_LINK_CLK_SRC>, 4690 <&dispcc DISP_CC_MDSS_DPTX2_PIXEL0_CLK_SRC>, 4691 <&dispcc DISP_CC_MDSS_DPTX2_PIXEL1_CLK_SRC>; 4692 assigned-clock-parents = <&usb_2_qmpphy QMP_USB43DP_DP_LINK_CLK>, 4693 <&usb_2_qmpphy QMP_USB43DP_DP_VCO_DIV_CLK>, 4694 <&usb_2_qmpphy QMP_USB43DP_DP_VCO_DIV_CLK>; 4695 4696 operating-points-v2 = <&mdss_dp0_opp_table>; 4697 4698 power-domains = <&rpmhpd RPMHPD_MMCX>; 4699 4700 phys = <&usb_2_qmpphy QMP_USB43DP_DP_PHY>; 4701 phy-names = "dp"; 4702 4703 #sound-dai-cells = <0>; 4704 4705 status = "disabled"; 4706 4707 ports { 4708 #address-cells = <1>; 4709 #size-cells = <0>; 4710 4711 port@0 { 4712 reg = <0>; 4713 mdss_dp2_in: endpoint { 4714 remote-endpoint = <&mdss_intf6_out>; 4715 }; 4716 }; 4717 4718 port@1 { 4719 reg = <1>; 4720 4721 mdss_dp2_out: endpoint { 4722 remote-endpoint = <&usb_2_qmpphy_dp_in>; 4723 }; 4724 }; 4725 }; 4726 }; 4727 4728 mdss_dp3: displayport-controller@af6c000 { 4729 compatible = "qcom,glymur-dp"; 4730 reg = <0x0 0x0af6c000 0x0 0x200>, 4731 <0x0 0x0af6c200 0x0 0x200>, 4732 <0x0 0x0af6d000 0x0 0xc00>, 4733 <0x0 0x0af6e000 0x0 0x400>, 4734 <0x0 0x0af6f000 0x0 0x400>, 4735 <0x0 0x0af70000 0x0 0x400>, 4736 <0x0 0x0af71000 0x0 0x400>, 4737 <0x0 0x0af72000 0x0 0x600>, 4738 <0x0 0x0af73000 0x0 0x600>; 4739 4740 interrupts-extended = <&mdss 15>; 4741 4742 clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>, 4743 <&dispcc DISP_CC_MDSS_DPTX3_AUX_CLK>, 4744 <&dispcc DISP_CC_MDSS_DPTX3_LINK_CLK>, 4745 <&dispcc DISP_CC_MDSS_DPTX3_LINK_INTF_CLK>, 4746 <&dispcc DISP_CC_MDSS_DPTX3_PIXEL0_CLK>; 4747 clock-names = "core_iface", 4748 "core_aux", 4749 "ctrl_link", 4750 "ctrl_link_iface", 4751 "stream_pixel"; 4752 4753 assigned-clocks = <&dispcc DISP_CC_MDSS_DPTX3_LINK_CLK_SRC>, 4754 <&dispcc DISP_CC_MDSS_DPTX3_PIXEL0_CLK_SRC>; 4755 assigned-clock-parents = <&mdss_dp3_phy 0>, 4756 <&mdss_dp3_phy 1>; 4757 4758 operating-points-v2 = <&mdss_dp0_opp_table>; 4759 4760 power-domains = <&rpmhpd RPMHPD_MMCX>; 4761 4762 phys = <&mdss_dp3_phy>; 4763 phy-names = "dp"; 4764 4765 #sound-dai-cells = <0>; 4766 4767 status = "disabled"; 4768 4769 ports { 4770 #address-cells = <1>; 4771 #size-cells = <0>; 4772 4773 port@0 { 4774 reg = <0>; 4775 4776 mdss_dp3_in: endpoint { 4777 remote-endpoint = <&mdss_intf5_out>; 4778 }; 4779 }; 4780 4781 port@1 { 4782 reg = <1>; 4783 4784 mdss_dp3_out: endpoint { 4785 }; 4786 }; 4787 }; 4788 }; 4789 }; 4790 4791 videocc: clock-controller@aaf0000 { 4792 compatible = "qcom,glymur-videocc"; 4793 reg = <0x0 0x0aaf0000 0x0 0x10000>; 4794 clocks = <&rpmhcc RPMH_CXO_CLK>, 4795 <&rpmhcc RPMH_CXO_CLK_A>; 4796 4797 power-domains = <&rpmhpd RPMHPD_MMCX>, 4798 <&rpmhpd RPMHPD_MXC>; 4799 required-opps = <&rpmhpd_opp_low_svs>, 4800 <&rpmhpd_opp_low_svs>; 4801 4802 #clock-cells = <1>; 4803 #reset-cells = <1>; 4804 #power-domain-cells = <1>; 4805 }; 4806 4807 dispcc: clock-controller@af00000 { 4808 compatible = "qcom,glymur-dispcc"; 4809 reg = <0x0 0x0af00000 0x0 0x20000>; 4810 clocks = <&rpmhcc RPMH_CXO_CLK>, 4811 <&sleep_clk>, 4812 <&usb_0_qmpphy QMP_USB43DP_DP_LINK_CLK>, /* dp0 */ 4813 <&usb_0_qmpphy QMP_USB43DP_DP_VCO_DIV_CLK>, 4814 <&usb_1_qmpphy QMP_USB43DP_DP_LINK_CLK>, /* dp1 */ 4815 <&usb_1_qmpphy QMP_USB43DP_DP_VCO_DIV_CLK>, 4816 <&usb_2_qmpphy QMP_USB43DP_DP_LINK_CLK>, /* dp2 */ 4817 <&usb_2_qmpphy QMP_USB43DP_DP_VCO_DIV_CLK>, 4818 <&mdss_dp3_phy 0>, /* dp3 */ 4819 <&mdss_dp3_phy 1>, 4820 <0>, /* dsi0 */ 4821 <0>, 4822 <0>, /* dsi1 */ 4823 <0>, 4824 <0>, 4825 <0>, 4826 <0>, 4827 <0>; 4828 power-domains = <&rpmhpd RPMHPD_MMCX>; 4829 required-opps = <&rpmhpd_opp_low_svs>; 4830 #clock-cells = <1>; 4831 #reset-cells = <1>; 4832 #power-domain-cells = <1>; 4833 }; 4834 4835 pdc: interrupt-controller@b220000 { 4836 compatible = "qcom,glymur-pdc", "qcom,pdc"; 4837 reg = <0x0 0x0b220000 0x0 0x10000>; 4838 qcom,pdc-ranges = <0 745 51>, 4839 <51 527 47>, 4840 <98 609 32>, 4841 <130 717 12>, 4842 <142 251 5>, 4843 <147 796 16>, 4844 <171 4104 36>; 4845 #interrupt-cells = <2>; 4846 interrupt-parent = <&intc>; 4847 interrupt-controller; 4848 }; 4849 4850 tsens0: thermal-sensor@c22c000 { 4851 compatible = "qcom,glymur-tsens", "qcom,tsens-v2"; 4852 reg = <0x0 0x0c22c000 0x0 0x1000>, 4853 <0x0 0x0c222000 0x0 0x1000>; 4854 4855 interrupts = <GIC_SPI 771 IRQ_TYPE_LEVEL_HIGH>, 4856 <GIC_SPI 861 IRQ_TYPE_LEVEL_HIGH>; 4857 interrupt-names = "uplow", 4858 "critical"; 4859 4860 #qcom,sensors = <13>; 4861 4862 #thermal-sensor-cells = <1>; 4863 }; 4864 4865 tsens1: thermal-sensor@c22d000 { 4866 compatible = "qcom,glymur-tsens", "qcom,tsens-v2"; 4867 reg = <0x0 0x0c22d000 0x0 0x1000>, 4868 <0x0 0x0c223000 0x0 0x1000>; 4869 4870 interrupts = <GIC_SPI 772 IRQ_TYPE_LEVEL_HIGH>, 4871 <GIC_SPI 862 IRQ_TYPE_LEVEL_HIGH>; 4872 interrupt-names = "uplow", 4873 "critical"; 4874 4875 #qcom,sensors = <9>; 4876 4877 #thermal-sensor-cells = <1>; 4878 }; 4879 4880 tsens2: thermal-sensor@c22e000 { 4881 compatible = "qcom,glymur-tsens", "qcom,tsens-v2"; 4882 reg = <0x0 0x0c22e000 0x0 0x1000>, 4883 <0x0 0x0c224000 0x0 0x1000>; 4884 4885 interrupts = <GIC_SPI 773 IRQ_TYPE_LEVEL_HIGH>, 4886 <GIC_SPI 863 IRQ_TYPE_LEVEL_HIGH>; 4887 interrupt-names = "uplow", 4888 "critical"; 4889 4890 #qcom,sensors = <13>; 4891 4892 #thermal-sensor-cells = <1>; 4893 }; 4894 4895 tsens3: thermal-sensor@c22f000 { 4896 compatible = "qcom,glymur-tsens", "qcom,tsens-v2"; 4897 reg = <0x0 0x0c22f000 0x0 0x1000>, 4898 <0x0 0x0c225000 0x0 0x1000>; 4899 4900 interrupts = <GIC_SPI 774 IRQ_TYPE_LEVEL_HIGH>, 4901 <GIC_SPI 864 IRQ_TYPE_LEVEL_HIGH>; 4902 interrupt-names = "uplow", 4903 "critical"; 4904 4905 #qcom,sensors = <8>; 4906 4907 #thermal-sensor-cells = <1>; 4908 }; 4909 4910 tsens4: thermal-sensor@c230000 { 4911 compatible = "qcom,glymur-tsens", "qcom,tsens-v2"; 4912 reg = <0x0 0x0c230000 0x0 0x1000>, 4913 <0x0 0x0c226000 0x0 0x1000>; 4914 4915 interrupts = <GIC_SPI 791 IRQ_TYPE_LEVEL_HIGH>, 4916 <GIC_SPI 865 IRQ_TYPE_LEVEL_HIGH>; 4917 interrupt-names = "uplow", 4918 "critical"; 4919 4920 #qcom,sensors = <13>; 4921 4922 #thermal-sensor-cells = <1>; 4923 }; 4924 4925 tsens5: thermal-sensor@c231000 { 4926 compatible = "qcom,glymur-tsens", "qcom,tsens-v2"; 4927 reg = <0x0 0x0c231000 0x0 0x1000>, 4928 <0x0 0x0c227000 0x0 0x1000>; 4929 4930 interrupts = <GIC_SPI 619 IRQ_TYPE_LEVEL_HIGH>, 4931 <GIC_SPI 814 IRQ_TYPE_LEVEL_HIGH>; 4932 interrupt-names = "uplow", 4933 "critical"; 4934 4935 #qcom,sensors = <8>; 4936 4937 #thermal-sensor-cells = <1>; 4938 }; 4939 4940 tsens6: thermal-sensor@c232000 { 4941 compatible = "qcom,glymur-tsens", "qcom,tsens-v2"; 4942 reg = <0x0 0x0c232000 0x0 0x1000>, 4943 <0x0 0x0c228000 0x0 0x1000>; 4944 4945 interrupts = <GIC_SPI 620 IRQ_TYPE_LEVEL_HIGH>, 4946 <GIC_SPI 815 IRQ_TYPE_LEVEL_HIGH>; 4947 interrupt-names = "uplow", 4948 "critical"; 4949 4950 #qcom,sensors = <13>; 4951 4952 #thermal-sensor-cells = <1>; 4953 }; 4954 4955 tsens7: thermal-sensor@c233000 { 4956 compatible = "qcom,glymur-tsens", "qcom,tsens-v2"; 4957 reg = <0x0 0x0c233000 0x0 0x1000>, 4958 <0x0 0x0c229000 0x0 0x1000>; 4959 4960 interrupts = <GIC_SPI 621 IRQ_TYPE_LEVEL_HIGH>, 4961 <GIC_SPI 816 IRQ_TYPE_LEVEL_HIGH>; 4962 interrupt-names = "uplow", 4963 "critical"; 4964 4965 #qcom,sensors = <15>; 4966 4967 #thermal-sensor-cells = <1>; 4968 }; 4969 4970 aoss_qmp: power-management@c300000 { 4971 compatible = "qcom,glymur-aoss-qmp", "qcom,aoss-qmp"; 4972 reg = <0x0 0x0c300000 0x0 0x400>; 4973 interrupt-parent = <&ipcc>; 4974 interrupts-extended = <&ipcc IPCC_MPROC_AOP IPCC_MPROC_SIGNAL_GLINK_QMP 4975 IRQ_TYPE_EDGE_RISING>; 4976 mboxes = <&ipcc IPCC_MPROC_AOP IPCC_MPROC_SIGNAL_GLINK_QMP>; 4977 4978 #clock-cells = <0>; 4979 }; 4980 4981 sram@c30f000 { 4982 compatible = "qcom,rpmh-stats"; 4983 reg = <0x0 0x0c30f000 0x0 0x400>; 4984 }; 4985 4986 arbiter@c400000 { 4987 compatible = "qcom,glymur-spmi-pmic-arb"; 4988 reg = <0x0 0x0c400000 0x0 0x3000>, 4989 <0x0 0x0c900000 0x0 0x400000>, 4990 <0x0 0x0c4c0000 0x0 0x400000>, 4991 <0x0 0x0c403000 0x0 0x8000>; 4992 reg-names = "core", 4993 "chnls", 4994 "obsrvr", 4995 "chnl_map"; 4996 #address-cells = <2>; 4997 #size-cells = <2>; 4998 ranges; 4999 qcom,channel = <0>; 5000 qcom,ee = <0>; 5001 5002 spmi_bus0: spmi@c426000 { 5003 reg = <0x0 0x0c426000 0x0 0x4000>, 5004 <0x0 0x0c8c0000 0x0 0x10000>, 5005 <0x0 0x0c42a000 0x0 0x8000>; 5006 reg-names = "cnfg", 5007 "intr", 5008 "chnl_owner"; 5009 interrupts-extended = <&pdc 1 IRQ_TYPE_LEVEL_HIGH>; 5010 interrupt-names = "periph_irq"; 5011 interrupt-controller; 5012 #interrupt-cells = <4>; 5013 #address-cells = <2>; 5014 #size-cells = <0>; 5015 }; 5016 5017 spmi_bus1: spmi@c437000 { 5018 reg = <0x0 0x0c437000 0x0 0x4000>, 5019 <0x0 0x0c8d0000 0x0 0x10000>, 5020 <0x0 0x0c43b000 0x0 0x8000>; 5021 reg-names = "cnfg", 5022 "intr", 5023 "chnl_owner"; 5024 interrupts-extended = <&pdc 3 IRQ_TYPE_LEVEL_HIGH>; 5025 interrupt-names = "periph_irq"; 5026 interrupt-controller; 5027 #interrupt-cells = <4>; 5028 #address-cells = <2>; 5029 #size-cells = <0>; 5030 }; 5031 5032 spmi_bus2: spmi@c48000 { 5033 reg = <0x0 0x0c448000 0x0 0x4000>, 5034 <0x0 0x0c8e0000 0x0 0x10000>, 5035 <0x0 0x0c44c000 0x0 0x8000>; 5036 reg-names = "cnfg", 5037 "intr", 5038 "chnl_owner"; 5039 interrupts-extended = <&pdc 72 IRQ_TYPE_LEVEL_HIGH>; 5040 interrupt-names = "periph_irq"; 5041 interrupt-controller; 5042 #interrupt-cells = <4>; 5043 #address-cells = <2>; 5044 #size-cells = <0>; 5045 }; 5046 }; 5047 5048 tlmm: pinctrl@f100000 { 5049 compatible = "qcom,glymur-tlmm"; 5050 reg = <0x0 0x0f100000 0x0 0xf00000>; 5051 interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>; 5052 gpio-controller; 5053 #gpio-cells = <2>; 5054 interrupt-controller; 5055 #interrupt-cells = <2>; 5056 gpio-ranges = <&tlmm 0 0 249>; 5057 wakeup-parent = <&pdc>; 5058 5059 qup_i2c0_data_clk: qup-i2c0-data-clk-state { 5060 /* SDA, SCL */ 5061 pins = "gpio0", "gpio1"; 5062 function = "qup0_se0"; 5063 drive-strength = <2>; 5064 bias-pull-up = <2200>; 5065 }; 5066 5067 qup_i2c1_data_clk: qup-i2c1-data-clk-state { 5068 /* SDA, SCL */ 5069 pins = "gpio4", "gpio5"; 5070 function = "qup0_se1"; 5071 drive-strength = <2>; 5072 bias-pull-up = <2200>; 5073 }; 5074 5075 qup_i2c2_data_clk: qup-i2c2-data-clk-state { 5076 /* SDA, SCL */ 5077 pins = "gpio8", "gpio9"; 5078 function = "qup0_se2"; 5079 drive-strength = <2>; 5080 bias-pull-up = <2200>; 5081 }; 5082 5083 qup_i2c3_data_clk: qup-i2c3-data-clk-state { 5084 /* SDA, SCL */ 5085 pins = "gpio12", "gpio13"; 5086 function = "qup0_se3"; 5087 drive-strength = <2>; 5088 bias-pull-up = <2200>; 5089 }; 5090 5091 qup_i2c4_data_clk: qup-i2c4-data-clk-state { 5092 /* SDA, SCL */ 5093 pins = "gpio16", "gpio17"; 5094 function = "qup0_se4"; 5095 drive-strength = <2>; 5096 bias-pull-up = <2200>; 5097 }; 5098 5099 qup_i2c5_data_clk: qup-i2c5-data-clk-state { 5100 /* SDA, SCL */ 5101 pins = "gpio20", "gpio21"; 5102 function = "qup0_se5"; 5103 drive-strength = <2>; 5104 bias-pull-up = <2200>; 5105 }; 5106 5107 qup_i2c6_data_clk: qup-i2c6-data-clk-state { 5108 /* SDA, SCL */ 5109 pins = "gpio6", "gpio7"; 5110 function = "qup0_se6"; 5111 drive-strength = <2>; 5112 bias-pull-up = <2200>; 5113 }; 5114 5115 qup_i2c7_data_clk: qup-i2c7-data-clk-state { 5116 /* SDA, SCL */ 5117 pins = "gpio14", "gpio15"; 5118 function = "qup0_se7"; 5119 drive-strength = <2>; 5120 bias-pull-up = <2200>; 5121 }; 5122 5123 qup_i2c8_data_clk: qup-i2c8-data-clk-state { 5124 /* SDA, SCL */ 5125 pins = "gpio32", "gpio33"; 5126 function = "qup1_se0"; 5127 drive-strength = <2>; 5128 bias-pull-up = <2200>; 5129 }; 5130 5131 qup_i2c9_data_clk: qup-i2c9-data-clk-state { 5132 /* SDA, SCL */ 5133 pins = "gpio36", "gpio37"; 5134 function = "qup1_se1"; 5135 drive-strength = <2>; 5136 bias-pull-up = <2200>; 5137 }; 5138 5139 qup_i2c10_data_clk: qup-i2c10-data-clk-state { 5140 /* SDA, SCL */ 5141 pins = "gpio40", "gpio41"; 5142 function = "qup1_se2"; 5143 drive-strength = <2>; 5144 bias-pull-up = <2200>; 5145 }; 5146 5147 qup_i2c11_data_clk: qup-i2c11-data-clk-state { 5148 /* SDA, SCL */ 5149 pins = "gpio44", "gpio45"; 5150 function = "qup1_se3"; 5151 drive-strength = <2>; 5152 bias-pull-up = <2200>; 5153 }; 5154 5155 qup_i2c12_data_clk: qup-i2c12-data-clk-state { 5156 /* SDA, SCL */ 5157 pins = "gpio48", "gpio49"; 5158 function = "qup1_se4"; 5159 drive-strength = <2>; 5160 bias-pull-up = <2200>; 5161 }; 5162 5163 qup_i2c13_data_clk: qup-i2c13-data-clk-state { 5164 /* SDA, SCL */ 5165 pins = "gpio52", "gpio53"; 5166 function = "qup1_se5"; 5167 drive-strength = <2>; 5168 bias-pull-up = <2200>; 5169 }; 5170 5171 qup_i2c14_data_clk: qup-i2c14-data-clk-state { 5172 /* SDA, SCL */ 5173 pins = "gpio56", "gpio57"; 5174 function = "qup1_se6"; 5175 drive-strength = <2>; 5176 bias-pull-up = <2200>; 5177 }; 5178 5179 qup_i2c15_data_clk: qup-i2c15-data-clk-state { 5180 /* SDA, SCL */ 5181 pins = "gpio54", "gpio55"; 5182 function = "qup1_se7"; 5183 drive-strength = <2>; 5184 bias-pull-up = <2200>; 5185 }; 5186 5187 qup_i2c16_data_clk: qup-i2c16-data-clk-state { 5188 /* SDA, SCL */ 5189 pins = "gpio64", "gpio65"; 5190 function = "qup2_se0"; 5191 drive-strength = <2>; 5192 bias-pull-up = <2200>; 5193 }; 5194 5195 qup_i2c17_data_clk: qup-i2c17-data-clk-state { 5196 /* SDA, SCL */ 5197 pins = "gpio68", "gpio69"; 5198 function = "qup2_se1"; 5199 drive-strength = <2>; 5200 bias-pull-up = <2200>; 5201 }; 5202 5203 qup_i2c18_data_clk: qup-i2c18-data-clk-state { 5204 /* SDA, SCL */ 5205 pins = "gpio72", "gpio73"; 5206 function = "qup2_se2"; 5207 drive-strength = <2>; 5208 bias-pull-up = <2200>; 5209 }; 5210 5211 qup_i2c19_data_clk: qup-i2c19-data-clk-state { 5212 /* SDA, SCL */ 5213 pins = "gpio76", "gpio77"; 5214 function = "qup2_se3"; 5215 drive-strength = <2>; 5216 bias-pull-up = <2200>; 5217 }; 5218 5219 qup_i2c20_data_clk: qup-i2c20-data-clk-state { 5220 /* SDA, SCL */ 5221 pins = "gpio80", "gpio81"; 5222 function = "qup2_se4"; 5223 drive-strength = <2>; 5224 bias-pull-up = <2200>; 5225 }; 5226 5227 qup_i2c21_data_clk: qup-i2c21-data-clk-state { 5228 /* SDA, SCL */ 5229 pins = "gpio84", "gpio85"; 5230 function = "qup2_se5"; 5231 drive-strength = <2>; 5232 bias-pull-up = <2200>; 5233 }; 5234 5235 qup_i2c22_data_clk: qup-i2c22-data-clk-state { 5236 /* SDA, SCL */ 5237 pins = "gpio88", "gpio89"; 5238 function = "qup2_se6"; 5239 drive-strength = <2>; 5240 bias-pull-up = <2200>; 5241 }; 5242 5243 qup_i2c23_data_clk: qup-i2c23-data-clk-state { 5244 /* SDA, SCL */ 5245 pins = "gpio80", "gpio81"; 5246 function = "qup2_se7"; 5247 drive-strength = <2>; 5248 bias-pull-up = <2200>; 5249 }; 5250 5251 qup_spi0_cs: qup-spi0-cs-state { 5252 pins = "gpio3"; 5253 function = "qup0_se0"; 5254 drive-strength = <6>; 5255 bias-disable; 5256 }; 5257 5258 qup_spi0_data_clk: qup-spi0-data-clk-state { 5259 /* MISO, MOSI, CLK */ 5260 pins = "gpio0", "gpio1", "gpio2"; 5261 function = "qup0_se0"; 5262 drive-strength = <6>; 5263 bias-disable; 5264 }; 5265 5266 qup_spi1_cs: qup-spi1-cs-state { 5267 pins = "gpio7"; 5268 function = "qup0_se1"; 5269 drive-strength = <6>; 5270 bias-disable; 5271 }; 5272 5273 qup_spi1_data_clk: qup-spi1-data-clk-state { 5274 /* MISO, MOSI, CLK */ 5275 pins = "gpio4", "gpio5", "gpio6"; 5276 function = "qup0_se1"; 5277 drive-strength = <6>; 5278 bias-disable; 5279 }; 5280 5281 qup_spi2_cs: qup-spi2-cs-state { 5282 pins = "gpio11"; 5283 function = "qup0_se2"; 5284 drive-strength = <6>; 5285 bias-disable; 5286 }; 5287 5288 qup_spi2_data_clk: qup-spi2-data-clk-state { 5289 /* MISO, MOSI, CLK */ 5290 pins = "gpio8", "gpio9", "gpio10"; 5291 function = "qup0_se2"; 5292 drive-strength = <6>; 5293 bias-disable; 5294 }; 5295 5296 qup_spi3_cs: qup-spi3-cs-state { 5297 pins = "gpio15"; 5298 function = "qup0_se3"; 5299 drive-strength = <6>; 5300 bias-disable; 5301 }; 5302 5303 qup_spi3_data_clk: qup-spi3-data-clk-state { 5304 /* MISO, MOSI, CLK */ 5305 pins = "gpio12", "gpio13", "gpio14"; 5306 function = "qup0_se3"; 5307 drive-strength = <6>; 5308 bias-disable; 5309 }; 5310 5311 qup_spi4_cs: qup-spi4-cs-state { 5312 pins = "gpio19"; 5313 function = "qup0_se4"; 5314 drive-strength = <6>; 5315 bias-disable; 5316 }; 5317 5318 qup_spi4_data_clk: qup-spi4-data-clk-state { 5319 /* MISO, MOSI, CLK */ 5320 pins = "gpio16", "gpio17", "gpio18"; 5321 function = "qup0_se4"; 5322 drive-strength = <6>; 5323 bias-disable; 5324 }; 5325 5326 qup_spi5_cs: qup-spi5-cs-state { 5327 pins = "gpio23"; 5328 function = "qup0_se5"; 5329 drive-strength = <6>; 5330 bias-disable; 5331 }; 5332 5333 qup_spi5_data_clk: qup-spi5-data-clk-state { 5334 /* MISO, MOSI, CLK */ 5335 pins = "gpio20", "gpio21", "gpio22"; 5336 function = "qup0_se5"; 5337 drive-strength = <6>; 5338 bias-disable; 5339 }; 5340 5341 qup_spi6_cs: qup-spi6-cs-state { 5342 pins = "gpio5"; 5343 function = "qup0_se6"; 5344 drive-strength = <6>; 5345 bias-disable; 5346 }; 5347 5348 qup_spi6_data_clk: qup-spi6-data-clk-state { 5349 /* MISO, MOSI, CLK */ 5350 pins = "gpio6", "gpio7", "gpio4"; 5351 function = "qup0_se6"; 5352 drive-strength = <6>; 5353 bias-disable; 5354 }; 5355 5356 qup_spi7_cs: qup-spi7-cs-state { 5357 pins = "gpio13"; 5358 function = "qup0_se7"; 5359 drive-strength = <6>; 5360 bias-disable; 5361 }; 5362 5363 qup_spi7_data_clk: qup-spi7-data-clk-state { 5364 /* MISO, MOSI, CLK */ 5365 pins = "gpio14", "gpio15", "gpio12"; 5366 function = "qup0_se7"; 5367 drive-strength = <6>; 5368 bias-disable; 5369 }; 5370 5371 qup_spi8_cs: qup-spi8-cs-state { 5372 pins = "gpio35"; 5373 function = "qup1_se0"; 5374 drive-strength = <6>; 5375 bias-disable; 5376 }; 5377 5378 qup_spi8_data_clk: qup-spi8-data-clk-state { 5379 /* MISO, MOSI, CLK */ 5380 pins = "gpio32", "gpio33", "gpio34"; 5381 function = "qup1_se0"; 5382 drive-strength = <6>; 5383 bias-disable; 5384 }; 5385 5386 qup_spi9_cs: qup-spi9-cs-state { 5387 pins = "gpio39"; 5388 function = "qup1_se1"; 5389 drive-strength = <6>; 5390 bias-disable; 5391 }; 5392 5393 qup_spi9_data_clk: qup-spi9-data-clk-state { 5394 /* MISO, MOSI, CLK */ 5395 pins = "gpio36", "gpio37", "gpio38"; 5396 function = "qup1_se1"; 5397 drive-strength = <6>; 5398 bias-disable; 5399 }; 5400 5401 qup_spi10_cs: qup-spi10-cs-state { 5402 pins = "gpio43"; 5403 function = "qup1_se2"; 5404 drive-strength = <6>; 5405 bias-disable; 5406 }; 5407 5408 qup_spi10_data_clk: qup-spi10-data-clk-state { 5409 /* MISO, MOSI, CLK */ 5410 pins = "gpio40", "gpio41", "gpio42"; 5411 function = "qup1_se2"; 5412 drive-strength = <6>; 5413 bias-disable; 5414 }; 5415 5416 qup_spi11_cs: qup-spi11-cs-state { 5417 pins = "gpio47"; 5418 function = "qup1_se3"; 5419 drive-strength = <6>; 5420 bias-disable; 5421 }; 5422 5423 qup_spi11_data_clk: qup-spi11-data-clk-state { 5424 pins = "gpio44", "gpio45", "gpio46"; 5425 function = "qup1_se3"; 5426 drive-strength = <6>; 5427 bias-disable; 5428 }; 5429 5430 qup_spi12_cs: qup-spi12-cs-state { 5431 pins = "gpio51"; 5432 function = "qup1_se4"; 5433 drive-strength = <6>; 5434 bias-disable; 5435 }; 5436 5437 qup_spi12_data_clk: qup-spi12-data-clk-state { 5438 /* MISO, MOSI, CLK */ 5439 pins = "gpio48", "gpio49", "gpio50"; 5440 function = "qup1_se4"; 5441 drive-strength = <6>; 5442 bias-disable; 5443 }; 5444 5445 qup_spi13_cs: qup-spi13-cs-state { 5446 pins = "gpio55"; 5447 function = "qup1_se5"; 5448 drive-strength = <6>; 5449 bias-disable; 5450 }; 5451 5452 qup_spi13_data_clk: qup-spi13-data-clk-state { 5453 /* MISO, MOSI, CLK */ 5454 pins = "gpio52", "gpio53", "gpio54"; 5455 function = "qup1_se5"; 5456 drive-strength = <6>; 5457 bias-disable; 5458 }; 5459 5460 qup_spi14_cs: qup-spi14-cs-state { 5461 pins = "gpio59"; 5462 function = "qup1_se6"; 5463 drive-strength = <6>; 5464 bias-disable; 5465 }; 5466 5467 qup_spi14_data_clk: qup-spi14-data-clk-state { 5468 /* MISO, MOSI, CLK */ 5469 pins = "gpio56", "gpio57", "gpio58"; 5470 function = "qup1_se6"; 5471 drive-strength = <6>; 5472 bias-disable; 5473 }; 5474 5475 qup_spi15_cs: qup-spi15-cs-state { 5476 pins = "gpio53"; 5477 function = "qup1_se7"; 5478 drive-strength = <6>; 5479 bias-disable; 5480 }; 5481 5482 qup_spi15_data_clk: qup-spi15-data-clk-state { 5483 /* MISO, MOSI, CLK */ 5484 pins = "gpio54", "gpio55", "gpio52"; 5485 function = "qup1_se7"; 5486 drive-strength = <6>; 5487 bias-disable; 5488 }; 5489 5490 qup_spi16_cs: qup-spi16-cs-state { 5491 pins = "gpio67"; 5492 function = "qup2_se0"; 5493 drive-strength = <6>; 5494 bias-disable; 5495 }; 5496 5497 qup_spi16_data_clk: qup-spi16-data-clk-state { 5498 /* MISO, MOSI, CLK */ 5499 pins = "gpio64", "gpio65", "gpio66"; 5500 function = "qup2_se0"; 5501 drive-strength = <6>; 5502 bias-disable; 5503 }; 5504 5505 qup_spi17_cs: qup-spi17-cs-state { 5506 pins = "gpio71"; 5507 function = "qup2_se1"; 5508 drive-strength = <6>; 5509 bias-disable; 5510 }; 5511 5512 qup_spi17_data_clk: qup-spi17-data-clk-state { 5513 /* MISO, MOSI, CLK */ 5514 pins = "gpio68", "gpio69", "gpio70"; 5515 function = "qup2_se1"; 5516 drive-strength = <6>; 5517 bias-disable; 5518 }; 5519 5520 qup_spi18_cs: qup-spi18-cs-state { 5521 pins = "gpio75"; 5522 function = "qup2_se2"; 5523 drive-strength = <6>; 5524 bias-disable; 5525 }; 5526 5527 qup_spi18_data_clk: qup-spi18-data-clk-state { 5528 /* MISO, MOSI, CLK */ 5529 pins = "gpio72", "gpio73", "gpio74"; 5530 function = "qup2_se2"; 5531 drive-strength = <6>; 5532 bias-disable; 5533 }; 5534 5535 qup_spi19_cs: qup-spi19-cs-state { 5536 pins = "gpio79"; 5537 function = "qup2_se3"; 5538 drive-strength = <6>; 5539 bias-disable; 5540 }; 5541 5542 qup_spi19_data_clk: qup-spi19-data-clk-state { 5543 /* MISO, MOSI, CLK */ 5544 pins = "gpio76", "gpio77", "gpio78"; 5545 function = "qup2_se3"; 5546 drive-strength = <6>; 5547 bias-disable; 5548 }; 5549 5550 qup_spi20_cs: qup-spi20-cs-state { 5551 pins = "gpio83"; 5552 function = "qup2_se4"; 5553 drive-strength = <6>; 5554 bias-disable; 5555 }; 5556 5557 qup_spi20_data_clk: qup-spi20-data-clk-state { 5558 /* MISO, MOSI, CLK */ 5559 pins = "gpio80", "gpio81", "gpio82"; 5560 function = "qup2_se4"; 5561 drive-strength = <6>; 5562 bias-disable; 5563 }; 5564 5565 qup_spi21_cs: qup-spi21-cs-state { 5566 pins = "gpio87"; 5567 function = "qup2_se5"; 5568 drive-strength = <6>; 5569 bias-disable; 5570 }; 5571 5572 qup_spi21_data_clk: qup-spi21-data-clk-state { 5573 /* MISO, MOSI, CLK */ 5574 pins = "gpio84", "gpio85", "gpio86"; 5575 function = "qup2_se5"; 5576 drive-strength = <6>; 5577 bias-disable; 5578 }; 5579 5580 qup_spi22_cs: qup-spi22-cs-state { 5581 pins = "gpio91"; 5582 function = "qup2_se6"; 5583 drive-strength = <6>; 5584 bias-disable; 5585 }; 5586 5587 qup_spi22_data_clk: qup-spi22-data-clk-state { 5588 /* MISO, MOSI, CLK */ 5589 pins = "gpio88", "gpio89", "gpio90"; 5590 function = "qup2_se6"; 5591 drive-strength = <6>; 5592 bias-disable; 5593 }; 5594 5595 qup_spi23_cs: qup-spi23-cs-state { 5596 pins = "gpio83"; 5597 function = "qup2_se7"; 5598 drive-strength = <6>; 5599 bias-disable; 5600 }; 5601 5602 qup_spi23_data_clk: qup-spi23-data-clk-state { 5603 /* MISO, MOSI, CLK */ 5604 pins = "gpio80", "gpio81", "gpio82"; 5605 function = "qup2_se7"; 5606 drive-strength = <6>; 5607 bias-disable; 5608 }; 5609 5610 qup_uart2_default: qup-uart2-default-state { 5611 tx-pins { 5612 pins = "gpio10"; 5613 function = "qup0_se2"; 5614 drive-strength = <2>; 5615 bias-disable; 5616 }; 5617 5618 rx-pins { 5619 pins = "gpio11"; 5620 function = "qup0_se2"; 5621 drive-strength = <2>; 5622 bias-disable; 5623 }; 5624 }; 5625 5626 qup_uart14_default: qup-uart14-default-state { 5627 cts-pins { 5628 pins = "gpio56"; 5629 function = "qup1_se6"; 5630 drive-strength = <2>; 5631 bias-disable; 5632 }; 5633 5634 rts-pins { 5635 pins = "gpio57"; 5636 function = "qup1_se6"; 5637 drive-strength = <2>; 5638 bias-disable; 5639 }; 5640 5641 tx-pins { 5642 pins = "gpio58"; 5643 function = "qup1_se6"; 5644 drive-strength = <2>; 5645 bias-disable; 5646 }; 5647 5648 rx-pins { 5649 pins = "gpio59"; 5650 function = "qup1_se6"; 5651 drive-strength = <2>; 5652 bias-disable; 5653 }; 5654 }; 5655 5656 qup_uart19_default: qup-uart19-default-state { 5657 cts-pins { 5658 pins = "gpio76"; 5659 function = "qup2_se3"; 5660 drive-strength = <2>; 5661 bias-disable; 5662 }; 5663 5664 rts-pins { 5665 pins = "gpio77"; 5666 function = "qup2_se3"; 5667 drive-strength = <2>; 5668 bias-disable; 5669 }; 5670 5671 tx-pins { 5672 pins = "gpio78"; 5673 function = "qup2_se3"; 5674 drive-strength = <2>; 5675 bias-disable; 5676 }; 5677 5678 rx-pins { 5679 pins = "gpio79"; 5680 function = "qup2_se3"; 5681 drive-strength = <2>; 5682 bias-disable; 5683 }; 5684 }; 5685 5686 qup_uart21_default: qup-uart21-default-state { 5687 tx-pins { 5688 pins = "gpio86"; 5689 function = "qup2_se5"; 5690 drive-strength = <2>; 5691 bias-disable; 5692 }; 5693 5694 rx-pins { 5695 pins = "gpio87"; 5696 function = "qup2_se5"; 5697 drive-strength = <2>; 5698 bias-disable; 5699 }; 5700 }; 5701 5702 qup_uart22_default: qup-uart22-default-state { 5703 tx-pins { 5704 pins = "gpio90"; 5705 function = "qup2_se6"; 5706 drive-strength = <2>; 5707 bias-disable; 5708 }; 5709 5710 rx-pins { 5711 pins = "gpio91"; 5712 function = "qup2_se6"; 5713 drive-strength = <2>; 5714 bias-disable; 5715 }; 5716 }; 5717 }; 5718 5719 stm: stm@10002000 { 5720 compatible = "arm,coresight-stm", "arm,primecell"; 5721 reg = <0x0 0x10002000 0x0 0x1000>, 5722 <0x0 0x16280000 0x0 0x180000>; 5723 reg-names = "stm-base", 5724 "stm-stimulus-base"; 5725 5726 clocks = <&aoss_qmp>; 5727 clock-names = "apb_pclk"; 5728 5729 out-ports { 5730 port { 5731 stm_out: endpoint { 5732 remote-endpoint = <&funnel0_in7>; 5733 }; 5734 }; 5735 }; 5736 }; 5737 5738 tpda@10004000 { 5739 compatible = "qcom,coresight-tpda", "arm,primecell"; 5740 reg = <0x0 0x10004000 0x0 0x1000>; 5741 5742 clocks = <&aoss_qmp>; 5743 clock-names = "apb_pclk"; 5744 5745 in-ports { 5746 #address-cells = <1>; 5747 #size-cells = <0>; 5748 5749 port@1 { 5750 reg = <1>; 5751 5752 qdss_tpda_in1: endpoint { 5753 remote-endpoint = <&spdm_tpdm_out>; 5754 }; 5755 }; 5756 }; 5757 5758 out-ports { 5759 port { 5760 qdss_tpda_out: endpoint { 5761 remote-endpoint = <&funnel0_in6>; 5762 }; 5763 }; 5764 }; 5765 }; 5766 5767 tpdm@1000f000 { 5768 compatible = "qcom,coresight-tpdm", "arm,primecell"; 5769 reg = <0x0 0x1000f000 0x0 0x1000>; 5770 5771 clocks = <&aoss_qmp>; 5772 clock-names = "apb_pclk"; 5773 5774 qcom,cmb-element-bits = <32>; 5775 qcom,cmb-msrs-num = <32>; 5776 5777 out-ports { 5778 port { 5779 spdm_tpdm_out: endpoint { 5780 remote-endpoint = <&qdss_tpda_in1>; 5781 }; 5782 }; 5783 }; 5784 }; 5785 5786 funnel@10041000 { 5787 compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; 5788 reg = <0x0 0x10041000 0x0 0x1000>; 5789 5790 clocks = <&aoss_qmp>; 5791 clock-names = "apb_pclk"; 5792 5793 in-ports { 5794 #address-cells = <1>; 5795 #size-cells = <0>; 5796 5797 port@0 { 5798 reg = <0>; 5799 5800 funnel0_in0: endpoint { 5801 remote-endpoint = <&tn_ag_out>; 5802 }; 5803 }; 5804 5805 port@6 { 5806 reg = <6>; 5807 5808 funnel0_in6: endpoint { 5809 remote-endpoint = <&qdss_tpda_out>; 5810 }; 5811 }; 5812 5813 port@7 { 5814 reg = <7>; 5815 5816 funnel0_in7: endpoint { 5817 remote-endpoint = <&stm_out>; 5818 }; 5819 }; 5820 }; 5821 5822 out-ports { 5823 port { 5824 funnel0_out: endpoint { 5825 remote-endpoint = <&aoss_funnel_in6>; 5826 }; 5827 }; 5828 }; 5829 }; 5830 5831 tpdm@1102c000 { 5832 compatible = "qcom,coresight-tpdm", "arm,primecell"; 5833 reg = <0x0 0x1102c000 0x0 0x1000>; 5834 5835 clocks = <&aoss_qmp>; 5836 clock-names = "apb_pclk"; 5837 5838 qcom,dsb-msrs-num = <32>; 5839 5840 out-ports { 5841 port { 5842 gcc_tpdm_out: endpoint { 5843 remote-endpoint = <&tn_ag_in36>; 5844 }; 5845 }; 5846 }; 5847 }; 5848 5849 tpdm@11180000 { 5850 compatible = "qcom,coresight-tpdm", "arm,primecell"; 5851 reg = <0x0 0x11180000 0x0 0x1000>; 5852 5853 clocks = <&aoss_qmp>; 5854 clock-names = "apb_pclk"; 5855 5856 qcom,dsb-element-bits = <32>; 5857 qcom,dsb-msrs-num = <32>; 5858 5859 out-ports { 5860 port { 5861 cdsp_tpdm_out: endpoint { 5862 remote-endpoint = <&cdsp_tpda_in0>; 5863 }; 5864 }; 5865 }; 5866 }; 5867 5868 tpdm@11185000 { 5869 compatible = "qcom,coresight-tpdm", "arm,primecell"; 5870 reg = <0x0 0x11185000 0x0 0x1000>; 5871 5872 clocks = <&aoss_qmp>; 5873 clock-names = "apb_pclk"; 5874 5875 qcom,cmb-element-bits = <64>; 5876 qcom,cmb-msrs-num = <32>; 5877 5878 out-ports { 5879 port { 5880 cdsp_dpm1_tpdm_out: endpoint { 5881 remote-endpoint = <&cdsp_tpda_in5>; 5882 }; 5883 }; 5884 }; 5885 }; 5886 5887 tpdm@11186000 { 5888 compatible = "qcom,coresight-tpdm", "arm,primecell"; 5889 reg = <0x0 0x11186000 0x0 0x1000>; 5890 5891 clocks = <&aoss_qmp>; 5892 clock-names = "apb_pclk"; 5893 5894 qcom,cmb-element-bits = <64>; 5895 qcom,cmb-msrs-num = <32>; 5896 5897 out-ports { 5898 port { 5899 cdsp_dpm2_tpdm_out: endpoint { 5900 remote-endpoint = <&cdsp_tpda_in6>; 5901 }; 5902 }; 5903 }; 5904 }; 5905 5906 tpda@11188000 { 5907 compatible = "qcom,coresight-tpda", "arm,primecell"; 5908 reg = <0x0 0x11188000 0x0 0x1000>; 5909 5910 clocks = <&aoss_qmp>; 5911 clock-names = "apb_pclk"; 5912 5913 in-ports { 5914 #address-cells = <1>; 5915 #size-cells = <0>; 5916 5917 port@0 { 5918 reg = <0>; 5919 5920 cdsp_tpda_in0: endpoint { 5921 remote-endpoint = <&cdsp_tpdm_out>; 5922 }; 5923 }; 5924 5925 port@1 { 5926 reg = <1>; 5927 5928 cdsp_tpda_in1: endpoint { 5929 remote-endpoint = <&cdsp_llm_tpdm_out>; 5930 }; 5931 }; 5932 5933 port@2 { 5934 reg = <2>; 5935 5936 cdsp_tpda_in2: endpoint { 5937 remote-endpoint = <&cdsp_llm2_tpdm_out>; 5938 }; 5939 }; 5940 5941 port@3 { 5942 reg = <3>; 5943 5944 cdsp_tpda_in3: endpoint { 5945 remote-endpoint = <&cdsp_cmsr_tpdm_out>; 5946 }; 5947 }; 5948 5949 port@4 { 5950 reg = <4>; 5951 5952 cdsp_tpda_in4: endpoint { 5953 remote-endpoint = <&cdsp_cmsr2_tpdm_out>; 5954 }; 5955 }; 5956 5957 port@5 { 5958 reg = <5>; 5959 5960 cdsp_tpda_in5: endpoint { 5961 remote-endpoint = <&cdsp_dpm1_tpdm_out>; 5962 }; 5963 }; 5964 5965 port@6 { 5966 reg = <6>; 5967 5968 cdsp_tpda_in6: endpoint { 5969 remote-endpoint = <&cdsp_dpm2_tpdm_out>; 5970 }; 5971 }; 5972 }; 5973 5974 out-ports { 5975 port { 5976 cdsp_tpda_out: endpoint { 5977 remote-endpoint = <&cdsp_funnel_in0>; 5978 }; 5979 }; 5980 }; 5981 }; 5982 5983 funnel@11189000 { 5984 compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; 5985 reg = <0x0 0x11189000 0x0 0x1000>; 5986 5987 clocks = <&aoss_qmp>; 5988 clock-names = "apb_pclk"; 5989 5990 in-ports { 5991 port { 5992 cdsp_funnel_in0: endpoint { 5993 remote-endpoint = <&cdsp_tpda_out>; 5994 }; 5995 }; 5996 }; 5997 5998 out-ports { 5999 port { 6000 cdsp_funnel_out: endpoint { 6001 remote-endpoint = <&tn_ag_in53>; 6002 }; 6003 }; 6004 }; 6005 }; 6006 6007 cti@11193000 { 6008 compatible = "arm,coresight-cti", "arm,primecell"; 6009 reg = <0x0 0x11193000 0x0 0x1000>; 6010 6011 clocks = <&aoss_qmp>; 6012 clock-names = "apb_pclk"; 6013 }; 6014 6015 cti_wpss: cti@111ab000 { 6016 compatible = "arm,coresight-cti", "arm,primecell"; 6017 reg = <0x0 0x111ab000 0x0 0x1000>; 6018 6019 clocks = <&aoss_qmp>; 6020 clock-names = "apb_pclk"; 6021 }; 6022 6023 tpdm@111d0000 { 6024 compatible = "qcom,coresight-tpdm", "arm,primecell"; 6025 reg = <0x0 0x111d0000 0x0 0x1000>; 6026 6027 clocks = <&aoss_qmp>; 6028 clock-names = "apb_pclk"; 6029 6030 qcom,dsb-msrs-num = <32>; 6031 6032 out-ports { 6033 port { 6034 qm_tpdm_out: endpoint { 6035 remote-endpoint = <&tn_ag_in35>; 6036 }; 6037 }; 6038 }; 6039 }; 6040 6041 itnoc@11200000 { 6042 compatible = "qcom,coresight-itnoc"; 6043 reg = <0x0 0x11200000 0x0 0x3c00>; 6044 6045 clocks = <&aoss_qmp>; 6046 clock-names = "apb"; 6047 6048 in-ports { 6049 #address-cells = <1>; 6050 #size-cells = <0>; 6051 6052 port@6 { 6053 reg = <6>; 6054 6055 tn_ag_in6: endpoint { 6056 remote-endpoint = <&mm_dsb_tpdm_out>; 6057 }; 6058 }; 6059 6060 port@10 { 6061 reg = <0x10>; 6062 6063 tn_ag_in16: endpoint { 6064 remote-endpoint = <&east_dsb_tpdm_out>; 6065 }; 6066 }; 6067 6068 port@21 { 6069 reg = <0x21>; 6070 6071 tn_ag_in33: endpoint { 6072 remote-endpoint = <&west_dsb_tpdm_out>; 6073 }; 6074 }; 6075 6076 port@23 { 6077 reg = <0x23>; 6078 6079 tn_ag_in35: endpoint { 6080 remote-endpoint = <&qm_tpdm_out>; 6081 }; 6082 }; 6083 6084 port@24 { 6085 reg = <0x24>; 6086 6087 tn_ag_in36: endpoint { 6088 remote-endpoint = <&gcc_tpdm_out>; 6089 }; 6090 }; 6091 6092 port@32 { 6093 reg = <0x32>; 6094 6095 tn_ag_in50: endpoint { 6096 remote-endpoint = <&pcie_rscc_tpda_out>; 6097 }; 6098 }; 6099 6100 port@35 { 6101 reg = <0x35>; 6102 6103 tn_ag_in53: endpoint { 6104 remote-endpoint = <&cdsp_funnel_out>; 6105 }; 6106 }; 6107 6108 port@3f { 6109 reg = <0x3f>; 6110 6111 tn_ag_in63: endpoint { 6112 remote-endpoint = <¢er_dsb_tpdm_out>; 6113 }; 6114 }; 6115 6116 port@40 { 6117 reg = <0x40>; 6118 6119 tn_ag_in64: endpoint { 6120 remote-endpoint = <&ipcc_cmb_tpdm_out>; 6121 }; 6122 }; 6123 6124 port@41 { 6125 reg = <0x41>; 6126 6127 tn_ag_in65: endpoint { 6128 remote-endpoint = <&qrng_tpdm_out>; 6129 }; 6130 }; 6131 6132 port@42 { 6133 reg = <0x42>; 6134 6135 tn_ag_in66: endpoint { 6136 remote-endpoint = <&pmu_tpdm_out>; 6137 }; 6138 }; 6139 6140 port@43 { 6141 reg = <0x43>; 6142 6143 tn_ag_in67: endpoint { 6144 remote-endpoint = <&rdpm_west_cmb0_tpdm_out>; 6145 }; 6146 }; 6147 6148 port@44 { 6149 reg = <0x44>; 6150 6151 tn_ag_in68: endpoint { 6152 remote-endpoint = <&rdpm_west_cmb1_tpdm_out>; 6153 }; 6154 }; 6155 6156 port@45 { 6157 reg = <0x45>; 6158 6159 tn_ag_in69: endpoint { 6160 remote-endpoint = <&rdpm_west_cmb2_tpdm_out>; 6161 }; 6162 }; 6163 6164 port@4b { 6165 reg = <0x4b>; 6166 6167 tn_ag_in75: endpoint { 6168 remote-endpoint = <&south_dsb2_tpdm_out>; 6169 }; 6170 }; 6171 6172 port@52 { 6173 reg = <0x52>; 6174 6175 tn_ag_in82: endpoint { 6176 remote-endpoint = <&south_dsb_tpdm_out>; 6177 }; 6178 }; 6179 6180 port@53 { 6181 reg = <0x53>; 6182 6183 tn_ag_in83: endpoint { 6184 remote-endpoint = <¢er_dsb1_tpdm_out>; 6185 }; 6186 }; 6187 }; 6188 6189 out-ports { 6190 port { 6191 tn_ag_out: endpoint { 6192 remote-endpoint = <&funnel0_in0>; 6193 }; 6194 }; 6195 }; 6196 }; 6197 6198 tpdm@11207000 { 6199 compatible = "qcom,coresight-tpdm", "arm,primecell"; 6200 reg = <0x0 0x11207000 0x0 0x1000>; 6201 6202 clocks = <&aoss_qmp>; 6203 clock-names = "apb_pclk"; 6204 6205 qcom,dsb-msrs-num = <32>; 6206 6207 out-ports { 6208 port { 6209 mm_dsb_tpdm_out: endpoint { 6210 remote-endpoint = <&tn_ag_in6>; 6211 }; 6212 }; 6213 }; 6214 }; 6215 6216 tpdm@1120b000 { 6217 compatible = "qcom,coresight-tpdm", "arm,primecell"; 6218 reg = <0x0 0x1120b000 0x0 0x1000>; 6219 6220 clocks = <&aoss_qmp>; 6221 clock-names = "apb_pclk"; 6222 6223 qcom,dsb-msrs-num = <32>; 6224 6225 out-ports { 6226 port { 6227 east_dsb_tpdm_out: endpoint { 6228 remote-endpoint = <&tn_ag_in16>; 6229 }; 6230 }; 6231 }; 6232 }; 6233 6234 tpdm@11213000 { 6235 compatible = "qcom,coresight-tpdm", "arm,primecell"; 6236 reg = <0x0 0x11213000 0x0 0x1000>; 6237 6238 clocks = <&aoss_qmp>; 6239 clock-names = "apb_pclk"; 6240 6241 qcom,dsb-msrs-num = <32>; 6242 6243 out-ports { 6244 port { 6245 west_dsb_tpdm_out: endpoint { 6246 remote-endpoint = <&tn_ag_in33>; 6247 }; 6248 }; 6249 }; 6250 }; 6251 6252 tpdm@11219000 { 6253 compatible = "qcom,coresight-tpdm", "arm,primecell"; 6254 reg = <0x0 0x11219000 0x0 0x1000>; 6255 6256 clocks = <&aoss_qmp>; 6257 clock-names = "apb_pclk"; 6258 6259 qcom,dsb-msrs-num = <32>; 6260 6261 out-ports { 6262 port { 6263 center_dsb_tpdm_out: endpoint { 6264 remote-endpoint = <&tn_ag_in63>; 6265 }; 6266 }; 6267 }; 6268 }; 6269 6270 tpdm@1121a000 { 6271 compatible = "qcom,coresight-tpdm", "arm,primecell"; 6272 reg = <0x0 0x1121a000 0x0 0x1000>; 6273 6274 clocks = <&aoss_qmp>; 6275 clock-names = "apb_pclk"; 6276 6277 qcom,cmb-msrs-num = <32>; 6278 6279 out-ports { 6280 port { 6281 ipcc_cmb_tpdm_out: endpoint { 6282 remote-endpoint = <&tn_ag_in64>; 6283 }; 6284 }; 6285 }; 6286 }; 6287 6288 tpdm@1121b000 { 6289 compatible = "qcom,coresight-tpdm", "arm,primecell"; 6290 reg = <0x0 0x1121b000 0x0 0x1000>; 6291 6292 clocks = <&aoss_qmp>; 6293 clock-names = "apb_pclk"; 6294 6295 qcom,cmb-msrs-num = <32>; 6296 6297 out-ports { 6298 port { 6299 qrng_tpdm_out: endpoint { 6300 remote-endpoint = <&tn_ag_in65>; 6301 }; 6302 }; 6303 }; 6304 }; 6305 6306 tpdm@1121c000 { 6307 compatible = "qcom,coresight-tpdm", "arm,primecell"; 6308 reg = <0x0 0x1121c000 0x0 0x1000>; 6309 6310 clocks = <&aoss_qmp>; 6311 clock-names = "apb_pclk"; 6312 6313 qcom,dsb-msrs-num = <32>; 6314 6315 out-ports { 6316 port { 6317 pmu_tpdm_out: endpoint { 6318 remote-endpoint = <&tn_ag_in66>; 6319 }; 6320 }; 6321 }; 6322 }; 6323 6324 tpdm@1121d000 { 6325 compatible = "qcom,coresight-tpdm", "arm,primecell"; 6326 reg = <0x0 0x1121d000 0x0 0x1000>; 6327 6328 clocks = <&aoss_qmp>; 6329 clock-names = "apb_pclk"; 6330 6331 qcom,cmb-msrs-num = <32>; 6332 6333 out-ports { 6334 port { 6335 rdpm_west_cmb0_tpdm_out: endpoint { 6336 remote-endpoint = <&tn_ag_in67>; 6337 }; 6338 }; 6339 }; 6340 }; 6341 6342 tpdm@1121e000 { 6343 compatible = "qcom,coresight-tpdm", "arm,primecell"; 6344 reg = <0x0 0x1121e000 0x0 0x1000>; 6345 6346 clocks = <&aoss_qmp>; 6347 clock-names = "apb_pclk"; 6348 6349 qcom,cmb-msrs-num = <32>; 6350 6351 out-ports { 6352 port { 6353 rdpm_west_cmb1_tpdm_out: endpoint { 6354 remote-endpoint = <&tn_ag_in68>; 6355 }; 6356 }; 6357 }; 6358 }; 6359 6360 tpdm@1121f000 { 6361 compatible = "qcom,coresight-tpdm", "arm,primecell"; 6362 reg = <0x0 0x1121f000 0x0 0x1000>; 6363 6364 clocks = <&aoss_qmp>; 6365 clock-names = "apb_pclk"; 6366 6367 qcom,cmb-msrs-num = <32>; 6368 6369 out-ports { 6370 port { 6371 rdpm_west_cmb2_tpdm_out: endpoint { 6372 remote-endpoint = <&tn_ag_in69>; 6373 }; 6374 }; 6375 }; 6376 }; 6377 6378 tpdm@11220000 { 6379 compatible = "qcom,coresight-tpdm", "arm,primecell"; 6380 reg = <0x0 0x11220000 0x0 0x1000>; 6381 6382 clocks = <&aoss_qmp>; 6383 clock-names = "apb_pclk"; 6384 6385 qcom,dsb-msrs-num = <32>; 6386 6387 out-ports { 6388 port { 6389 center_dsb1_tpdm_out: endpoint { 6390 remote-endpoint = <&tn_ag_in83>; 6391 }; 6392 }; 6393 }; 6394 }; 6395 6396 tpdm@11224000 { 6397 compatible = "qcom,coresight-tpdm", "arm,primecell"; 6398 reg = <0x0 0x11224000 0x0 0x1000>; 6399 6400 clocks = <&aoss_qmp>; 6401 clock-names = "apb_pclk"; 6402 6403 qcom,dsb-msrs-num = <32>; 6404 6405 out-ports { 6406 port { 6407 south_dsb2_tpdm_out: endpoint { 6408 remote-endpoint = <&tn_ag_in75>; 6409 }; 6410 }; 6411 }; 6412 }; 6413 6414 tpdm@11228000 { 6415 compatible = "qcom,coresight-tpdm", "arm,primecell"; 6416 reg = <0x0 0x11228000 0x0 0x1000>; 6417 6418 clocks = <&aoss_qmp>; 6419 clock-names = "apb_pclk"; 6420 6421 qcom,dsb-msrs-num = <32>; 6422 6423 out-ports { 6424 port { 6425 south_dsb_tpdm_out: endpoint { 6426 remote-endpoint = <&tn_ag_in82>; 6427 }; 6428 }; 6429 }; 6430 }; 6431 6432 tpdm@11470000 { 6433 compatible = "qcom,coresight-tpdm", "arm,primecell"; 6434 reg = <0x0 0x11470000 0x0 0x1000>; 6435 6436 clocks = <&aoss_qmp>; 6437 clock-names = "apb_pclk"; 6438 6439 qcom,cmb-element-bits = <32>; 6440 qcom,cmb-msrs-num = <32>; 6441 6442 out-ports { 6443 port { 6444 pcie_rscc_tpdm_out: endpoint { 6445 remote-endpoint = <&pcie_rscc_tpda_in0>; 6446 }; 6447 }; 6448 }; 6449 }; 6450 6451 tpda@11471000 { 6452 compatible = "qcom,coresight-tpda", "arm,primecell"; 6453 reg = <0x0 0x11471000 0x0 0x1000>; 6454 6455 clocks = <&aoss_qmp>; 6456 clock-names = "apb_pclk"; 6457 6458 in-ports { 6459 port { 6460 pcie_rscc_tpda_in0: endpoint { 6461 remote-endpoint = <&pcie_rscc_tpdm_out>; 6462 }; 6463 }; 6464 }; 6465 6466 out-ports { 6467 port { 6468 pcie_rscc_tpda_out: endpoint { 6469 remote-endpoint = <&tn_ag_in50>; 6470 }; 6471 }; 6472 }; 6473 }; 6474 6475 tpdm@11c03000 { 6476 compatible = "qcom,coresight-tpdm", "arm,primecell"; 6477 reg = <0x0 0x11c03000 0x0 0x1000>; 6478 6479 clocks = <&aoss_qmp>; 6480 clock-names = "apb_pclk"; 6481 6482 qcom,cmb-element-bits = <64>; 6483 qcom,cmb-msrs-num = <32>; 6484 6485 out-ports { 6486 port { 6487 swao_prio4_tpdm_out: endpoint { 6488 remote-endpoint = <&aoss_tpda_in4>; 6489 }; 6490 }; 6491 }; 6492 }; 6493 6494 funnel@11c04000 { 6495 compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; 6496 reg = <0x0 0x11c04000 0x0 0x1000>; 6497 6498 clocks = <&aoss_qmp>; 6499 clock-names = "apb_pclk"; 6500 6501 in-ports { 6502 #address-cells = <1>; 6503 #size-cells = <0>; 6504 6505 port@5 { 6506 reg = <5>; 6507 6508 aoss_funnel_in5: endpoint { 6509 remote-endpoint = <&aoss_tpda_out>; 6510 }; 6511 }; 6512 6513 port@6 { 6514 reg = <6>; 6515 6516 aoss_funnel_in6: endpoint { 6517 remote-endpoint = <&funnel0_out>; 6518 }; 6519 }; 6520 }; 6521 6522 out-ports { 6523 port { 6524 aoss_funnel_out: endpoint { 6525 remote-endpoint = <&etf0_in>; 6526 }; 6527 }; 6528 }; 6529 }; 6530 6531 tmc_etf: tmc@11c05000 { 6532 compatible = "arm,coresight-tmc", "arm,primecell"; 6533 reg = <0x0 0x11c05000 0x0 0x1000>; 6534 6535 clocks = <&aoss_qmp>; 6536 clock-names = "apb_pclk"; 6537 6538 in-ports { 6539 port { 6540 etf0_in: endpoint { 6541 remote-endpoint = <&aoss_funnel_out>; 6542 }; 6543 }; 6544 }; 6545 6546 out-ports { 6547 port { 6548 etf0_out: endpoint { 6549 remote-endpoint = <&swao_rep_in>; 6550 }; 6551 }; 6552 }; 6553 }; 6554 6555 replicator@11c06000 { 6556 compatible = "arm,coresight-dynamic-replicator", "arm,primecell"; 6557 reg = <0x0 0x11c06000 0x0 0x1000>; 6558 6559 clocks = <&aoss_qmp>; 6560 clock-names = "apb_pclk"; 6561 6562 in-ports { 6563 port { 6564 swao_rep_in: endpoint { 6565 remote-endpoint = <&etf0_out>; 6566 }; 6567 }; 6568 }; 6569 6570 out-ports { 6571 #address-cells = <1>; 6572 #size-cells = <0>; 6573 6574 port@1 { 6575 reg = <1>; 6576 6577 swao_rep_out1: endpoint { 6578 remote-endpoint = <&eud_in>; 6579 }; 6580 }; 6581 }; 6582 }; 6583 6584 tpda@11c08000 { 6585 compatible = "qcom,coresight-tpda", "arm,primecell"; 6586 reg = <0x0 0x11c08000 0x0 0x1000>; 6587 6588 clocks = <&aoss_qmp>; 6589 clock-names = "apb_pclk"; 6590 6591 in-ports { 6592 #address-cells = <1>; 6593 #size-cells = <0>; 6594 6595 port@0 { 6596 reg = <0>; 6597 6598 aoss_tpda_in0: endpoint { 6599 remote-endpoint = <&swao_prio0_tpdm_out>; 6600 }; 6601 }; 6602 6603 port@1 { 6604 reg = <1>; 6605 6606 aoss_tpda_in1: endpoint { 6607 remote-endpoint = <&swao_prio1_tpdm_out>; 6608 }; 6609 }; 6610 6611 port@2 { 6612 reg = <2>; 6613 6614 aoss_tpda_in2: endpoint { 6615 remote-endpoint = <&swao_prio2_tpdm_out>; 6616 }; 6617 }; 6618 6619 port@3 { 6620 reg = <3>; 6621 6622 aoss_tpda_in3: endpoint { 6623 remote-endpoint = <&swao_prio3_tpdm_out>; 6624 }; 6625 }; 6626 6627 port@4 { 6628 reg = <4>; 6629 6630 aoss_tpda_in4: endpoint { 6631 remote-endpoint = <&swao_prio4_tpdm_out>; 6632 }; 6633 }; 6634 6635 port@5 { 6636 reg = <5>; 6637 6638 aoss_tpda_in5: endpoint { 6639 remote-endpoint = <&swao_tpdm_out>; 6640 }; 6641 }; 6642 }; 6643 6644 out-ports { 6645 port { 6646 aoss_tpda_out: endpoint { 6647 remote-endpoint = <&aoss_funnel_in5>; 6648 }; 6649 }; 6650 }; 6651 }; 6652 6653 tpdm@11c09000 { 6654 compatible = "qcom,coresight-tpdm", "arm,primecell"; 6655 reg = <0x0 0x11c09000 0x0 0x1000>; 6656 6657 clocks = <&aoss_qmp>; 6658 clock-names = "apb_pclk"; 6659 6660 qcom,cmb-element-bits = <64>; 6661 qcom,cmb-msrs-num = <32>; 6662 6663 out-ports { 6664 port { 6665 swao_prio0_tpdm_out: endpoint { 6666 remote-endpoint = <&aoss_tpda_in0>; 6667 }; 6668 }; 6669 }; 6670 }; 6671 6672 tpdm@11c0a000 { 6673 compatible = "qcom,coresight-tpdm", "arm,primecell"; 6674 reg = <0x0 0x11c0a000 0x0 0x1000>; 6675 6676 clocks = <&aoss_qmp>; 6677 clock-names = "apb_pclk"; 6678 6679 qcom,cmb-element-bits = <64>; 6680 qcom,cmb-msrs-num = <32>; 6681 6682 out-ports { 6683 port { 6684 swao_prio1_tpdm_out: endpoint { 6685 remote-endpoint = <&aoss_tpda_in1>; 6686 }; 6687 }; 6688 }; 6689 }; 6690 6691 tpdm@11c0b000 { 6692 compatible = "qcom,coresight-tpdm", "arm,primecell"; 6693 reg = <0x0 0x11c0b000 0x0 0x1000>; 6694 6695 clocks = <&aoss_qmp>; 6696 clock-names = "apb_pclk"; 6697 6698 qcom,cmb-element-bits = <64>; 6699 qcom,cmb-msrs-num = <32>; 6700 6701 out-ports { 6702 port { 6703 swao_prio2_tpdm_out: endpoint { 6704 remote-endpoint = <&aoss_tpda_in2>; 6705 }; 6706 }; 6707 }; 6708 }; 6709 6710 tpdm@11c0c000 { 6711 compatible = "qcom,coresight-tpdm", "arm,primecell"; 6712 reg = <0x0 0x11c0c000 0x0 0x1000>; 6713 6714 clocks = <&aoss_qmp>; 6715 clock-names = "apb_pclk"; 6716 6717 qcom,cmb-element-bits = <64>; 6718 qcom,cmb-msrs-num = <32>; 6719 6720 out-ports { 6721 port { 6722 swao_prio3_tpdm_out: endpoint { 6723 remote-endpoint = <&aoss_tpda_in3>; 6724 }; 6725 }; 6726 }; 6727 }; 6728 6729 tpdm@11c0d000 { 6730 compatible = "qcom,coresight-tpdm", "arm,primecell"; 6731 reg = <0x0 0x11c0d000 0x0 0x1000>; 6732 6733 clocks = <&aoss_qmp>; 6734 clock-names = "apb_pclk"; 6735 6736 qcom,dsb-element-bits = <32>; 6737 qcom,dsb-msrs-num = <32>; 6738 6739 out-ports { 6740 port { 6741 swao_tpdm_out: endpoint { 6742 remote-endpoint = <&aoss_tpda_in5>; 6743 }; 6744 }; 6745 }; 6746 }; 6747 6748 apps_smmu: iommu@15000000 { 6749 compatible = "qcom,glymur-smmu-500", 6750 "qcom,smmu-500", 6751 "arm,mmu-500"; 6752 reg = <0x0 0x15000000 0x0 0x100000>; 6753 6754 #iommu-cells = <2>; 6755 #global-interrupts = <1>; 6756 6757 interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>, 6758 <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>, 6759 <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>, 6760 <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>, 6761 <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>, 6762 <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>, 6763 <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>, 6764 <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>, 6765 <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>, 6766 <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>, 6767 <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>, 6768 <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>, 6769 <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>, 6770 <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>, 6771 <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>, 6772 <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>, 6773 <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>, 6774 <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>, 6775 <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>, 6776 <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>, 6777 <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>, 6778 <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>, 6779 <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>, 6780 <GIC_SPI 181 IRQ_TYPE_LEVEL_HIGH>, 6781 <GIC_SPI 182 IRQ_TYPE_LEVEL_HIGH>, 6782 <GIC_SPI 183 IRQ_TYPE_LEVEL_HIGH>, 6783 <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>, 6784 <GIC_SPI 185 IRQ_TYPE_LEVEL_HIGH>, 6785 <GIC_SPI 186 IRQ_TYPE_LEVEL_HIGH>, 6786 <GIC_SPI 187 IRQ_TYPE_LEVEL_HIGH>, 6787 <GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>, 6788 <GIC_SPI 189 IRQ_TYPE_LEVEL_HIGH>, 6789 <GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>, 6790 <GIC_SPI 191 IRQ_TYPE_LEVEL_HIGH>, 6791 <GIC_SPI 192 IRQ_TYPE_LEVEL_HIGH>, 6792 <GIC_SPI 315 IRQ_TYPE_LEVEL_HIGH>, 6793 <GIC_SPI 316 IRQ_TYPE_LEVEL_HIGH>, 6794 <GIC_SPI 317 IRQ_TYPE_LEVEL_HIGH>, 6795 <GIC_SPI 318 IRQ_TYPE_LEVEL_HIGH>, 6796 <GIC_SPI 319 IRQ_TYPE_LEVEL_HIGH>, 6797 <GIC_SPI 320 IRQ_TYPE_LEVEL_HIGH>, 6798 <GIC_SPI 321 IRQ_TYPE_LEVEL_HIGH>, 6799 <GIC_SPI 322 IRQ_TYPE_LEVEL_HIGH>, 6800 <GIC_SPI 323 IRQ_TYPE_LEVEL_HIGH>, 6801 <GIC_SPI 324 IRQ_TYPE_LEVEL_HIGH>, 6802 <GIC_SPI 325 IRQ_TYPE_LEVEL_HIGH>, 6803 <GIC_SPI 326 IRQ_TYPE_LEVEL_HIGH>, 6804 <GIC_SPI 327 IRQ_TYPE_LEVEL_HIGH>, 6805 <GIC_SPI 328 IRQ_TYPE_LEVEL_HIGH>, 6806 <GIC_SPI 329 IRQ_TYPE_LEVEL_HIGH>, 6807 <GIC_SPI 330 IRQ_TYPE_LEVEL_HIGH>, 6808 <GIC_SPI 331 IRQ_TYPE_LEVEL_HIGH>, 6809 <GIC_SPI 332 IRQ_TYPE_LEVEL_HIGH>, 6810 <GIC_SPI 333 IRQ_TYPE_LEVEL_HIGH>, 6811 <GIC_SPI 334 IRQ_TYPE_LEVEL_HIGH>, 6812 <GIC_SPI 335 IRQ_TYPE_LEVEL_HIGH>, 6813 <GIC_SPI 336 IRQ_TYPE_LEVEL_HIGH>, 6814 <GIC_SPI 337 IRQ_TYPE_LEVEL_HIGH>, 6815 <GIC_SPI 338 IRQ_TYPE_LEVEL_HIGH>, 6816 <GIC_SPI 339 IRQ_TYPE_LEVEL_HIGH>, 6817 <GIC_SPI 340 IRQ_TYPE_LEVEL_HIGH>, 6818 <GIC_SPI 341 IRQ_TYPE_LEVEL_HIGH>, 6819 <GIC_SPI 342 IRQ_TYPE_LEVEL_HIGH>, 6820 <GIC_SPI 343 IRQ_TYPE_LEVEL_HIGH>, 6821 <GIC_SPI 344 IRQ_TYPE_LEVEL_HIGH>, 6822 <GIC_SPI 345 IRQ_TYPE_LEVEL_HIGH>, 6823 <GIC_SPI 395 IRQ_TYPE_LEVEL_HIGH>, 6824 <GIC_SPI 396 IRQ_TYPE_LEVEL_HIGH>, 6825 <GIC_SPI 397 IRQ_TYPE_LEVEL_HIGH>, 6826 <GIC_SPI 398 IRQ_TYPE_LEVEL_HIGH>, 6827 <GIC_SPI 399 IRQ_TYPE_LEVEL_HIGH>, 6828 <GIC_SPI 400 IRQ_TYPE_LEVEL_HIGH>, 6829 <GIC_SPI 401 IRQ_TYPE_LEVEL_HIGH>, 6830 <GIC_SPI 402 IRQ_TYPE_LEVEL_HIGH>, 6831 <GIC_SPI 403 IRQ_TYPE_LEVEL_HIGH>, 6832 <GIC_SPI 404 IRQ_TYPE_LEVEL_HIGH>, 6833 <GIC_SPI 405 IRQ_TYPE_LEVEL_HIGH>, 6834 <GIC_SPI 406 IRQ_TYPE_LEVEL_HIGH>, 6835 <GIC_SPI 407 IRQ_TYPE_LEVEL_HIGH>, 6836 <GIC_SPI 408 IRQ_TYPE_LEVEL_HIGH>, 6837 <GIC_SPI 409 IRQ_TYPE_LEVEL_HIGH>, 6838 <GIC_SPI 418 IRQ_TYPE_LEVEL_HIGH>, 6839 <GIC_SPI 419 IRQ_TYPE_LEVEL_HIGH>, 6840 <GIC_SPI 412 IRQ_TYPE_LEVEL_HIGH>, 6841 <GIC_SPI 421 IRQ_TYPE_LEVEL_HIGH>, 6842 <GIC_SPI 707 IRQ_TYPE_LEVEL_HIGH>, 6843 <GIC_SPI 423 IRQ_TYPE_LEVEL_HIGH>, 6844 <GIC_SPI 424 IRQ_TYPE_LEVEL_HIGH>, 6845 <GIC_SPI 425 IRQ_TYPE_LEVEL_HIGH>, 6846 <GIC_SPI 690 IRQ_TYPE_LEVEL_HIGH>, 6847 <GIC_SPI 691 IRQ_TYPE_LEVEL_HIGH>, 6848 <GIC_SPI 692 IRQ_TYPE_LEVEL_HIGH>, 6849 <GIC_SPI 693 IRQ_TYPE_LEVEL_HIGH>, 6850 <GIC_SPI 694 IRQ_TYPE_LEVEL_HIGH>, 6851 <GIC_SPI 695 IRQ_TYPE_LEVEL_HIGH>, 6852 <GIC_SPI 696 IRQ_TYPE_LEVEL_HIGH>, 6853 <GIC_SPI 697 IRQ_TYPE_LEVEL_HIGH>, 6854 <GIC_SPI 410 IRQ_TYPE_LEVEL_HIGH>, 6855 <GIC_SPI 488 IRQ_TYPE_LEVEL_HIGH>, 6856 <GIC_SPI 489 IRQ_TYPE_LEVEL_HIGH>, 6857 <GIC_SPI 490 IRQ_TYPE_LEVEL_HIGH>, 6858 <GIC_SPI 491 IRQ_TYPE_LEVEL_HIGH>, 6859 <GIC_SPI 492 IRQ_TYPE_LEVEL_HIGH>, 6860 <GIC_SPI 493 IRQ_TYPE_LEVEL_HIGH>, 6861 <GIC_SPI 494 IRQ_TYPE_LEVEL_HIGH>, 6862 <GIC_SPI 495 IRQ_TYPE_LEVEL_HIGH>, 6863 <GIC_SPI 496 IRQ_TYPE_LEVEL_HIGH>, 6864 <GIC_SPI 497 IRQ_TYPE_LEVEL_HIGH>, 6865 <GIC_SPI 498 IRQ_TYPE_LEVEL_HIGH>, 6866 <GIC_SPI 499 IRQ_TYPE_LEVEL_HIGH>, 6867 <GIC_SPI 500 IRQ_TYPE_LEVEL_HIGH>, 6868 <GIC_SPI 501 IRQ_TYPE_LEVEL_HIGH>, 6869 <GIC_SPI 502 IRQ_TYPE_LEVEL_HIGH>; 6870 6871 dma-coherent; 6872 }; 6873 6874 pcie_smmu: iommu@15480000 { 6875 compatible = "arm,smmu-v3"; 6876 reg = <0x0 0x15480000 0x0 0x20000>; 6877 interrupts = <GIC_SPI 964 IRQ_TYPE_LEVEL_HIGH>, 6878 <GIC_SPI 962 IRQ_TYPE_LEVEL_HIGH>, 6879 <GIC_SPI 960 IRQ_TYPE_LEVEL_HIGH>; 6880 interrupt-names = "eventq", "cmdq-sync", "gerror"; 6881 dma-coherent; 6882 #iommu-cells = <1>; 6883 }; 6884 6885 intc: interrupt-controller@17000000 { 6886 compatible = "arm,gic-v3"; 6887 reg = <0x0 0x17000000 0x0 0x10000>, 6888 <0x0 0x17080000 0x0 0x480000>; 6889 6890 interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>; 6891 6892 #interrupt-cells = <3>; 6893 interrupt-controller; 6894 6895 #address-cells = <2>; 6896 #size-cells = <2>; 6897 ranges; 6898 6899 gic_its: msi-controller@17040000 { 6900 compatible = "arm,gic-v3-its"; 6901 reg = <0x0 0x17040000 0x0 0x40000>; 6902 6903 msi-controller; 6904 #msi-cells = <1>; 6905 }; 6906 }; 6907 6908 watchdog@17600000 { 6909 compatible = "qcom,apss-wdt-glymur", "qcom,kpss-wdt"; 6910 reg = <0x0 0x17600000 0x0 0x1000>; 6911 clocks = <&sleep_clk>; 6912 interrupts = <GIC_SPI 0 IRQ_TYPE_EDGE_RISING>; 6913 }; 6914 6915 pdp0_mbox: mailbox@17610000 { 6916 compatible = "qcom,glymur-cpucp-mbox", "qcom,x1e80100-cpucp-mbox"; 6917 reg = <0x0 0x17610000 0 0x8000>, <0 0x19980000 0 0x8000>; 6918 interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>; 6919 #mbox-cells = <1>; 6920 }; 6921 6922 timer@17810000 { 6923 compatible = "arm,armv7-timer-mem"; 6924 reg = <0x0 0x17810000 0x0 0x1000>; 6925 #address-cells = <2>; 6926 #size-cells = <1>; 6927 ranges = <0x0 0x0 0x0 0x0 0x20000000>; 6928 6929 frame@17811000 { 6930 reg = <0x0 0x17811000 0x1000>, 6931 <0x0 0x17812000 0x1000>; 6932 6933 interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>, 6934 <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>; 6935 6936 frame-number = <0>; 6937 }; 6938 6939 frame@17813000 { 6940 reg = <0x0 0x17813000 0x1000>; 6941 6942 interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>; 6943 6944 frame-number = <1>; 6945 6946 status = "disabled"; 6947 }; 6948 6949 frame@17815000 { 6950 reg = <0x0 0x17815000 0x1000>; 6951 6952 interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>; 6953 6954 frame-number = <2>; 6955 6956 status = "disabled"; 6957 }; 6958 6959 frame@17817000 { 6960 reg = <0x0 0x17817000 0x1000>; 6961 6962 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>; 6963 6964 frame-number = <3>; 6965 6966 status = "disabled"; 6967 }; 6968 6969 frame@17819000 { 6970 reg = <0x0 0x17819000 0x1000>; 6971 6972 interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>; 6973 6974 frame-number = <4>; 6975 6976 status = "disabled"; 6977 }; 6978 6979 frame@1781b000 { 6980 reg = <0x0 0x1781b000 0x1000>; 6981 6982 interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>; 6983 6984 frame-number = <5>; 6985 6986 status = "disabled"; 6987 }; 6988 6989 frame@1781d000 { 6990 reg = <0x0 0x1781d000 0x1000>; 6991 6992 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>; 6993 6994 frame-number = <6>; 6995 6996 status = "disabled"; 6997 }; 6998 }; 6999 7000 apps_rsc: rsc@18900000 { 7001 compatible = "qcom,rpmh-rsc"; 7002 label = "apps_rsc"; 7003 reg = <0x0 0x18900000 0x0 0x10000>, 7004 <0x0 0x18910000 0x0 0x10000>, 7005 <0x0 0x18920000 0x0 0x10000>; 7006 reg-names = "drv-0", 7007 "drv-1", 7008 "drv-2"; 7009 interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>, 7010 <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>, 7011 <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>; 7012 qcom,tcs-offset = <0xd00>; 7013 qcom,drv-id = <2>; 7014 qcom,tcs-config = <ACTIVE_TCS 2>, 7015 <SLEEP_TCS 3>, 7016 <WAKE_TCS 3>, 7017 <CONTROL_TCS 0>; 7018 power-domains = <&system_pd>; 7019 7020 apps_bcm_voter: bcm-voter { 7021 compatible = "qcom,bcm-voter"; 7022 }; 7023 7024 rpmhcc: clock-controller { 7025 compatible = "qcom,glymur-rpmh-clk"; 7026 7027 clocks = <&xo_board>; 7028 clock-names = "xo"; 7029 7030 #clock-cells = <1>; 7031 }; 7032 7033 rpmhpd: power-controller { 7034 compatible = "qcom,glymur-rpmhpd"; 7035 7036 operating-points-v2 = <&rpmhpd_opp_table>; 7037 7038 #power-domain-cells = <1>; 7039 7040 rpmhpd_opp_table: opp-table { 7041 compatible = "operating-points-v2"; 7042 7043 rpmhpd_opp_ret: opp-16 { 7044 opp-level = <RPMH_REGULATOR_LEVEL_RETENTION>; 7045 }; 7046 7047 rpmhpd_opp_min_svs: opp-48 { 7048 opp-level = <RPMH_REGULATOR_LEVEL_MIN_SVS>; 7049 }; 7050 7051 rpmhpd_opp_low_svs_d2: opp-52 { 7052 opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS_D2>; 7053 }; 7054 7055 rpmhpd_opp_low_svs_d1: opp-56 { 7056 opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS_D1>; 7057 }; 7058 7059 rpmhpd_opp_low_svs_d0: opp-60 { 7060 opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS_D0>; 7061 }; 7062 7063 rpmhpd_opp_low_svs: opp-64 { 7064 opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS>; 7065 }; 7066 7067 rpmhpd_opp_low_svs_l1: opp-80 { 7068 opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS_L1>; 7069 }; 7070 7071 rpmhpd_opp_svs: opp-128 { 7072 opp-level = <RPMH_REGULATOR_LEVEL_SVS>; 7073 }; 7074 7075 rpmhpd_opp_svs_l0: opp-144 { 7076 opp-level = <RPMH_REGULATOR_LEVEL_SVS_L0>; 7077 }; 7078 7079 rpmhpd_opp_svs_l1: opp-192 { 7080 opp-level = <RPMH_REGULATOR_LEVEL_SVS_L1>; 7081 }; 7082 7083 rpmhpd_opp_nom: opp-256 { 7084 opp-level = <RPMH_REGULATOR_LEVEL_NOM>; 7085 }; 7086 7087 rpmhpd_opp_nom_l1: opp-320 { 7088 opp-level = <RPMH_REGULATOR_LEVEL_NOM_L1>; 7089 }; 7090 7091 rpmhpd_opp_nom_l2: opp-336 { 7092 opp-level = <RPMH_REGULATOR_LEVEL_NOM_L2>; 7093 }; 7094 7095 rpmhpd_opp_turbo: opp-384 { 7096 opp-level = <RPMH_REGULATOR_LEVEL_TURBO>; 7097 }; 7098 7099 rpmhpd_opp_turbo_l1: opp-416 { 7100 opp-level = <RPMH_REGULATOR_LEVEL_TURBO_L1>; 7101 }; 7102 }; 7103 }; 7104 }; 7105 7106 nsi_noc: interconnect@1d600000 { 7107 compatible = "qcom,glymur-nsinoc"; 7108 reg = <0x0 0x1d600000 0x0 0x14080>; 7109 qcom,bcm-voters = <&apps_bcm_voter>; 7110 #interconnect-cells = <2>; 7111 }; 7112 7113 oobm_ss_noc: interconnect@1f300000 { 7114 compatible = "qcom,glymur-oobm-ss-noc"; 7115 reg = <0x0 0x1f300000 0x0 0x49a00>; 7116 qcom,bcm-voters = <&apps_bcm_voter>; 7117 #interconnect-cells = <2>; 7118 }; 7119 7120 system-cache-controller@21800000 { 7121 compatible = "qcom,glymur-llcc"; 7122 reg = <0x0 0x21800000 0x0 0x100000>, 7123 <0x0 0x21a00000 0x0 0x100000>, 7124 <0x0 0x21c00000 0x0 0x100000>, 7125 <0x0 0x21e00000 0x0 0x100000>, 7126 <0x0 0x22800000 0x0 0x100000>, 7127 <0x0 0x22a00000 0x0 0x100000>, 7128 <0x0 0x22c00000 0x0 0x100000>, 7129 <0x0 0x22e00000 0x0 0x100000>, 7130 <0x0 0x23800000 0x0 0x100000>, 7131 <0x0 0x23a00000 0x0 0x100000>, 7132 <0x0 0x23c00000 0x0 0x100000>, 7133 <0x0 0x23e00000 0x0 0x100000>, 7134 <0x0 0x20400000 0x0 0x100000>, 7135 <0x0 0x20600000 0x0 0x100000>; 7136 reg-names = "llcc0_base", 7137 "llcc1_base", 7138 "llcc2_base", 7139 "llcc3_base", 7140 "llcc4_base", 7141 "llcc5_base", 7142 "llcc6_base", 7143 "llcc7_base", 7144 "llcc8_base", 7145 "llcc9_base", 7146 "llcc10_base", 7147 "llcc11_base", 7148 "llcc_broadcast_base", 7149 "llcc_broadcast_and_base"; 7150 7151 interrupts = <GIC_SPI 266 IRQ_TYPE_LEVEL_HIGH>; 7152 }; 7153 7154 remoteproc_cdsp: remoteproc@32300000 { 7155 compatible = "qcom,glymur-cdsp-pas", "qcom,sm8550-cdsp-pas"; 7156 reg = <0x0 0x32300000 0x0 0x10000>; 7157 7158 iommus = <&apps_smmu 0x2400 0x400>; 7159 7160 interrupts-extended = <&intc GIC_SPI 578 IRQ_TYPE_EDGE_RISING>, 7161 <&smp2p_cdsp_in 0 IRQ_TYPE_EDGE_RISING>, 7162 <&smp2p_cdsp_in 1 IRQ_TYPE_EDGE_RISING>, 7163 <&smp2p_cdsp_in 2 IRQ_TYPE_EDGE_RISING>, 7164 <&smp2p_cdsp_in 3 IRQ_TYPE_EDGE_RISING>, 7165 <&smp2p_cdsp_in 7 IRQ_TYPE_EDGE_RISING>; 7166 interrupt-names = "wdog", 7167 "fatal", 7168 "ready", 7169 "handover", 7170 "stop-ack", 7171 "shutdown-ack"; 7172 7173 clocks = <&rpmhcc RPMH_CXO_CLK>; 7174 clock-names = "xo"; 7175 7176 interconnects = <&nsp_noc MASTER_CDSP_PROC QCOM_ICC_TAG_ALWAYS 7177 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 7178 7179 power-domains = <&rpmhpd RPMHPD_CX>, 7180 <&rpmhpd RPMHPD_MXC>, 7181 <&rpmhpd RPMHPD_NSP>; 7182 power-domain-names = "cx", 7183 "mxc", 7184 "nsp"; 7185 7186 memory-region = <&cdsp_mem>, <&q6_cdsp_dtb_mem>; 7187 qcom,qmp = <&aoss_qmp>; 7188 qcom,smem-states = <&smp2p_cdsp_out 0>; 7189 qcom,smem-state-names = "stop"; 7190 7191 status = "disabled"; 7192 7193 glink-edge { 7194 interrupts-extended = <&ipcc IPCC_MPROC_CDSP 7195 IPCC_MPROC_SIGNAL_GLINK_QMP 7196 IRQ_TYPE_EDGE_RISING>; 7197 mboxes = <&ipcc IPCC_MPROC_CDSP 7198 IPCC_MPROC_SIGNAL_GLINK_QMP>; 7199 qcom,remote-pid = <5>; 7200 label = "cdsp"; 7201 7202 fastrpc { 7203 compatible = "qcom,glymur-fastrpc", "qcom,kaanapali-fastrpc"; 7204 qcom,glink-channels = "fastrpcglink-apps-dsp"; 7205 label = "cdsp"; 7206 #address-cells = <1>; 7207 #size-cells = <0>; 7208 7209 compute-cb@1 { 7210 compatible = "qcom,fastrpc-compute-cb"; 7211 reg = <1>; 7212 7213 iommus = <&apps_smmu 0x2401 0x440>, 7214 <&apps_smmu 0x1961 0x0>, 7215 <&apps_smmu 0x19c1 0x0>; 7216 dma-coherent; 7217 }; 7218 7219 compute-cb@2 { 7220 compatible = "qcom,fastrpc-compute-cb"; 7221 reg = <2>; 7222 7223 iommus = <&apps_smmu 0x2402 0x440>, 7224 <&apps_smmu 0x1962 0x0>, 7225 <&apps_smmu 0x19c2 0x0>; 7226 dma-coherent; 7227 }; 7228 7229 compute-cb@3 { 7230 compatible = "qcom,fastrpc-compute-cb"; 7231 reg = <3>; 7232 7233 iommus = <&apps_smmu 0x2403 0x440>, 7234 <&apps_smmu 0x1963 0x0>, 7235 <&apps_smmu 0x19c3 0x0>; 7236 dma-coherent; 7237 }; 7238 7239 compute-cb@4 { 7240 compatible = "qcom,fastrpc-compute-cb"; 7241 reg = <4>; 7242 7243 iommus = <&apps_smmu 0x2404 0x440>, 7244 <&apps_smmu 0x1964 0x0>, 7245 <&apps_smmu 0x19c4 0x0>; 7246 dma-coherent; 7247 }; 7248 7249 compute-cb@5 { 7250 compatible = "qcom,fastrpc-compute-cb"; 7251 reg = <5>; 7252 7253 iommus = <&apps_smmu 0x2405 0x440>, 7254 <&apps_smmu 0x1965 0x0>, 7255 <&apps_smmu 0x19c5 0x0>; 7256 dma-coherent; 7257 }; 7258 7259 compute-cb@6 { 7260 compatible = "qcom,fastrpc-compute-cb"; 7261 reg = <6>; 7262 7263 iommus = <&apps_smmu 0x2406 0x440>, 7264 <&apps_smmu 0x1966 0x0>, 7265 <&apps_smmu 0x19c6 0x0>; 7266 dma-coherent; 7267 }; 7268 7269 compute-cb@7 { 7270 compatible = "qcom,fastrpc-compute-cb"; 7271 reg = <7>; 7272 7273 iommus = <&apps_smmu 0x2407 0x440>, 7274 <&apps_smmu 0x1967 0x0>, 7275 <&apps_smmu 0x19c7 0x0>; 7276 dma-coherent; 7277 }; 7278 7279 compute-cb@8 { 7280 compatible = "qcom,fastrpc-compute-cb"; 7281 reg = <8>; 7282 7283 iommus = <&apps_smmu 0x2408 0x440>, 7284 <&apps_smmu 0x1968 0x0>, 7285 <&apps_smmu 0x19c8 0x0>; 7286 dma-coherent; 7287 }; 7288 7289 /* note: compute-cb@9 is secure */ 7290 7291 compute-cb@10 { 7292 compatible = "qcom,fastrpc-compute-cb"; 7293 reg = <10>; 7294 7295 iommus = <&apps_smmu 0x240c 0x440>, 7296 <&apps_smmu 0x196c 0x0>, 7297 <&apps_smmu 0x19cc 0x0>; 7298 dma-coherent; 7299 }; 7300 7301 compute-cb@11 { 7302 compatible = "qcom,fastrpc-compute-cb"; 7303 reg = <11>; 7304 7305 iommus = <&apps_smmu 0x240d 0x440>, 7306 <&apps_smmu 0x196d 0x0>, 7307 <&apps_smmu 0x19cd 0x0>; 7308 dma-coherent; 7309 }; 7310 7311 compute-cb@12 { 7312 compatible = "qcom,fastrpc-compute-cb"; 7313 reg = <12>; 7314 7315 iommus = <&apps_smmu 0x240e 0x440>, 7316 <&apps_smmu 0x196e 0x0>, 7317 <&apps_smmu 0x19ce 0x0>; 7318 dma-coherent; 7319 }; 7320 }; 7321 }; 7322 }; 7323 7324 nsp_noc: interconnect@320c0000 { 7325 compatible = "qcom,glymur-nsp-noc"; 7326 reg = <0x0 0x320c0000 0x0 0x21280>; 7327 qcom,bcm-voters = <&apps_bcm_voter>; 7328 #interconnect-cells = <2>; 7329 }; 7330 7331 qfprom: efuse@361c8000 { 7332 compatible = "qcom,glymur-qfprom", "qcom,qfprom"; 7333 reg = <0x0 0x361c8000 0x0 0x1000>; 7334 #address-cells = <1>; 7335 #size-cells = <1>; 7336 7337 gpu_speed_bin: gpu-speed-bin@138 { 7338 reg = <0x138 0x2>; 7339 bits = <0 9>; 7340 }; 7341 }; 7342 7343 imem: sram@81e08600 { 7344 compatible = "mmio-sram"; 7345 reg = <0x0 0x81e08600 0x0 0x300>; 7346 7347 #address-cells = <1>; 7348 #size-cells = <1>; 7349 ranges = <0x0 0x0 0x81e08600 0x300>; 7350 7351 cpu_scp_lpri0: scp-sram-section@0 { 7352 compatible = "arm,scmi-shmem"; 7353 reg = <0x0 0x180>; 7354 }; 7355 7356 cpu_scp_lpri1: scp-sram-section@180 { 7357 compatible = "arm,scmi-shmem"; 7358 reg = <0x180 0x180>; 7359 }; 7360 }; 7361 }; 7362 7363 timer { 7364 compatible = "arm,armv8-timer"; 7365 interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_LOW>, 7366 <GIC_PPI 14 IRQ_TYPE_LEVEL_LOW>, 7367 <GIC_PPI 11 IRQ_TYPE_LEVEL_LOW>, 7368 <GIC_PPI 10 IRQ_TYPE_LEVEL_LOW>, 7369 <GIC_PPI 12 IRQ_TYPE_LEVEL_LOW>; 7370 }; 7371 7372 thermal_zones: thermal-zones { 7373 aoss-0-thermal { 7374 thermal-sensors = <&tsens0 0>; 7375 7376 trips { 7377 aoss-0-critical { 7378 temperature = <115000>; 7379 hysteresis = <1000>; 7380 type = "critical"; 7381 }; 7382 }; 7383 }; 7384 7385 cpu-0-0-0-thermal { 7386 thermal-sensors = <&tsens0 1>; 7387 7388 trips { 7389 cpu-0-0-0-critical { 7390 temperature = <115000>; 7391 hysteresis = <1000>; 7392 type = "critical"; 7393 }; 7394 }; 7395 }; 7396 7397 cpu-0-0-1-thermal { 7398 thermal-sensors = <&tsens0 2>; 7399 7400 trips { 7401 cpu-0-0-1-critical { 7402 temperature = <115000>; 7403 hysteresis = <1000>; 7404 type = "critical"; 7405 }; 7406 }; 7407 }; 7408 7409 cpu-0-1-0-thermal { 7410 thermal-sensors = <&tsens0 3>; 7411 7412 trips { 7413 cpu-0-1-0-critical { 7414 temperature = <115000>; 7415 hysteresis = <1000>; 7416 type = "critical"; 7417 }; 7418 }; 7419 }; 7420 7421 cpu-0-1-1-thermal { 7422 thermal-sensors = <&tsens0 4>; 7423 7424 trips { 7425 cpu-0-1-1-critical { 7426 temperature = <115000>; 7427 hysteresis = <1000>; 7428 type = "critical"; 7429 }; 7430 }; 7431 }; 7432 7433 cpu-0-2-0-thermal { 7434 thermal-sensors = <&tsens0 5>; 7435 7436 trips { 7437 cpu-0-2-0-critical { 7438 temperature = <115000>; 7439 hysteresis = <1000>; 7440 type = "critical"; 7441 }; 7442 }; 7443 }; 7444 7445 cpu-0-2-1-thermal { 7446 thermal-sensors = <&tsens0 6>; 7447 7448 trips { 7449 cpu-0-2-1-critical { 7450 temperature = <115000>; 7451 hysteresis = <1000>; 7452 type = "critical"; 7453 }; 7454 }; 7455 }; 7456 7457 cpu-0-3-0-thermal { 7458 thermal-sensors = <&tsens0 7>; 7459 7460 trips { 7461 cpu-0-3-0-critical { 7462 temperature = <115000>; 7463 hysteresis = <1000>; 7464 type = "critical"; 7465 }; 7466 }; 7467 }; 7468 7469 cpu-0-3-1-thermal { 7470 thermal-sensors = <&tsens0 8>; 7471 7472 trips { 7473 cpu-0-3-1-critical { 7474 temperature = <115000>; 7475 hysteresis = <1000>; 7476 type = "critical"; 7477 }; 7478 }; 7479 }; 7480 7481 cpu-0-4-0-thermal { 7482 thermal-sensors = <&tsens0 9>; 7483 7484 trips { 7485 cpu-0-4-0-critical { 7486 temperature = <115000>; 7487 hysteresis = <1000>; 7488 type = "critical"; 7489 }; 7490 }; 7491 }; 7492 7493 cpu-0-4-1-thermal { 7494 thermal-sensors = <&tsens0 10>; 7495 7496 trips { 7497 cpu-0-4-1-critical { 7498 temperature = <115000>; 7499 hysteresis = <1000>; 7500 type = "critical"; 7501 }; 7502 }; 7503 }; 7504 7505 cpu-0-5-0-thermal { 7506 thermal-sensors = <&tsens0 11>; 7507 7508 trips { 7509 cpu-0-5-0-critical { 7510 temperature = <115000>; 7511 hysteresis = <1000>; 7512 type = "critical"; 7513 }; 7514 }; 7515 }; 7516 7517 cpu-0-5-1-thermal { 7518 thermal-sensors = <&tsens0 12>; 7519 7520 trips { 7521 cpu-0-5-1-critical { 7522 temperature = <115000>; 7523 hysteresis = <1000>; 7524 type = "critical"; 7525 }; 7526 }; 7527 }; 7528 7529 aoss-1-thermal { 7530 thermal-sensors = <&tsens1 0>; 7531 7532 trips { 7533 aoss-1-critical { 7534 temperature = <115000>; 7535 hysteresis = <1000>; 7536 type = "critical"; 7537 }; 7538 }; 7539 }; 7540 7541 cpullc-0-0-thermal { 7542 thermal-sensors = <&tsens1 1>; 7543 7544 trips { 7545 cpullc-0-0-critical { 7546 temperature = <115000>; 7547 hysteresis = <1000>; 7548 type = "critical"; 7549 }; 7550 }; 7551 }; 7552 7553 cpullc-0-1-thermal { 7554 thermal-sensors = <&tsens1 2>; 7555 7556 trips { 7557 cpullc-0-1-critical { 7558 temperature = <115000>; 7559 hysteresis = <1000>; 7560 type = "critical"; 7561 }; 7562 }; 7563 }; 7564 7565 qmx-0-0-thermal { 7566 thermal-sensors = <&tsens1 3>; 7567 7568 trips { 7569 qmx-0-0-critical { 7570 temperature = <115000>; 7571 hysteresis = <1000>; 7572 type = "critical"; 7573 }; 7574 }; 7575 }; 7576 7577 qmx-0-1-thermal { 7578 thermal-sensors = <&tsens1 4>; 7579 7580 trips { 7581 qmx-0-1-critical { 7582 temperature = <115000>; 7583 hysteresis = <1000>; 7584 type = "critical"; 7585 }; 7586 }; 7587 }; 7588 7589 qmx-0-2-thermal { 7590 thermal-sensors = <&tsens1 5>; 7591 7592 trips { 7593 qmx-0-2-critical { 7594 temperature = <115000>; 7595 hysteresis = <1000>; 7596 type = "critical"; 7597 }; 7598 }; 7599 }; 7600 7601 ddr-0-thermal { 7602 thermal-sensors = <&tsens1 6>; 7603 7604 trips { 7605 ddr-0-critical { 7606 temperature = <115000>; 7607 hysteresis = <1000>; 7608 type = "critical"; 7609 }; 7610 }; 7611 }; 7612 7613 thermal_video_0: video-0-thermal { 7614 thermal-sensors = <&tsens1 7>; 7615 7616 trips { 7617 video-0-critical { 7618 temperature = <115000>; 7619 hysteresis = <1000>; 7620 type = "critical"; 7621 }; 7622 }; 7623 }; 7624 7625 thermal_video_1: video-1-thermal { 7626 thermal-sensors = <&tsens1 8>; 7627 7628 trips { 7629 video-1-critical { 7630 temperature = <115000>; 7631 hysteresis = <1000>; 7632 type = "critical"; 7633 }; 7634 }; 7635 }; 7636 7637 aoss-2-thermal { 7638 thermal-sensors = <&tsens2 0>; 7639 7640 trips { 7641 aoss-2-critical { 7642 temperature = <115000>; 7643 hysteresis = <1000>; 7644 type = "critical"; 7645 }; 7646 }; 7647 }; 7648 7649 cpu-1-0-0-thermal { 7650 thermal-sensors = <&tsens2 1>; 7651 7652 trips { 7653 cpu-1-0-0-critical { 7654 temperature = <115000>; 7655 hysteresis = <1000>; 7656 type = "critical"; 7657 }; 7658 }; 7659 }; 7660 7661 cpu-1-0-1-thermal { 7662 thermal-sensors = <&tsens2 2>; 7663 7664 trips { 7665 cpu-1-0-1-critical { 7666 temperature = <115000>; 7667 hysteresis = <1000>; 7668 type = "critical"; 7669 }; 7670 }; 7671 }; 7672 7673 cpu-1-1-0-thermal { 7674 thermal-sensors = <&tsens2 3>; 7675 7676 trips { 7677 cpu-1-1-0-critical { 7678 temperature = <115000>; 7679 hysteresis = <1000>; 7680 type = "critical"; 7681 }; 7682 }; 7683 }; 7684 7685 cpu-1-1-1-thermal { 7686 thermal-sensors = <&tsens2 4>; 7687 7688 trips { 7689 cpu-1-1-1-critical { 7690 temperature = <115000>; 7691 hysteresis = <1000>; 7692 type = "critical"; 7693 }; 7694 }; 7695 }; 7696 7697 cpu-1-2-0-thermal { 7698 thermal-sensors = <&tsens2 5>; 7699 7700 trips { 7701 cpu-1-2-0-critical { 7702 temperature = <115000>; 7703 hysteresis = <1000>; 7704 type = "critical"; 7705 }; 7706 }; 7707 }; 7708 7709 cpu-1-2-1-thermal { 7710 thermal-sensors = <&tsens2 6>; 7711 7712 trips { 7713 cpu-1-2-1-critical { 7714 temperature = <115000>; 7715 hysteresis = <1000>; 7716 type = "critical"; 7717 }; 7718 }; 7719 }; 7720 7721 cpu-1-3-0-thermal { 7722 thermal-sensors = <&tsens2 7>; 7723 7724 trips { 7725 cpu-1-3-0-critical { 7726 temperature = <115000>; 7727 hysteresis = <1000>; 7728 type = "critical"; 7729 }; 7730 }; 7731 }; 7732 7733 cpu-1-3-1-thermal { 7734 thermal-sensors = <&tsens2 8>; 7735 7736 trips { 7737 cpu-1-3-1-critical { 7738 temperature = <115000>; 7739 hysteresis = <1000>; 7740 type = "critical"; 7741 }; 7742 }; 7743 }; 7744 7745 cpu-1-4-0-thermal { 7746 thermal-sensors = <&tsens2 9>; 7747 7748 trips { 7749 cpu-1-4-0-critical { 7750 temperature = <115000>; 7751 hysteresis = <1000>; 7752 type = "critical"; 7753 }; 7754 }; 7755 }; 7756 7757 cpu-1-4-1-thermal { 7758 thermal-sensors = <&tsens2 10>; 7759 7760 trips { 7761 cpu-1-4-1-critical { 7762 temperature = <115000>; 7763 hysteresis = <1000>; 7764 type = "critical"; 7765 }; 7766 }; 7767 }; 7768 7769 cpu-1-5-0-thermal { 7770 thermal-sensors = <&tsens2 11>; 7771 7772 trips { 7773 cpu-1-5-0-critical { 7774 temperature = <115000>; 7775 hysteresis = <1000>; 7776 type = "critical"; 7777 }; 7778 }; 7779 }; 7780 7781 cpu-1-5-1-thermal { 7782 thermal-sensors = <&tsens2 12>; 7783 7784 trips { 7785 cpu-1-5-1-critical { 7786 temperature = <115000>; 7787 hysteresis = <1000>; 7788 type = "critical"; 7789 }; 7790 }; 7791 }; 7792 7793 aoss-3-thermal { 7794 thermal-sensors = <&tsens3 0>; 7795 7796 trips { 7797 aoss-3-critical { 7798 temperature = <115000>; 7799 hysteresis = <1000>; 7800 type = "critical"; 7801 }; 7802 }; 7803 }; 7804 7805 cpullc-1-0-thermal { 7806 thermal-sensors = <&tsens3 1>; 7807 7808 trips { 7809 cpullc-1-0-critical { 7810 temperature = <115000>; 7811 hysteresis = <1000>; 7812 type = "critical"; 7813 }; 7814 }; 7815 }; 7816 7817 cpullc-1-1-thermal { 7818 thermal-sensors = <&tsens3 2>; 7819 7820 trips { 7821 cpullc-1-1-critical { 7822 temperature = <115000>; 7823 hysteresis = <1000>; 7824 type = "critical"; 7825 }; 7826 }; 7827 }; 7828 7829 qmx-1-0-thermal { 7830 thermal-sensors = <&tsens3 3>; 7831 7832 trips { 7833 qmx-1-0-critical { 7834 temperature = <115000>; 7835 hysteresis = <1000>; 7836 type = "critical"; 7837 }; 7838 }; 7839 }; 7840 7841 qmx-1-1-thermal { 7842 thermal-sensors = <&tsens3 4>; 7843 7844 trips { 7845 qmx-1-1-critical { 7846 temperature = <115000>; 7847 hysteresis = <1000>; 7848 type = "critical"; 7849 }; 7850 }; 7851 }; 7852 7853 qmx-1-2-thermal { 7854 thermal-sensors = <&tsens3 5>; 7855 7856 trips { 7857 qmx-1-2-critical { 7858 temperature = <115000>; 7859 hysteresis = <1000>; 7860 type = "critical"; 7861 }; 7862 }; 7863 }; 7864 7865 qmx-1-3-thermal { 7866 thermal-sensors = <&tsens3 6>; 7867 7868 trips { 7869 qmx-1-3-critical { 7870 temperature = <115000>; 7871 hysteresis = <1000>; 7872 type = "critical"; 7873 }; 7874 }; 7875 }; 7876 7877 qmx-1-4-thermal { 7878 thermal-sensors = <&tsens3 7>; 7879 7880 trips { 7881 qmx-1-4-critical { 7882 temperature = <115000>; 7883 hysteresis = <1000>; 7884 type = "critical"; 7885 }; 7886 }; 7887 }; 7888 7889 aoss-4-thermal { 7890 thermal-sensors = <&tsens4 0>; 7891 7892 trips { 7893 aoss-4-critical { 7894 temperature = <115000>; 7895 hysteresis = <1000>; 7896 type = "critical"; 7897 }; 7898 }; 7899 }; 7900 7901 thermal_cpu_2_0_0: cpu-2-0-0-thermal { 7902 thermal-sensors = <&tsens4 1>; 7903 7904 trips { 7905 cpu-2-0-0-critical { 7906 temperature = <115000>; 7907 hysteresis = <1000>; 7908 type = "critical"; 7909 }; 7910 }; 7911 }; 7912 7913 thermal_cpu_2_0_1: cpu-2-0-1-thermal { 7914 thermal-sensors = <&tsens4 2>; 7915 7916 trips { 7917 cpu-2-0-1-critical { 7918 temperature = <115000>; 7919 hysteresis = <1000>; 7920 type = "critical"; 7921 }; 7922 }; 7923 }; 7924 7925 thermal_cpu_2_1_0: cpu-2-1-0-thermal { 7926 thermal-sensors = <&tsens4 3>; 7927 7928 trips { 7929 cpu-2-1-0-critical { 7930 temperature = <115000>; 7931 hysteresis = <1000>; 7932 type = "critical"; 7933 }; 7934 }; 7935 }; 7936 7937 thermal_cpu_2_1_1: cpu-2-1-1-thermal { 7938 thermal-sensors = <&tsens4 4>; 7939 7940 trips { 7941 cpu-2-1-1-critical { 7942 temperature = <115000>; 7943 hysteresis = <1000>; 7944 type = "critical"; 7945 }; 7946 }; 7947 }; 7948 7949 thermal_cpu_2_2_0: cpu-2-2-0-thermal { 7950 thermal-sensors = <&tsens4 5>; 7951 7952 trips { 7953 cpu-2-2-0-critical { 7954 temperature = <115000>; 7955 hysteresis = <1000>; 7956 type = "critical"; 7957 }; 7958 }; 7959 }; 7960 7961 thermal_cpu_2_2_1: cpu-2-2-1-thermal { 7962 thermal-sensors = <&tsens4 6>; 7963 7964 trips { 7965 cpu-2-2-1-critical { 7966 temperature = <115000>; 7967 hysteresis = <1000>; 7968 type = "critical"; 7969 }; 7970 }; 7971 }; 7972 7973 thermal_cpu_2_3_0: cpu-2-3-0-thermal { 7974 thermal-sensors = <&tsens4 7>; 7975 7976 trips { 7977 cpu-2-3-0-critical { 7978 temperature = <115000>; 7979 hysteresis = <1000>; 7980 type = "critical"; 7981 }; 7982 }; 7983 }; 7984 7985 thermal_cpu_2_3_1: cpu-2-3-1-thermal { 7986 thermal-sensors = <&tsens4 8>; 7987 7988 trips { 7989 cpu-2-3-1-critical { 7990 temperature = <115000>; 7991 hysteresis = <1000>; 7992 type = "critical"; 7993 }; 7994 }; 7995 }; 7996 7997 thermal_cpu_2_4_0: cpu-2-4-0-thermal { 7998 thermal-sensors = <&tsens4 9>; 7999 8000 trips { 8001 cpu-2-4-0-critical { 8002 temperature = <115000>; 8003 hysteresis = <1000>; 8004 type = "critical"; 8005 }; 8006 }; 8007 }; 8008 8009 thermal_cpu_2_4_1: cpu-2-4-1-thermal { 8010 thermal-sensors = <&tsens4 10>; 8011 8012 trips { 8013 cpu-2-4-1-critical { 8014 temperature = <115000>; 8015 hysteresis = <1000>; 8016 type = "critical"; 8017 }; 8018 }; 8019 }; 8020 8021 thermal_cpu_2_5_0: cpu-2-5-0-thermal { 8022 thermal-sensors = <&tsens4 11>; 8023 8024 trips { 8025 cpu-2-5-0-critical { 8026 temperature = <115000>; 8027 hysteresis = <1000>; 8028 type = "critical"; 8029 }; 8030 }; 8031 }; 8032 8033 thermal_cpu_2_5_1: cpu-2-5-1-thermal { 8034 thermal-sensors = <&tsens4 12>; 8035 8036 trips { 8037 cpu-2-5-1-critical { 8038 temperature = <115000>; 8039 hysteresis = <1000>; 8040 type = "critical"; 8041 }; 8042 }; 8043 }; 8044 8045 aoss-5-thermal { 8046 thermal-sensors = <&tsens5 0>; 8047 8048 trips { 8049 aoss-5-critical { 8050 temperature = <115000>; 8051 hysteresis = <1000>; 8052 type = "critical"; 8053 }; 8054 }; 8055 }; 8056 8057 thermal_cpullc_2_0: cpullc-2-0-thermal { 8058 thermal-sensors = <&tsens5 1>; 8059 8060 trips { 8061 cpullc-2-0-critical { 8062 temperature = <115000>; 8063 hysteresis = <1000>; 8064 type = "critical"; 8065 }; 8066 }; 8067 }; 8068 8069 thermal_cpuillc_2_1: cpuillc-2-1-thermal { 8070 thermal-sensors = <&tsens5 2>; 8071 8072 trips { 8073 cpullc-2-1-critical { 8074 temperature = <115000>; 8075 hysteresis = <1000>; 8076 type = "critical"; 8077 }; 8078 }; 8079 }; 8080 8081 thermal_qmx_2_0: qmx-2-0-thermal { 8082 thermal-sensors = <&tsens5 3>; 8083 8084 trips { 8085 qmx-2-0-critical { 8086 temperature = <115000>; 8087 hysteresis = <1000>; 8088 type = "critical"; 8089 }; 8090 }; 8091 }; 8092 8093 thermal_qmx_2_1: qmx-2-1-thermal { 8094 thermal-sensors = <&tsens5 4>; 8095 8096 trips { 8097 qmx-2-1-critical { 8098 temperature = <115000>; 8099 hysteresis = <1000>; 8100 type = "critical"; 8101 }; 8102 }; 8103 }; 8104 8105 thermal_qmx_2_2: qmx-2-2-thermal { 8106 thermal-sensors = <&tsens5 5>; 8107 8108 trips { 8109 qmx-2-2-critical { 8110 temperature = <115000>; 8111 hysteresis = <1000>; 8112 type = "critical"; 8113 }; 8114 }; 8115 }; 8116 8117 thermal_qmx_2_3: qmx-2-3-thermal { 8118 thermal-sensors = <&tsens5 6>; 8119 8120 trips { 8121 qmx-2-3-critical { 8122 temperature = <115000>; 8123 hysteresis = <1000>; 8124 type = "critical"; 8125 }; 8126 }; 8127 }; 8128 8129 thermal_qmx_2_4: qmx-2-4-thermal { 8130 thermal-sensors = <&tsens5 7>; 8131 8132 trips { 8133 qmx-2-4-critical { 8134 temperature = <115000>; 8135 hysteresis = <1000>; 8136 type = "critical"; 8137 }; 8138 }; 8139 }; 8140 8141 thermal_aoss_6: aoss-6-thermal { 8142 thermal-sensors = <&tsens6 0>; 8143 8144 trips { 8145 aoss-6-critical { 8146 temperature = <115000>; 8147 hysteresis = <1000>; 8148 type = "critical"; 8149 }; 8150 }; 8151 }; 8152 8153 thermal_nsphvx_0: nsphvx-0-thermal { 8154 thermal-sensors = <&tsens6 1>; 8155 8156 trips { 8157 nsphvx-0-critical { 8158 temperature = <115000>; 8159 hysteresis = <1000>; 8160 type = "critical"; 8161 }; 8162 }; 8163 }; 8164 8165 thermal_nsphvx_1: nsphvx-1-thermal { 8166 thermal-sensors = <&tsens6 2>; 8167 8168 trips { 8169 nsphvx-1-critical { 8170 temperature = <115000>; 8171 hysteresis = <1000>; 8172 type = "critical"; 8173 }; 8174 }; 8175 }; 8176 8177 thermal_nsphvx_2: nsphvx-2-thermal { 8178 thermal-sensors = <&tsens6 3>; 8179 8180 trips { 8181 nsphvx-2-critical { 8182 temperature = <115000>; 8183 hysteresis = <1000>; 8184 type = "critical"; 8185 }; 8186 }; 8187 }; 8188 8189 thermal_nsphvx_3: nsphvx-3-thermal { 8190 thermal-sensors = <&tsens6 4>; 8191 8192 trips { 8193 nsphvx-3-critical { 8194 temperature = <115000>; 8195 hysteresis = <1000>; 8196 type = "critical"; 8197 }; 8198 }; 8199 }; 8200 8201 thermal_nsphmx_0: nsphmx-0-thermal { 8202 thermal-sensors = <&tsens6 5>; 8203 8204 trips { 8205 nsphmx-0-critical { 8206 temperature = <115000>; 8207 hysteresis = <1000>; 8208 type = "critical"; 8209 }; 8210 }; 8211 }; 8212 8213 thermal_nsphmx_1: nsphmx-1-thermal { 8214 thermal-sensors = <&tsens6 6>; 8215 8216 trips { 8217 nsphmx-1-critical { 8218 temperature = <115000>; 8219 hysteresis = <1000>; 8220 type = "critical"; 8221 }; 8222 }; 8223 }; 8224 8225 thermal_nsphmx_2: nsphmx-2-thermal { 8226 thermal-sensors = <&tsens6 7>; 8227 8228 trips { 8229 nsphmx-2-critical { 8230 temperature = <115000>; 8231 hysteresis = <1000>; 8232 type = "critical"; 8233 }; 8234 }; 8235 }; 8236 8237 thermal_nsphmx_3: nsphmx-3-thermal { 8238 thermal-sensors = <&tsens6 8>; 8239 8240 trips { 8241 nsphmx-3-critical { 8242 temperature = <115000>; 8243 hysteresis = <1000>; 8244 type = "critical"; 8245 }; 8246 }; 8247 }; 8248 8249 thermal_camera_0: camera-0-thermal { 8250 thermal-sensors = <&tsens6 9>; 8251 8252 trips { 8253 camera-0-critical { 8254 temperature = <115000>; 8255 hysteresis = <1000>; 8256 type = "critical"; 8257 }; 8258 }; 8259 }; 8260 8261 thermal_camera_1: camera-1-thermal { 8262 thermal-sensors = <&tsens6 10>; 8263 8264 trips { 8265 camera-1-critical { 8266 temperature = <115000>; 8267 hysteresis = <1000>; 8268 type = "critical"; 8269 }; 8270 }; 8271 }; 8272 8273 thermal_ddr_1: ddr-1-thermal { 8274 thermal-sensors = <&tsens6 11>; 8275 8276 trips { 8277 ddr-1-critical { 8278 temperature = <115000>; 8279 hysteresis = <1000>; 8280 type = "critical"; 8281 }; 8282 }; 8283 }; 8284 8285 thermal_ddr_2: ddr-2-thermal { 8286 thermal-sensors = <&tsens6 12>; 8287 8288 trips { 8289 ddr-2-critical { 8290 temperature = <115000>; 8291 hysteresis = <1000>; 8292 type = "critical"; 8293 }; 8294 }; 8295 }; 8296 8297 thermal_aoss_7: aoss-7-thermal { 8298 thermal-sensors = <&tsens7 0>; 8299 8300 trips { 8301 aoss-7-critical { 8302 temperature = <115000>; 8303 hysteresis = <1000>; 8304 type = "critical"; 8305 }; 8306 }; 8307 }; 8308 8309 thermal_gpu_0_0: gpu-0-0-thermal { 8310 thermal-sensors = <&tsens7 1>; 8311 8312 trips { 8313 trip-point0 { 8314 temperature = <90000>; 8315 hysteresis = <5000>; 8316 type = "hot"; 8317 }; 8318 8319 gpu-0-0-critical { 8320 temperature = <115000>; 8321 hysteresis = <1000>; 8322 type = "critical"; 8323 }; 8324 }; 8325 }; 8326 8327 thermal_gpu_0_1: gpu-0-1-thermal { 8328 thermal-sensors = <&tsens7 2>; 8329 8330 trips { 8331 trip-point0 { 8332 temperature = <90000>; 8333 hysteresis = <5000>; 8334 type = "hot"; 8335 }; 8336 8337 gpu-0-1-critical { 8338 temperature = <115000>; 8339 hysteresis = <1000>; 8340 type = "critical"; 8341 }; 8342 }; 8343 }; 8344 8345 thermal_gpu_0_2: gpu-0-2-thermal { 8346 thermal-sensors = <&tsens7 3>; 8347 8348 trips { 8349 trip-point0 { 8350 temperature = <90000>; 8351 hysteresis = <5000>; 8352 type = "hot"; 8353 }; 8354 8355 gpu-0-2-critical { 8356 temperature = <115000>; 8357 hysteresis = <1000>; 8358 type = "critical"; 8359 }; 8360 }; 8361 }; 8362 8363 thermal_gpu_1_0: gpu-1-0-thermal { 8364 thermal-sensors = <&tsens7 4>; 8365 8366 trips { 8367 trip-point0 { 8368 temperature = <90000>; 8369 hysteresis = <5000>; 8370 type = "hot"; 8371 }; 8372 8373 gpu-1-0-critical { 8374 temperature = <115000>; 8375 hysteresis = <1000>; 8376 type = "critical"; 8377 }; 8378 }; 8379 }; 8380 8381 thermal_gpu_1_1: gpu-1-1-thermal { 8382 thermal-sensors = <&tsens7 5>; 8383 8384 trips { 8385 trip-point0 { 8386 temperature = <90000>; 8387 hysteresis = <5000>; 8388 type = "hot"; 8389 }; 8390 8391 gpu-1-1-critical { 8392 temperature = <115000>; 8393 hysteresis = <1000>; 8394 type = "critical"; 8395 }; 8396 }; 8397 }; 8398 8399 thermal_gpu_1_2: gpu-1-2-thermal { 8400 thermal-sensors = <&tsens7 6>; 8401 8402 trips { 8403 trip-point0 { 8404 temperature = <90000>; 8405 hysteresis = <5000>; 8406 type = "hot"; 8407 }; 8408 8409 gpu-1-2-critical { 8410 temperature = <115000>; 8411 hysteresis = <1000>; 8412 type = "critical"; 8413 }; 8414 }; 8415 }; 8416 8417 thermal_gpu_2_0: gpu-2-0-thermal { 8418 thermal-sensors = <&tsens7 7>; 8419 8420 trips { 8421 trip-point0 { 8422 temperature = <90000>; 8423 hysteresis = <5000>; 8424 type = "hot"; 8425 }; 8426 8427 gpu-2-0-critical { 8428 temperature = <115000>; 8429 hysteresis = <1000>; 8430 type = "critical"; 8431 }; 8432 }; 8433 }; 8434 8435 thermal_gpu_2_1: gpu-2-1-thermal { 8436 thermal-sensors = <&tsens7 8>; 8437 8438 trips { 8439 trip-point0 { 8440 temperature = <90000>; 8441 hysteresis = <5000>; 8442 type = "hot"; 8443 }; 8444 8445 gpu-2-1-critical { 8446 temperature = <115000>; 8447 hysteresis = <1000>; 8448 type = "critical"; 8449 }; 8450 }; 8451 }; 8452 8453 thermal_gpu_2_2: gpu-2-2-thermal { 8454 thermal-sensors = <&tsens7 9>; 8455 8456 trips { 8457 trip-point0 { 8458 temperature = <90000>; 8459 hysteresis = <5000>; 8460 type = "hot"; 8461 }; 8462 8463 gpu-2-2-critical { 8464 temperature = <115000>; 8465 hysteresis = <1000>; 8466 type = "critical"; 8467 }; 8468 }; 8469 }; 8470 8471 thermal_gpu_3_0: gpu-3-0-thermal { 8472 thermal-sensors = <&tsens7 10>; 8473 8474 trips { 8475 trip-point0 { 8476 temperature = <90000>; 8477 hysteresis = <5000>; 8478 type = "hot"; 8479 }; 8480 8481 gpu-3-0-critical { 8482 temperature = <115000>; 8483 hysteresis = <1000>; 8484 type = "critical"; 8485 }; 8486 }; 8487 }; 8488 8489 thermal_gpu_3_1: gpu-3-1-thermal { 8490 thermal-sensors = <&tsens7 11>; 8491 8492 trips { 8493 trip-point0 { 8494 temperature = <90000>; 8495 hysteresis = <5000>; 8496 type = "hot"; 8497 }; 8498 8499 gpu-3-1-critical { 8500 temperature = <115000>; 8501 hysteresis = <1000>; 8502 type = "critical"; 8503 }; 8504 }; 8505 }; 8506 8507 thermal_gpu_3_2: gpu-3-2-thermal { 8508 thermal-sensors = <&tsens7 12>; 8509 8510 trips { 8511 trip-point0 { 8512 temperature = <90000>; 8513 hysteresis = <5000>; 8514 type = "hot"; 8515 }; 8516 8517 gpu-3-2-critical { 8518 temperature = <115000>; 8519 hysteresis = <1000>; 8520 type = "critical"; 8521 }; 8522 }; 8523 }; 8524 8525 thermal_gpuss_0: gpuss-0-thermal { 8526 thermal-sensors = <&tsens7 13>; 8527 8528 trips { 8529 trip-point0 { 8530 temperature = <90000>; 8531 hysteresis = <5000>; 8532 type = "hot"; 8533 }; 8534 8535 gpuss-0-critical { 8536 temperature = <115000>; 8537 hysteresis = <1000>; 8538 type = "critical"; 8539 }; 8540 }; 8541 }; 8542 8543 thermal_gpuss_1: gpuss-1-thermal { 8544 thermal-sensors = <&tsens7 14>; 8545 8546 trips { 8547 trip-point0 { 8548 temperature = <90000>; 8549 hysteresis = <5000>; 8550 type = "hot"; 8551 }; 8552 8553 gpuss-1-critical { 8554 temperature = <115000>; 8555 hysteresis = <1000>; 8556 type = "critical"; 8557 }; 8558 }; 8559 }; 8560 }; 8561 8562 tpdm-cdsp-llm { 8563 compatible = "qcom,coresight-static-tpdm"; 8564 qcom,cmb-element-bits = <32>; 8565 8566 out-ports { 8567 port { 8568 cdsp_llm_tpdm_out: endpoint { 8569 remote-endpoint = <&cdsp_tpda_in1>; 8570 }; 8571 }; 8572 }; 8573 }; 8574 8575 tpdm-cdsp-llm2 { 8576 compatible = "qcom,coresight-static-tpdm"; 8577 qcom,cmb-element-bits = <32>; 8578 8579 out-ports { 8580 port { 8581 cdsp_llm2_tpdm_out: endpoint { 8582 remote-endpoint = <&cdsp_tpda_in2>; 8583 }; 8584 }; 8585 }; 8586 }; 8587 8588 tpdm-cdsp-cmsr { 8589 compatible = "qcom,coresight-static-tpdm"; 8590 8591 qcom,cmb-element-bits = <32>; 8592 qcom,dsb-element-bits = <32>; 8593 8594 out-ports { 8595 port { 8596 cdsp_cmsr_tpdm_out: endpoint { 8597 remote-endpoint = <&cdsp_tpda_in3>; 8598 }; 8599 }; 8600 }; 8601 }; 8602 8603 tpdm-cdsp-cmsr2 { 8604 compatible = "qcom,coresight-static-tpdm"; 8605 8606 qcom,cmb-element-bits = <32>; 8607 qcom,dsb-element-bits = <32>; 8608 8609 out-ports { 8610 port { 8611 cdsp_cmsr2_tpdm_out: endpoint { 8612 remote-endpoint = <&cdsp_tpda_in4>; 8613 }; 8614 }; 8615 }; 8616 }; 8617}; 8618