1// SPDX-License-Identifier: BSD-3-Clause 2/* 3 * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. 4 */ 5 6#include <dt-bindings/clock/qcom,dsi-phy-28nm.h> 7#include <dt-bindings/clock/qcom,eliza-dispcc.h> 8#include <dt-bindings/clock/qcom,eliza-gcc.h> 9#include <dt-bindings/clock/qcom,eliza-tcsr.h> 10#include <dt-bindings/clock/qcom,rpmh.h> 11#include <dt-bindings/dma/qcom-gpi.h> 12#include <dt-bindings/gpio/gpio.h> 13#include <dt-bindings/interconnect/qcom,eliza-rpmh.h> 14#include <dt-bindings/interconnect/qcom,icc.h> 15#include <dt-bindings/interconnect/qcom,osm-l3.h> 16#include <dt-bindings/interrupt-controller/arm-gic.h> 17#include <dt-bindings/mailbox/qcom-ipcc.h> 18#include <dt-bindings/phy/phy-qcom-qmp.h> 19#include <dt-bindings/power/qcom,rpmhpd.h> 20#include <dt-bindings/soc/qcom,rpmh-rsc.h> 21 22/ { 23 interrupt-parent = <&intc>; 24 25 #address-cells = <2>; 26 #size-cells = <2>; 27 28 cpus { 29 #address-cells = <2>; 30 #size-cells = <0>; 31 32 cpu0: cpu@0 { 33 device_type = "cpu"; 34 compatible = "arm,cortex-a520"; 35 reg = <0x0 0x0>; 36 37 clocks = <&cpufreq_hw 0>; 38 39 power-domains = <&cpu_pd0>; 40 power-domain-names = "psci"; 41 42 enable-method = "psci"; 43 next-level-cache = <&l2_0>; 44 capacity-dmips-mhz = <1024>; 45 dynamic-power-coefficient = <100>; 46 47 qcom,freq-domain = <&cpufreq_hw 0>; 48 49 l2_0: l2-cache { 50 compatible = "cache"; 51 cache-level = <2>; 52 cache-unified; 53 next-level-cache = <&l3>; 54 55 l3: l3-cache { 56 compatible = "cache"; 57 cache-level = <3>; 58 cache-unified; 59 }; 60 }; 61 }; 62 63 cpu1: cpu@100 { 64 device_type = "cpu"; 65 compatible = "arm,cortex-a520"; 66 reg = <0x0 0x100>; 67 68 clocks = <&cpufreq_hw 0>; 69 70 power-domains = <&cpu_pd1>; 71 power-domain-names = "psci"; 72 73 enable-method = "psci"; 74 next-level-cache = <&l2_0>; 75 capacity-dmips-mhz = <1024>; 76 dynamic-power-coefficient = <100>; 77 78 qcom,freq-domain = <&cpufreq_hw 0>; 79 }; 80 81 cpu2: cpu@200 { 82 device_type = "cpu"; 83 compatible = "arm,cortex-a520"; 84 reg = <0x0 0x200>; 85 86 clocks = <&cpufreq_hw 0>; 87 88 power-domains = <&cpu_pd2>; 89 power-domain-names = "psci"; 90 91 enable-method = "psci"; 92 next-level-cache = <&l2_2>; 93 capacity-dmips-mhz = <1024>; 94 dynamic-power-coefficient = <100>; 95 96 qcom,freq-domain = <&cpufreq_hw 0>; 97 98 l2_2: l2-cache { 99 compatible = "cache"; 100 cache-level = <2>; 101 cache-unified; 102 next-level-cache = <&l3>; 103 }; 104 }; 105 106 cpu3: cpu@300 { 107 device_type = "cpu"; 108 compatible = "arm,cortex-a720"; 109 reg = <0x0 0x300>; 110 111 clocks = <&cpufreq_hw 1>; 112 113 power-domains = <&cpu_pd3>; 114 power-domain-names = "psci"; 115 116 enable-method = "psci"; 117 next-level-cache = <&l2_3>; 118 capacity-dmips-mhz = <1792>; 119 dynamic-power-coefficient = <238>; 120 121 qcom,freq-domain = <&cpufreq_hw 1>; 122 123 l2_3: l2-cache { 124 compatible = "cache"; 125 cache-level = <2>; 126 cache-unified; 127 next-level-cache = <&l3>; 128 }; 129 }; 130 131 cpu4: cpu@400 { 132 device_type = "cpu"; 133 compatible = "arm,cortex-a720"; 134 reg = <0x0 0x400>; 135 136 clocks = <&cpufreq_hw 1>; 137 138 power-domains = <&cpu_pd4>; 139 power-domain-names = "psci"; 140 141 enable-method = "psci"; 142 next-level-cache = <&l2_4>; 143 capacity-dmips-mhz = <1792>; 144 dynamic-power-coefficient = <238>; 145 146 qcom,freq-domain = <&cpufreq_hw 1>; 147 148 l2_4: l2-cache { 149 compatible = "cache"; 150 cache-level = <2>; 151 cache-unified; 152 next-level-cache = <&l3>; 153 }; 154 }; 155 156 cpu5: cpu@500 { 157 device_type = "cpu"; 158 compatible = "arm,cortex-a720"; 159 reg = <0x0 0x500>; 160 161 clocks = <&cpufreq_hw 1>; 162 163 power-domains = <&cpu_pd5>; 164 power-domain-names = "psci"; 165 166 enable-method = "psci"; 167 next-level-cache = <&l2_5>; 168 capacity-dmips-mhz = <1792>; 169 dynamic-power-coefficient = <238>; 170 171 qcom,freq-domain = <&cpufreq_hw 1>; 172 173 l2_5: l2-cache { 174 compatible = "cache"; 175 cache-level = <2>; 176 cache-unified; 177 next-level-cache = <&l3>; 178 }; 179 }; 180 181 cpu6: cpu@600 { 182 device_type = "cpu"; 183 compatible = "arm,cortex-a720"; 184 reg = <0x0 0x600>; 185 186 clocks = <&cpufreq_hw 1>; 187 188 power-domains = <&cpu_pd6>; 189 power-domain-names = "psci"; 190 191 enable-method = "psci"; 192 next-level-cache = <&l2_6>; 193 capacity-dmips-mhz = <1792>; 194 dynamic-power-coefficient = <238>; 195 196 qcom,freq-domain = <&cpufreq_hw 1>; 197 198 l2_6: l2-cache { 199 compatible = "cache"; 200 cache-level = <2>; 201 cache-unified; 202 next-level-cache = <&l3>; 203 }; 204 }; 205 206 cpu7: cpu@700 { 207 device_type = "cpu"; 208 compatible = "arm,cortex-x3"; 209 reg = <0x0 0x700>; 210 211 clocks = <&cpufreq_hw 2>; 212 213 power-domains = <&cpu_pd7>; 214 power-domain-names = "psci"; 215 216 enable-method = "psci"; 217 next-level-cache = <&l2_7>; 218 capacity-dmips-mhz = <1894>; 219 dynamic-power-coefficient = <588>; 220 221 qcom,freq-domain = <&cpufreq_hw 2>; 222 223 l2_7: l2-cache { 224 compatible = "cache"; 225 cache-level = <2>; 226 cache-unified; 227 next-level-cache = <&l3>; 228 }; 229 }; 230 231 cpu-map { 232 cluster0 { 233 core0 { 234 cpu = <&cpu0>; 235 }; 236 237 core1 { 238 cpu = <&cpu1>; 239 }; 240 241 core2 { 242 cpu = <&cpu2>; 243 }; 244 245 core3 { 246 cpu = <&cpu3>; 247 }; 248 249 core4 { 250 cpu = <&cpu4>; 251 }; 252 253 core5 { 254 cpu = <&cpu5>; 255 }; 256 257 core6 { 258 cpu = <&cpu6>; 259 }; 260 261 core7 { 262 cpu = <&cpu7>; 263 }; 264 }; 265 }; 266 267 idle-states { 268 entry-method = "psci"; 269 270 cluster0_c4: cpu-sleep-0 { 271 compatible = "arm,idle-state"; 272 idle-state-name = "silver-rail-power-collapse"; 273 arm,psci-suspend-param = <0x40000004>; 274 entry-latency-us = <550>; 275 exit-latency-us = <750>; 276 min-residency-us = <6700>; 277 }; 278 279 cluster1_c4: cpu-sleep-1 { 280 compatible = "arm,idle-state"; 281 idle-state-name = "gold-rail-power-collapse"; 282 arm,psci-suspend-param = <0x40000004>; 283 entry-latency-us = <550>; 284 exit-latency-us = <1050>; 285 min-residency-us = <7951>; 286 }; 287 288 cluster2_c4: cpu-sleep-2 { 289 compatible = "arm,idle-state"; 290 idle-state-name = "gold-plus-rail-power-collapse"; 291 arm,psci-suspend-param = <0x40000004>; 292 entry-latency-us = <500>; 293 exit-latency-us = <1350>; 294 min-residency-us = <7480>; 295 }; 296 }; 297 298 domain-idle-states { 299 cluster_sleep_0: cluster-sleep-0 { 300 compatible = "domain-idle-state"; 301 arm,psci-suspend-param = <0x41000044>; 302 entry-latency-us = <750>; 303 exit-latency-us = <2350>; 304 min-residency-us = <9144>; 305 }; 306 307 cluster_sleep_1: cluster-sleep-1 { 308 compatible = "domain-idle-state"; 309 arm,psci-suspend-param = <0x4100b344>; 310 entry-latency-us = <2800>; 311 exit-latency-us = <4400>; 312 min-residency-us = <10150>; 313 }; 314 }; 315 }; 316 317 firmware { 318 scm: scm { 319 compatible = "qcom,scm-eliza", "qcom,scm"; 320 interconnects = <&aggre2_noc MASTER_CRYPTO QCOM_ICC_TAG_ALWAYS 321 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 322 qcom,dload-mode = <&tcsr 0x1a000>; 323 }; 324 }; 325 326 clk_virt: interconnect-0 { 327 compatible = "qcom,eliza-clk-virt"; 328 #interconnect-cells = <2>; 329 qcom,bcm-voters = <&apps_bcm_voter>; 330 }; 331 332 mc_virt: interconnect-1 { 333 compatible = "qcom,eliza-mc-virt"; 334 #interconnect-cells = <2>; 335 qcom,bcm-voters = <&apps_bcm_voter>; 336 }; 337 338 memory@a0000000 { 339 device_type = "memory"; 340 /* We expect the bootloader to fill in the size */ 341 reg = <0x0 0xa0000000 0x0 0x0>; 342 }; 343 344 psci { 345 compatible = "arm,psci-1.0"; 346 method = "smc"; 347 348 cpu_pd0: power-domain-cpu0 { 349 #power-domain-cells = <0>; 350 power-domains = <&cluster_pd>; 351 domain-idle-states = <&cluster0_c4>; 352 }; 353 354 cpu_pd1: power-domain-cpu1 { 355 #power-domain-cells = <0>; 356 power-domains = <&cluster_pd>; 357 domain-idle-states = <&cluster0_c4>; 358 }; 359 360 cpu_pd2: power-domain-cpu2 { 361 #power-domain-cells = <0>; 362 power-domains = <&cluster_pd>; 363 domain-idle-states = <&cluster0_c4>; 364 }; 365 366 cpu_pd3: power-domain-cpu3 { 367 #power-domain-cells = <0>; 368 power-domains = <&cluster_pd>; 369 domain-idle-states = <&cluster1_c4>; 370 }; 371 372 cpu_pd4: power-domain-cpu4 { 373 #power-domain-cells = <0>; 374 power-domains = <&cluster_pd>; 375 domain-idle-states = <&cluster1_c4>; 376 }; 377 378 cpu_pd5: power-domain-cpu5 { 379 #power-domain-cells = <0>; 380 power-domains = <&cluster_pd>; 381 domain-idle-states = <&cluster1_c4>; 382 }; 383 384 cpu_pd6: power-domain-cpu6 { 385 #power-domain-cells = <0>; 386 power-domains = <&cluster_pd>; 387 domain-idle-states = <&cluster1_c4>; 388 }; 389 390 cpu_pd7: power-domain-cpu7 { 391 #power-domain-cells = <0>; 392 power-domains = <&cluster_pd>; 393 domain-idle-states = <&cluster2_c4>; 394 }; 395 396 cluster_pd: power-domain-cluster { 397 #power-domain-cells = <0>; 398 domain-idle-states = <&cluster_sleep_0>, 399 <&cluster_sleep_1>; 400 }; 401 }; 402 403 reserved-memory { 404 #address-cells = <2>; 405 #size-cells = <2>; 406 ranges; 407 408 gunyah_hyp_mem: gunyah-hyp@80000000 { 409 reg = <0x0 0x80000000 0x0 0xe00000>; 410 no-map; 411 }; 412 413 cpusys_vm_mem: cpusys-vm-mem@80e00000 { 414 reg = <0x0 0x80e00000 0x0 0x400000>; 415 no-map; 416 }; 417 418 cpucp_mem: cpucp@81200000 { 419 reg = <0x0 0x81200000 0x0 0x100000>; 420 no-map; 421 }; 422 423 xbl_dtlog_mem: xbl-dtlog@81a00000 { 424 reg = <0x0 0x81a00000 0x0 0x40000>; 425 no-map; 426 }; 427 428 aop_image_mem: aop-image@81c00000 { 429 reg = <0x0 0x81c00000 0x0 0x60000>; 430 no-map; 431 }; 432 433 aop_cmd_db_mem: aop-cmd-db@81c60000 { 434 compatible = "qcom,cmd-db"; 435 reg = <0x0 0x81c60000 0x0 0x20000>; 436 no-map; 437 }; 438 439 /* Merged aop_config, tme_crash_dump, tme_log and uefi_log regions */ 440 aop_tme_uefi_merged_mem: aop-tme-uefi-merged@81c80000 { 441 reg = <0x0 0x81c80000 0x0 0x74000>; 442 no-map; 443 }; 444 445 /* Secdata region can be reused by apps */ 446 smem_mem: smem@81d00000 { 447 compatible = "qcom,smem"; 448 reg = <0x0 0x81d00000 0x0 0x200000>; 449 hwlocks = <&tcsr_mutex 3>; 450 no-map; 451 }; 452 453 cpucp_scandump_mem: cpucp-scandump@82200000 { 454 reg = <0x0 0x82200000 0x0 0x180000>; 455 no-map; 456 }; 457 458 adsp_mhi_mem: adsp-mhi@82380000 { 459 reg = <0x0 0x82380000 0x0 0x20000>; 460 no-map; 461 }; 462 463 soccp_sdi_mem: soccp-sdi@823a0000 { 464 reg = <0x0 0x823a0000 0x0 0x40000>; 465 no-map; 466 }; 467 468 pmic_minii_dump_mem: pmic-minii-dump@823e0000 { 469 reg = <0x0 0x823e0000 0x0 0x80000>; 470 no-map; 471 }; 472 473 pvmfw_mem: pvmfw@824a0000 { 474 reg = <0x0 0x824a0000 0x0 0x100000>; 475 no-map; 476 }; 477 478 hyp_db_mem: hyp-db@825a0000 { 479 reg = <0x0 0x825a0000 0x0 0x60000>; 480 no-map; 481 }; 482 483 global_sync_mem: global-sync@82600000 { 484 reg = <0x0 0x82600000 0x0 0x100000>; 485 no-map; 486 }; 487 488 tz_stat_mem: tz-stat@82700000 { 489 reg = <0x0 0x82700000 0x0 0x100000>; 490 no-map; 491 }; 492 493 qdss_mem: qdss@82800000 { 494 reg = <0x0 0x82800000 0x0 0x2000000>; 495 no-map; 496 }; 497 498 dsm_partition_1_mem: dsm-partition-1@84a00000 { 499 reg = <0x0 0x84a00000 0x0 0x3700000>; 500 no-map; 501 }; 502 503 mpss_mem: mpss@88100000 { 504 reg = <0x0 0x88100000 0x0 0xcd00000>; 505 no-map; 506 }; 507 508 q6_mpss_dtb_mem: q6-mpss-dtb@94e00000 { 509 reg = <0x0 0x94e00000 0x0 0x80000>; 510 no-map; 511 }; 512 513 ipa_fw_mem: ipa-fw@94e80000 { 514 reg = <0x0 0x94e80000 0x0 0x10000>; 515 no-map; 516 }; 517 518 ipa_gsi_mem: ipa-gsi@94e90000 { 519 reg = <0x0 0x94e90000 0x0 0xa000>; 520 no-map; 521 }; 522 523 gpu_micro_code_mem: gpu-micro-code@94e9a000 { 524 reg = <0x0 0x94e9a000 0x0 0x2000>; 525 no-map; 526 }; 527 528 camera_mem: camera@94f00000 { 529 reg = <0x0 0x94f00000 0x0 0x800000>; 530 no-map; 531 }; 532 533 camera_2_mem: camera-2@95700000 { 534 reg = <0x0 0x95700000 0x0 0x800000>; 535 no-map; 536 }; 537 538 video_mem: video@95f00000 { 539 reg = <0x0 0x95f00000 0x0 0x800000>; 540 no-map; 541 }; 542 543 soccp_mem: soccp@96700000 { 544 reg = <0x0 0x96700000 0x0 0x180000>; 545 no-map; 546 }; 547 548 wpss_mem: wpss@97000000 { 549 reg = <0x0 0x97000000 0x0 0x1900000>; 550 no-map; 551 }; 552 553 cdsp_mem: cdsp@98900000 { 554 reg = <0x0 0x98900000 0x0 0x1400000>; 555 no-map; 556 }; 557 558 q6_cdsp_dtb_mem: q6-cdsp-dtb@99d00000 { 559 reg = <0x0 0x99d00000 0x0 0x80000>; 560 no-map; 561 }; 562 563 q6_adsp_dtb_mem: q6-adsp-dtb@99d80000 { 564 reg = <0x0 0x99d80000 0x0 0x80000>; 565 no-map; 566 }; 567 568 adspslpi_mem: adspslpi@99e00000 { 569 reg = <0x0 0x99e00000 0x0 0x2a00000>; 570 no-map; 571 }; 572 573 wlan_msa_mem: wlan-msa@a6400000 { 574 reg = <0x0 0xa6400000 0x0 0xc00000>; 575 no-map; 576 }; 577 578 xbl_ramdump_mem: xbl-ramdump@b8000000 { 579 reg = <0x0 0xb8000000 0x0 0x1c0000>; 580 no-map; 581 }; 582 583 /* Merged tz_reserved, xbl_sc, and qtee regions */ 584 tz_merged_mem: tz-merged@d8000000 { 585 reg = <0x0 0xd8000000 0x0 0x600000>; 586 no-map; 587 }; 588 589 trust_ui_vm_mem: trust-ui-vm@f3800000 { 590 reg = <0x0 0xf3800000 0x0 0x4400000>; 591 no-map; 592 }; 593 594 oem_vm_mem: oem-vm@f7c00000 { 595 reg = <0x0 0xf7c00000 0x0 0x4c00000>; 596 no-map; 597 }; 598 599 llcc_lpi_mem: llcc-lpi@ff800000 { 600 reg = <0x0 0xff800000 0x0 0x180000>; 601 no-map; 602 }; 603 }; 604 605 smp2p-adsp { 606 compatible = "qcom,smp2p"; 607 qcom,smem = <443>, <429>; 608 interrupts-extended = <&ipcc IPCC_CLIENT_LPASS 609 IPCC_MPROC_SIGNAL_SMP2P 610 IRQ_TYPE_EDGE_RISING>; 611 mboxes = <&ipcc IPCC_CLIENT_LPASS 612 IPCC_MPROC_SIGNAL_SMP2P>; 613 614 qcom,local-pid = <0>; 615 qcom,remote-pid = <2>; 616 617 smp2p_adsp_out: master-kernel { 618 qcom,entry-name = "master-kernel"; 619 #qcom,smem-state-cells = <1>; 620 }; 621 622 smp2p_adsp_in: slave-kernel { 623 qcom,entry-name = "slave-kernel"; 624 interrupt-controller; 625 #interrupt-cells = <2>; 626 }; 627 }; 628 629 soc: soc@0 { 630 compatible = "simple-bus"; 631 632 #address-cells = <2>; 633 #size-cells = <2>; 634 dma-ranges = <0x0 0x0 0x0 0x0 0x10 0x0>; 635 ranges = <0x0 0x0 0x0 0x0 0x10 0x0>; 636 637 gcc: clock-controller@100000 { 638 compatible = "qcom,eliza-gcc"; 639 reg = <0x0 0x00100000 0x0 0x1f4200>; 640 641 clocks = <&bi_tcxo_div2>, 642 <&sleep_clk>, 643 <0>, 644 <0>, 645 <&ufs_mem_phy 0>, 646 <&ufs_mem_phy 1>, 647 <&ufs_mem_phy 2>, 648 <0>; 649 650 power-domains = <&rpmhpd RPMHPD_CX>; 651 652 #clock-cells = <1>; 653 #reset-cells = <1>; 654 #power-domain-cells = <1>; 655 }; 656 657 ipcc: mailbox@406000 { 658 compatible = "qcom,eliza-ipcc", "qcom,ipcc"; 659 reg = <0x0 0x00406000 0x0 0x1000>; 660 661 interrupts = <GIC_SPI 229 IRQ_TYPE_LEVEL_HIGH>; 662 interrupt-controller; 663 #interrupt-cells = <3>; 664 665 #mbox-cells = <2>; 666 }; 667 668 gpi_dma2: dma-controller@800000 { 669 compatible = "qcom,eliza-gpi-dma", "qcom,sm6350-gpi-dma"; 670 reg = <0x0 0x00800000 0x0 0x60000>; 671 672 interrupts = <GIC_SPI 588 IRQ_TYPE_LEVEL_HIGH>, 673 <GIC_SPI 589 IRQ_TYPE_LEVEL_HIGH>, 674 <GIC_SPI 590 IRQ_TYPE_LEVEL_HIGH>, 675 <GIC_SPI 591 IRQ_TYPE_LEVEL_HIGH>, 676 <GIC_SPI 592 IRQ_TYPE_LEVEL_HIGH>, 677 <GIC_SPI 593 IRQ_TYPE_LEVEL_HIGH>, 678 <GIC_SPI 594 IRQ_TYPE_LEVEL_HIGH>, 679 <GIC_SPI 595 IRQ_TYPE_LEVEL_HIGH>, 680 <GIC_SPI 596 IRQ_TYPE_LEVEL_HIGH>, 681 <GIC_SPI 597 IRQ_TYPE_LEVEL_HIGH>, 682 <GIC_SPI 598 IRQ_TYPE_LEVEL_HIGH>, 683 <GIC_SPI 599 IRQ_TYPE_LEVEL_HIGH>; 684 685 dma-channels = <12>; 686 dma-channel-mask = <0x3f>; 687 #dma-cells = <3>; 688 689 iommus = <&apps_smmu 0x436 0>; 690 691 dma-coherent; 692 }; 693 694 qupv3_2: geniqup@8c0000 { 695 compatible = "qcom,geni-se-qup"; 696 reg = <0x0 0x008c0000 0x0 0x2000>; 697 698 clocks = <&gcc GCC_QUPV3_WRAP_2_M_AHB_CLK>, 699 <&gcc GCC_QUPV3_WRAP_2_S_AHB_CLK>; 700 clock-names = "m-ahb", 701 "s-ahb"; 702 703 iommus = <&apps_smmu 0x423 0x0>; 704 705 #address-cells = <2>; 706 #size-cells = <2>; 707 ranges; 708 709 i2c8: i2c@880000 { 710 compatible = "qcom,geni-i2c"; 711 reg = <0x0 0x00880000 0x0 0x4000>; 712 713 interrupts = <GIC_SPI 373 IRQ_TYPE_LEVEL_HIGH>; 714 715 clocks = <&gcc GCC_QUPV3_WRAP2_S0_CLK>; 716 clock-names = "se"; 717 718 interconnects = <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS 719 &clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>, 720 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY 721 &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ACTIVE_ONLY>, 722 <&aggre2_noc MASTER_QUP_2 QCOM_ICC_TAG_ALWAYS 723 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 724 interconnect-names = "qup-core", 725 "qup-config", 726 "qup-memory"; 727 728 dmas = <&gpi_dma2 0 0 QCOM_GPI_I2C>, 729 <&gpi_dma2 1 0 QCOM_GPI_I2C>; 730 dma-names = "tx", 731 "rx"; 732 733 pinctrl-0 = <&qup_i2c8_data_clk>; 734 pinctrl-names = "default"; 735 736 #address-cells = <1>; 737 #size-cells = <0>; 738 739 status = "disabled"; 740 }; 741 742 spi8: spi@880000 { 743 compatible = "qcom,geni-spi"; 744 reg = <0x0 0x00880000 0x0 0x4000>; 745 746 interrupts = <GIC_SPI 373 IRQ_TYPE_LEVEL_HIGH>; 747 748 clocks = <&gcc GCC_QUPV3_WRAP2_S0_CLK>; 749 clock-names = "se"; 750 751 interconnects = <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS 752 &clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>, 753 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY 754 &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ACTIVE_ONLY>, 755 <&aggre2_noc MASTER_QUP_2 QCOM_ICC_TAG_ALWAYS 756 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 757 interconnect-names = "qup-core", 758 "qup-config", 759 "qup-memory"; 760 761 dmas = <&gpi_dma2 0 0 QCOM_GPI_SPI>, 762 <&gpi_dma2 1 0 QCOM_GPI_SPI>; 763 dma-names = "tx", 764 "rx"; 765 766 pinctrl-0 = <&qup_spi8_data_clk>, <&qup_spi8_cs>; 767 pinctrl-names = "default"; 768 769 #address-cells = <1>; 770 #size-cells = <0>; 771 772 status = "disabled"; 773 }; 774 775 i2c9: i2c@884000 { 776 compatible = "qcom,geni-i2c"; 777 reg = <0x0 0x00884000 0x0 0x4000>; 778 779 interrupts = <GIC_SPI 583 IRQ_TYPE_LEVEL_HIGH>; 780 781 clocks = <&gcc GCC_QUPV3_WRAP2_S1_CLK>; 782 clock-names = "se"; 783 784 interconnects = <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS 785 &clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>, 786 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY 787 &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ACTIVE_ONLY>, 788 <&aggre2_noc MASTER_QUP_2 QCOM_ICC_TAG_ALWAYS 789 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 790 interconnect-names = "qup-core", 791 "qup-config", 792 "qup-memory"; 793 794 dmas = <&gpi_dma2 0 1 QCOM_GPI_I2C>, 795 <&gpi_dma2 1 1 QCOM_GPI_I2C>; 796 dma-names = "tx", 797 "rx"; 798 799 pinctrl-0 = <&qup_i2c9_data_clk>; 800 pinctrl-names = "default"; 801 802 #address-cells = <1>; 803 #size-cells = <0>; 804 805 status = "disabled"; 806 }; 807 808 spi9: spi@884000 { 809 compatible = "qcom,geni-spi"; 810 reg = <0x0 0x00884000 0x0 0x4000>; 811 812 interrupts = <GIC_SPI 583 IRQ_TYPE_LEVEL_HIGH>; 813 814 clocks = <&gcc GCC_QUPV3_WRAP2_S1_CLK>; 815 clock-names = "se"; 816 817 interconnects = <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS 818 &clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>, 819 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY 820 &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ACTIVE_ONLY>, 821 <&aggre2_noc MASTER_QUP_2 QCOM_ICC_TAG_ALWAYS 822 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 823 interconnect-names = "qup-core", 824 "qup-config", 825 "qup-memory"; 826 827 dmas = <&gpi_dma2 0 1 QCOM_GPI_SPI>, 828 <&gpi_dma2 1 1 QCOM_GPI_SPI>; 829 dma-names = "tx", 830 "rx"; 831 832 pinctrl-0 = <&qup_spi9_data_clk>, <&qup_spi9_cs>; 833 pinctrl-names = "default"; 834 835 #address-cells = <1>; 836 #size-cells = <0>; 837 838 status = "disabled"; 839 }; 840 841 i2c10: i2c@888000 { 842 compatible = "qcom,geni-i2c"; 843 reg = <0x0 0x00888000 0x0 0x4000>; 844 845 interrupts = <GIC_SPI 584 IRQ_TYPE_LEVEL_HIGH>; 846 847 clocks = <&gcc GCC_QUPV3_WRAP2_S2_CLK>; 848 clock-names = "se"; 849 850 interconnects = <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS 851 &clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>, 852 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY 853 &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ACTIVE_ONLY>, 854 <&aggre2_noc MASTER_QUP_2 QCOM_ICC_TAG_ALWAYS 855 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 856 interconnect-names = "qup-core", 857 "qup-config", 858 "qup-memory"; 859 860 dmas = <&gpi_dma2 0 2 QCOM_GPI_I2C>, 861 <&gpi_dma2 1 2 QCOM_GPI_I2C>; 862 dma-names = "tx", 863 "rx"; 864 865 pinctrl-0 = <&qup_i2c10_data_clk>; 866 pinctrl-names = "default"; 867 868 #address-cells = <1>; 869 #size-cells = <0>; 870 871 status = "disabled"; 872 }; 873 874 spi10: spi@888000 { 875 compatible = "qcom,geni-spi"; 876 reg = <0x0 0x00888000 0x0 0x4000>; 877 878 interrupts = <GIC_SPI 584 IRQ_TYPE_LEVEL_HIGH>; 879 880 clocks = <&gcc GCC_QUPV3_WRAP2_S2_CLK>; 881 clock-names = "se"; 882 883 interconnects = <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS 884 &clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>, 885 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY 886 &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ACTIVE_ONLY>, 887 <&aggre2_noc MASTER_QUP_2 QCOM_ICC_TAG_ALWAYS 888 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 889 interconnect-names = "qup-core", 890 "qup-config", 891 "qup-memory"; 892 893 dmas = <&gpi_dma2 0 2 QCOM_GPI_SPI>, 894 <&gpi_dma2 1 2 QCOM_GPI_SPI>; 895 dma-names = "tx", 896 "rx"; 897 898 pinctrl-0 = <&qup_spi10_data_clk>, <&qup_spi10_cs>; 899 pinctrl-names = "default"; 900 901 #address-cells = <1>; 902 #size-cells = <0>; 903 904 status = "disabled"; 905 }; 906 907 i2c11: i2c@88c000 { 908 compatible = "qcom,geni-i2c"; 909 reg = <0x0 0x0088c000 0x0 0x4000>; 910 911 interrupts = <GIC_SPI 585 IRQ_TYPE_LEVEL_HIGH>; 912 913 clocks = <&gcc GCC_QUPV3_WRAP2_S3_CLK>; 914 clock-names = "se"; 915 916 interconnects = <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS 917 &clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>, 918 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY 919 &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ACTIVE_ONLY>, 920 <&aggre2_noc MASTER_QUP_2 QCOM_ICC_TAG_ALWAYS 921 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 922 interconnect-names = "qup-core", 923 "qup-config", 924 "qup-memory"; 925 926 dmas = <&gpi_dma2 0 3 QCOM_GPI_I2C>, 927 <&gpi_dma2 1 3 QCOM_GPI_I2C>; 928 dma-names = "tx", 929 "rx"; 930 931 pinctrl-0 = <&qup_i2c11_data_clk>; 932 pinctrl-names = "default"; 933 934 #address-cells = <1>; 935 #size-cells = <0>; 936 937 status = "disabled"; 938 }; 939 940 spi11: spi@88c000 { 941 compatible = "qcom,geni-spi"; 942 reg = <0x0 0x0088c000 0x0 0x4000>; 943 944 interrupts = <GIC_SPI 585 IRQ_TYPE_LEVEL_HIGH>; 945 946 clocks = <&gcc GCC_QUPV3_WRAP2_S3_CLK>; 947 clock-names = "se"; 948 949 interconnects = <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS 950 &clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>, 951 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY 952 &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ACTIVE_ONLY>, 953 <&aggre2_noc MASTER_QUP_2 QCOM_ICC_TAG_ALWAYS 954 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 955 interconnect-names = "qup-core", 956 "qup-config", 957 "qup-memory"; 958 959 dmas = <&gpi_dma2 0 3 QCOM_GPI_SPI>, 960 <&gpi_dma2 1 3 QCOM_GPI_SPI>; 961 dma-names = "tx", 962 "rx"; 963 964 pinctrl-0 = <&qup_spi11_data_clk>, <&qup_spi11_cs>; 965 pinctrl-names = "default"; 966 967 #address-cells = <1>; 968 #size-cells = <0>; 969 970 status = "disabled"; 971 }; 972 973 i2c12: i2c@890000 { 974 compatible = "qcom,geni-i2c"; 975 reg = <0x0 0x00890000 0x0 0x4000>; 976 977 interrupts = <GIC_SPI 586 IRQ_TYPE_LEVEL_HIGH>; 978 979 clocks = <&gcc GCC_QUPV3_WRAP2_S4_CLK>; 980 clock-names = "se"; 981 982 interconnects = <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS 983 &clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>, 984 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY 985 &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ACTIVE_ONLY>, 986 <&aggre2_noc MASTER_QUP_2 QCOM_ICC_TAG_ALWAYS 987 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 988 interconnect-names = "qup-core", 989 "qup-config", 990 "qup-memory"; 991 992 dmas = <&gpi_dma2 0 4 QCOM_GPI_I2C>, 993 <&gpi_dma2 1 4 QCOM_GPI_I2C>; 994 dma-names = "tx", 995 "rx"; 996 997 pinctrl-0 = <&qup_i2c12_data_clk>; 998 pinctrl-names = "default"; 999 1000 #address-cells = <1>; 1001 #size-cells = <0>; 1002 1003 status = "disabled"; 1004 }; 1005 1006 spi12: spi@890000 { 1007 compatible = "qcom,geni-spi"; 1008 reg = <0x0 0x00890000 0x0 0x4000>; 1009 1010 interrupts = <GIC_SPI 586 IRQ_TYPE_LEVEL_HIGH>; 1011 1012 clocks = <&gcc GCC_QUPV3_WRAP2_S4_CLK>; 1013 clock-names = "se"; 1014 1015 interconnects = <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS 1016 &clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>, 1017 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY 1018 &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ACTIVE_ONLY>, 1019 <&aggre2_noc MASTER_QUP_2 QCOM_ICC_TAG_ALWAYS 1020 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 1021 interconnect-names = "qup-core", 1022 "qup-config", 1023 "qup-memory"; 1024 1025 dmas = <&gpi_dma2 0 4 QCOM_GPI_SPI>, 1026 <&gpi_dma2 1 4 QCOM_GPI_SPI>; 1027 dma-names = "tx", 1028 "rx"; 1029 1030 pinctrl-0 = <&qup_spi12_data_clk>, <&qup_spi12_cs>; 1031 pinctrl-names = "default"; 1032 1033 #address-cells = <1>; 1034 #size-cells = <0>; 1035 1036 status = "disabled"; 1037 }; 1038 1039 uart13: serial@894000 { 1040 compatible = "qcom,geni-uart"; 1041 reg = <0x0 0x00894000 0x0 0x4000>; 1042 1043 interrupts = <GIC_SPI 587 IRQ_TYPE_LEVEL_HIGH>; 1044 1045 clocks = <&gcc GCC_QUPV3_WRAP2_S5_CLK>; 1046 clock-names = "se"; 1047 1048 interconnects = <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS 1049 &clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>, 1050 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 1051 &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ALWAYS>; 1052 interconnect-names = "qup-core", 1053 "qup-config"; 1054 1055 pinctrl-0 = <&qup_uart13_default>; 1056 pinctrl-names = "default"; 1057 1058 status = "disabled"; 1059 }; 1060 1061 i2c14: i2c@898000 { 1062 compatible = "qcom,geni-i2c"; 1063 reg = <0x0 0x00898000 0x0 0x4000>; 1064 1065 interrupts = <GIC_SPI 461 IRQ_TYPE_LEVEL_HIGH>; 1066 1067 clocks = <&gcc GCC_QUPV3_WRAP2_S6_CLK>; 1068 clock-names = "se"; 1069 1070 interconnects = <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS 1071 &clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>, 1072 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY 1073 &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ACTIVE_ONLY>, 1074 <&aggre2_noc MASTER_QUP_2 QCOM_ICC_TAG_ALWAYS 1075 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 1076 interconnect-names = "qup-core", 1077 "qup-config", 1078 "qup-memory"; 1079 1080 dmas = <&gpi_dma2 0 6 QCOM_GPI_I2C>, 1081 <&gpi_dma2 1 6 QCOM_GPI_I2C>; 1082 dma-names = "tx", 1083 "rx"; 1084 1085 pinctrl-0 = <&qup_i2c14_data_clk>; 1086 pinctrl-names = "default"; 1087 1088 #address-cells = <1>; 1089 #size-cells = <0>; 1090 1091 status = "disabled"; 1092 }; 1093 1094 spi14: spi@898000 { 1095 compatible = "qcom,geni-spi"; 1096 reg = <0x0 0x00898000 0x0 0x4000>; 1097 1098 interrupts = <GIC_SPI 461 IRQ_TYPE_LEVEL_HIGH>; 1099 1100 clocks = <&gcc GCC_QUPV3_WRAP2_S6_CLK>; 1101 clock-names = "se"; 1102 1103 interconnects = <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS 1104 &clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>, 1105 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY 1106 &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ACTIVE_ONLY>, 1107 <&aggre2_noc MASTER_QUP_2 QCOM_ICC_TAG_ALWAYS 1108 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 1109 interconnect-names = "qup-core", 1110 "qup-config", 1111 "qup-memory"; 1112 1113 dmas = <&gpi_dma2 0 6 QCOM_GPI_SPI>, 1114 <&gpi_dma2 1 6 QCOM_GPI_SPI>; 1115 dma-names = "tx", 1116 "rx"; 1117 1118 pinctrl-0 = <&qup_spi14_data_clk>, <&qup_spi14_cs>; 1119 pinctrl-names = "default"; 1120 1121 #address-cells = <1>; 1122 #size-cells = <0>; 1123 1124 status = "disabled"; 1125 }; 1126 1127 i2c15: i2c@89c000 { 1128 compatible = "qcom,geni-i2c"; 1129 reg = <0x0 0x0089c000 0x0 0x4000>; 1130 1131 interrupts = <GIC_SPI 462 IRQ_TYPE_LEVEL_HIGH>; 1132 1133 clocks = <&gcc GCC_QUPV3_WRAP2_S7_CLK>; 1134 clock-names = "se"; 1135 1136 interconnects = <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS 1137 &clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>, 1138 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY 1139 &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ACTIVE_ONLY>, 1140 <&aggre2_noc MASTER_QUP_2 QCOM_ICC_TAG_ALWAYS 1141 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 1142 interconnect-names = "qup-core", 1143 "qup-config", 1144 "qup-memory"; 1145 1146 dmas = <&gpi_dma2 0 7 QCOM_GPI_I2C>, 1147 <&gpi_dma2 1 7 QCOM_GPI_I2C>; 1148 dma-names = "tx", 1149 "rx"; 1150 1151 pinctrl-0 = <&qup_i2c15_data_clk>; 1152 pinctrl-names = "default"; 1153 1154 #address-cells = <1>; 1155 #size-cells = <0>; 1156 1157 status = "disabled"; 1158 }; 1159 1160 spi15: spi@89c000 { 1161 compatible = "qcom,geni-spi"; 1162 reg = <0x0 0x0089c000 0x0 0x4000>; 1163 1164 interrupts = <GIC_SPI 462 IRQ_TYPE_LEVEL_HIGH>; 1165 1166 clocks = <&gcc GCC_QUPV3_WRAP2_S7_CLK>; 1167 clock-names = "se"; 1168 1169 interconnects = <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS 1170 &clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>, 1171 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY 1172 &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ACTIVE_ONLY>, 1173 <&aggre2_noc MASTER_QUP_2 QCOM_ICC_TAG_ALWAYS 1174 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 1175 interconnect-names = "qup-core", 1176 "qup-config", 1177 "qup-memory"; 1178 1179 dmas = <&gpi_dma2 0 7 QCOM_GPI_SPI>, 1180 <&gpi_dma2 1 7 QCOM_GPI_SPI>; 1181 dma-names = "tx", 1182 "rx"; 1183 1184 pinctrl-0 = <&qup_spi15_data_clk>, <&qup_spi15_cs>; 1185 pinctrl-names = "default"; 1186 1187 #address-cells = <1>; 1188 #size-cells = <0>; 1189 1190 status = "disabled"; 1191 }; 1192 }; 1193 1194 gpi_dma1: dma-controller@a00000 { 1195 compatible = "qcom,eliza-gpi-dma", "qcom,sm6350-gpi-dma"; 1196 reg = <0x0 0x00a00000 0x0 0x60000>; 1197 1198 interrupts = <GIC_SPI 279 IRQ_TYPE_LEVEL_HIGH>, 1199 <GIC_SPI 280 IRQ_TYPE_LEVEL_HIGH>, 1200 <GIC_SPI 281 IRQ_TYPE_LEVEL_HIGH>, 1201 <GIC_SPI 282 IRQ_TYPE_LEVEL_HIGH>, 1202 <GIC_SPI 283 IRQ_TYPE_LEVEL_HIGH>, 1203 <GIC_SPI 284 IRQ_TYPE_LEVEL_HIGH>, 1204 <GIC_SPI 293 IRQ_TYPE_LEVEL_HIGH>, 1205 <GIC_SPI 294 IRQ_TYPE_LEVEL_HIGH>, 1206 <GIC_SPI 295 IRQ_TYPE_LEVEL_HIGH>, 1207 <GIC_SPI 296 IRQ_TYPE_LEVEL_HIGH>, 1208 <GIC_SPI 297 IRQ_TYPE_LEVEL_HIGH>, 1209 <GIC_SPI 298 IRQ_TYPE_LEVEL_HIGH>; 1210 1211 dma-channels = <12>; 1212 dma-channel-mask = <0x3f>; 1213 #dma-cells = <3>; 1214 1215 iommus = <&apps_smmu 0xb6 0x0>; 1216 1217 dma-coherent; 1218 }; 1219 1220 qupv3_1: geniqup@ac0000 { 1221 compatible = "qcom,geni-se-qup"; 1222 reg = <0x0 0x00ac0000 0x0 0x2000>; 1223 1224 clocks = <&gcc GCC_QUPV3_WRAP_1_M_AHB_CLK>, 1225 <&gcc GCC_QUPV3_WRAP_1_S_AHB_CLK>; 1226 clock-names = "m-ahb", 1227 "s-ahb"; 1228 1229 iommus = <&apps_smmu 0xa3 0x0>; 1230 1231 #address-cells = <2>; 1232 #size-cells = <2>; 1233 ranges; 1234 1235 status = "disabled"; 1236 1237 i2c0: i2c@a80000 { 1238 compatible = "qcom,geni-i2c"; 1239 reg = <0x0 0x00a80000 0x0 0x4000>; 1240 1241 interrupts = <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>; 1242 1243 clocks = <&gcc GCC_QUPV3_WRAP1_S0_CLK>; 1244 clock-names = "se"; 1245 1246 interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS 1247 &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>, 1248 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY 1249 &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ACTIVE_ONLY>, 1250 <&aggre1_noc MASTER_QUP_1 QCOM_ICC_TAG_ALWAYS 1251 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 1252 interconnect-names = "qup-core", 1253 "qup-config", 1254 "qup-memory"; 1255 1256 dmas = <&gpi_dma1 0 0 QCOM_GPI_I2C>, 1257 <&gpi_dma1 1 0 QCOM_GPI_I2C>; 1258 dma-names = "tx", 1259 "rx"; 1260 1261 pinctrl-0 = <&qup_i2c0_data_clk>; 1262 pinctrl-names = "default"; 1263 1264 #address-cells = <1>; 1265 #size-cells = <0>; 1266 1267 status = "disabled"; 1268 }; 1269 1270 spi0: spi@a80000 { 1271 compatible = "qcom,geni-spi"; 1272 reg = <0x0 0x00a80000 0x0 0x4000>; 1273 1274 interrupts = <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>; 1275 1276 clocks = <&gcc GCC_QUPV3_WRAP1_S0_CLK>; 1277 clock-names = "se"; 1278 1279 interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS 1280 &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>, 1281 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY 1282 &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ACTIVE_ONLY>, 1283 <&aggre1_noc MASTER_QUP_1 QCOM_ICC_TAG_ALWAYS 1284 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 1285 interconnect-names = "qup-core", 1286 "qup-config", 1287 "qup-memory"; 1288 1289 dmas = <&gpi_dma1 0 0 QCOM_GPI_SPI>, 1290 <&gpi_dma1 1 0 QCOM_GPI_SPI>; 1291 dma-names = "tx", 1292 "rx"; 1293 1294 pinctrl-0 = <&qup_spi0_data_clk>, <&qup_spi0_cs>; 1295 pinctrl-names = "default"; 1296 1297 #address-cells = <1>; 1298 #size-cells = <0>; 1299 1300 status = "disabled"; 1301 }; 1302 1303 i2c1: i2c@a84000 { 1304 compatible = "qcom,geni-i2c"; 1305 reg = <0x0 0x00a84000 0x0 0x4000>; 1306 1307 interrupts = <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>; 1308 1309 clocks = <&gcc GCC_QUPV3_WRAP1_S1_CLK>; 1310 clock-names = "se"; 1311 1312 interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS 1313 &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>, 1314 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY 1315 &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ACTIVE_ONLY>, 1316 <&aggre1_noc MASTER_QUP_1 QCOM_ICC_TAG_ALWAYS 1317 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 1318 interconnect-names = "qup-core", 1319 "qup-config", 1320 "qup-memory"; 1321 1322 dmas = <&gpi_dma1 0 1 QCOM_GPI_I2C>, 1323 <&gpi_dma1 1 1 QCOM_GPI_I2C>; 1324 dma-names = "tx", 1325 "rx"; 1326 1327 pinctrl-0 = <&qup_i2c1_data_clk>; 1328 pinctrl-names = "default"; 1329 1330 #address-cells = <1>; 1331 #size-cells = <0>; 1332 1333 status = "disabled"; 1334 }; 1335 1336 spi1: spi@a84000 { 1337 compatible = "qcom,geni-spi"; 1338 reg = <0x0 0x00a84000 0x0 0x4000>; 1339 1340 interrupts = <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>; 1341 1342 clocks = <&gcc GCC_QUPV3_WRAP1_S1_CLK>; 1343 clock-names = "se"; 1344 1345 interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS 1346 &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>, 1347 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY 1348 &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ACTIVE_ONLY>, 1349 <&aggre1_noc MASTER_QUP_1 QCOM_ICC_TAG_ALWAYS 1350 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 1351 interconnect-names = "qup-core", 1352 "qup-config", 1353 "qup-memory"; 1354 1355 dmas = <&gpi_dma1 0 1 QCOM_GPI_SPI>, 1356 <&gpi_dma1 1 1 QCOM_GPI_SPI>; 1357 dma-names = "tx", 1358 "rx"; 1359 1360 pinctrl-0 = <&qup_spi1_data_clk>, <&qup_spi1_cs>; 1361 pinctrl-names = "default"; 1362 1363 #address-cells = <1>; 1364 #size-cells = <0>; 1365 1366 status = "disabled"; 1367 }; 1368 1369 i2c2: i2c@a88000 { 1370 compatible = "qcom,geni-i2c"; 1371 reg = <0x0 0x00a88000 0x0 0x4000>; 1372 1373 interrupts = <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>; 1374 1375 clocks = <&gcc GCC_QUPV3_WRAP1_S2_CLK>; 1376 clock-names = "se"; 1377 1378 interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS 1379 &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>, 1380 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY 1381 &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ACTIVE_ONLY>, 1382 <&aggre1_noc MASTER_QUP_1 QCOM_ICC_TAG_ALWAYS 1383 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 1384 interconnect-names = "qup-core", 1385 "qup-config", 1386 "qup-memory"; 1387 1388 dmas = <&gpi_dma1 0 2 QCOM_GPI_I2C>, 1389 <&gpi_dma1 1 2 QCOM_GPI_I2C>; 1390 dma-names = "tx", 1391 "rx"; 1392 1393 pinctrl-0 = <&qup_i2c2_data_clk>; 1394 pinctrl-names = "default"; 1395 1396 #address-cells = <1>; 1397 #size-cells = <0>; 1398 1399 status = "disabled"; 1400 }; 1401 1402 spi2: spi@a88000 { 1403 compatible = "qcom,geni-spi"; 1404 reg = <0x0 0x00a88000 0x0 0x4000>; 1405 1406 interrupts = <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>; 1407 1408 clocks = <&gcc GCC_QUPV3_WRAP1_S2_CLK>; 1409 clock-names = "se"; 1410 1411 interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS 1412 &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>, 1413 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY 1414 &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ACTIVE_ONLY>, 1415 <&aggre1_noc MASTER_QUP_1 QCOM_ICC_TAG_ALWAYS 1416 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 1417 interconnect-names = "qup-core", 1418 "qup-config", 1419 "qup-memory"; 1420 1421 dmas = <&gpi_dma1 0 2 QCOM_GPI_SPI>, 1422 <&gpi_dma1 1 2 QCOM_GPI_SPI>; 1423 dma-names = "tx", 1424 "rx"; 1425 1426 pinctrl-0 = <&qup_spi2_data_clk>, <&qup_spi2_cs>; 1427 pinctrl-names = "default"; 1428 1429 #address-cells = <1>; 1430 #size-cells = <0>; 1431 1432 status = "disabled"; 1433 }; 1434 1435 i2c3: i2c@a8c000 { 1436 compatible = "qcom,geni-i2c"; 1437 reg = <0x0 0x00a8c000 0x0 0x4000>; 1438 1439 interrupts = <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>; 1440 1441 clocks = <&gcc GCC_QUPV3_WRAP1_S3_CLK>; 1442 clock-names = "se"; 1443 1444 interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS 1445 &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>, 1446 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY 1447 &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ACTIVE_ONLY>, 1448 <&aggre1_noc MASTER_QUP_1 QCOM_ICC_TAG_ALWAYS 1449 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 1450 interconnect-names = "qup-core", 1451 "qup-config", 1452 "qup-memory"; 1453 1454 dmas = <&gpi_dma1 0 3 QCOM_GPI_I2C>, 1455 <&gpi_dma1 1 3 QCOM_GPI_I2C>; 1456 dma-names = "tx", 1457 "rx"; 1458 1459 pinctrl-0 = <&qup_i2c3_data_clk>; 1460 pinctrl-names = "default"; 1461 1462 #address-cells = <1>; 1463 #size-cells = <0>; 1464 1465 status = "disabled"; 1466 }; 1467 1468 spi3: spi@a8c000 { 1469 compatible = "qcom,geni-spi"; 1470 reg = <0x0 0x00a8c000 0x0 0x4000>; 1471 1472 interrupts = <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>; 1473 1474 clocks = <&gcc GCC_QUPV3_WRAP1_S3_CLK>; 1475 clock-names = "se"; 1476 1477 interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS 1478 &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>, 1479 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY 1480 &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ACTIVE_ONLY>, 1481 <&aggre1_noc MASTER_QUP_1 QCOM_ICC_TAG_ALWAYS 1482 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 1483 interconnect-names = "qup-core", 1484 "qup-config", 1485 "qup-memory"; 1486 1487 dmas = <&gpi_dma1 0 3 QCOM_GPI_SPI>, 1488 <&gpi_dma1 1 3 QCOM_GPI_SPI>; 1489 dma-names = "tx", 1490 "rx"; 1491 1492 pinctrl-0 = <&qup_spi3_data_clk>, <&qup_spi3_cs>; 1493 pinctrl-names = "default"; 1494 1495 #address-cells = <1>; 1496 #size-cells = <0>; 1497 1498 status = "disabled"; 1499 }; 1500 1501 i2c4: i2c@a90000 { 1502 compatible = "qcom,geni-i2c"; 1503 reg = <0x0 0x00a90000 0x0 0x4000>; 1504 1505 interrupts = <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>; 1506 1507 clocks = <&gcc GCC_QUPV3_WRAP1_S4_CLK>; 1508 clock-names = "se"; 1509 1510 interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS 1511 &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>, 1512 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY 1513 &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ACTIVE_ONLY>, 1514 <&aggre1_noc MASTER_QUP_1 QCOM_ICC_TAG_ALWAYS 1515 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 1516 interconnect-names = "qup-core", 1517 "qup-config", 1518 "qup-memory"; 1519 1520 dmas = <&gpi_dma1 0 4 QCOM_GPI_I2C>, 1521 <&gpi_dma1 1 4 QCOM_GPI_I2C>; 1522 dma-names = "tx", 1523 "rx"; 1524 1525 pinctrl-0 = <&qup_i2c4_data_clk>; 1526 pinctrl-names = "default"; 1527 1528 #address-cells = <1>; 1529 #size-cells = <0>; 1530 1531 status = "disabled"; 1532 }; 1533 1534 spi4: spi@a90000 { 1535 compatible = "qcom,geni-spi"; 1536 reg = <0x0 0x00a90000 0x0 0x4000>; 1537 1538 interrupts = <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>; 1539 1540 clocks = <&gcc GCC_QUPV3_WRAP1_S4_CLK>; 1541 clock-names = "se"; 1542 1543 interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS 1544 &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>, 1545 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY 1546 &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ACTIVE_ONLY>, 1547 <&aggre1_noc MASTER_QUP_1 QCOM_ICC_TAG_ALWAYS 1548 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 1549 interconnect-names = "qup-core", 1550 "qup-config", 1551 "qup-memory"; 1552 1553 dmas = <&gpi_dma1 0 4 QCOM_GPI_SPI>, 1554 <&gpi_dma1 1 4 QCOM_GPI_SPI>; 1555 dma-names = "tx", 1556 "rx"; 1557 1558 pinctrl-0 = <&qup_spi4_clk>, <&qup_spi4_cs>, 1559 <&qup_spi4_data>; 1560 pinctrl-names = "default"; 1561 1562 #address-cells = <1>; 1563 #size-cells = <0>; 1564 1565 status = "disabled"; 1566 }; 1567 1568 uart5: serial@a94000 { 1569 compatible = "qcom,geni-uart"; 1570 reg = <0x0 0x00a94000 0x0 0x4000>; 1571 1572 interrupts = <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>; 1573 1574 clocks = <&gcc GCC_QUPV3_WRAP1_S5_CLK>; 1575 clock-names = "se"; 1576 1577 interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS 1578 &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>, 1579 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 1580 &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ALWAYS>; 1581 interconnect-names = "qup-core", 1582 "qup-config"; 1583 1584 pinctrl-0 = <&qup_uart5_default>, <&qup_uart5_cts_rts>; 1585 pinctrl-names = "default"; 1586 1587 status = "disabled"; 1588 }; 1589 1590 uart6: serial@a98000 { 1591 compatible = "qcom,geni-uart"; 1592 reg = <0x0 0x00a98000 0x0 0x4000>; 1593 1594 interrupts = <GIC_SPI 363 IRQ_TYPE_LEVEL_HIGH>; 1595 1596 clocks = <&gcc GCC_QUPV3_WRAP1_S6_CLK>; 1597 clock-names = "se"; 1598 1599 interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS 1600 &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>, 1601 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 1602 &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ALWAYS>; 1603 interconnect-names = "qup-core", 1604 "qup-config"; 1605 1606 pinctrl-0 = <&qup_uart6_default>, <&qup_uart6_cts_rts>; 1607 pinctrl-names = "default"; 1608 1609 status = "disabled"; 1610 }; 1611 1612 i2c7: i2c@a9c000 { 1613 compatible = "qcom,geni-i2c"; 1614 reg = <0x0 0x00a9c000 0x0 0x4000>; 1615 1616 interrupts = <GIC_SPI 579 IRQ_TYPE_LEVEL_HIGH>; 1617 1618 clocks = <&gcc GCC_QUPV3_WRAP1_S7_CLK>; 1619 clock-names = "se"; 1620 1621 interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS 1622 &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>, 1623 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY 1624 &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ACTIVE_ONLY>, 1625 <&aggre1_noc MASTER_QUP_1 QCOM_ICC_TAG_ALWAYS 1626 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 1627 interconnect-names = "qup-core", 1628 "qup-config", 1629 "qup-memory"; 1630 1631 dmas = <&gpi_dma1 0 7 QCOM_GPI_I2C>, 1632 <&gpi_dma1 1 7 QCOM_GPI_I2C>; 1633 dma-names = "tx", 1634 "rx"; 1635 1636 pinctrl-0 = <&qup_i2c7_data_clk>; 1637 pinctrl-names = "default"; 1638 1639 #address-cells = <1>; 1640 #size-cells = <0>; 1641 1642 status = "disabled"; 1643 }; 1644 1645 spi7: spi@a9c000 { 1646 compatible = "qcom,geni-spi"; 1647 reg = <0x0 0x00a9c000 0x0 0x4000>; 1648 1649 interrupts = <GIC_SPI 579 IRQ_TYPE_LEVEL_HIGH>; 1650 1651 clocks = <&gcc GCC_QUPV3_WRAP1_S7_CLK>; 1652 clock-names = "se"; 1653 1654 interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS 1655 &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>, 1656 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY 1657 &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ACTIVE_ONLY>, 1658 <&aggre1_noc MASTER_QUP_1 QCOM_ICC_TAG_ALWAYS 1659 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 1660 interconnect-names = "qup-core", 1661 "qup-config", 1662 "qup-memory"; 1663 1664 dmas = <&gpi_dma1 0 7 QCOM_GPI_SPI>, 1665 <&gpi_dma1 1 7 QCOM_GPI_SPI>; 1666 dma-names = "tx", 1667 "rx"; 1668 1669 pinctrl-0 = <&qup_spi7_data_clk>, <&qup_spi7_cs>; 1670 pinctrl-names = "default"; 1671 1672 #address-cells = <1>; 1673 #size-cells = <0>; 1674 1675 status = "disabled"; 1676 }; 1677 }; 1678 1679 sdhc_1: mmc@f44000 { 1680 compatible = "qcom,eliza-sdhci", "qcom,sdhci-msm-v5"; 1681 reg = <0x0 0x00f44000 0x0 0x1000>, 1682 <0x0 0x00f45000 0x0 0x1000>; 1683 reg-names = "hc", 1684 "cqhci"; 1685 1686 interrupts = <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>, 1687 <GIC_SPI 417 IRQ_TYPE_LEVEL_HIGH>; 1688 interrupt-names = "hc_irq", 1689 "pwr_irq"; 1690 1691 clocks = <&gcc GCC_SDCC1_AHB_CLK>, 1692 <&gcc GCC_SDCC1_APPS_CLK>, 1693 <&rpmhcc RPMH_CXO_CLK>; 1694 clock-names = "iface", 1695 "core", 1696 "xo"; 1697 1698 interconnects = <&aggre2_noc MASTER_SDCC_1 QCOM_ICC_TAG_ALWAYS 1699 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>, 1700 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY 1701 &config_noc 30 /*TODO: SLAVE_SDCC_1*/ QCOM_ICC_TAG_ACTIVE_ONLY>; 1702 interconnect-names = "sdhc-ddr", 1703 "cpu-sdhc"; 1704 1705 power-domains = <&rpmhpd RPMHPD_CX>; 1706 operating-points-v2 = <&sdhc1_opp_table>; 1707 1708 qcom,dll-config = <0x000f44ec>; 1709 qcom,ddr-config = <0x80040868>; 1710 1711 iommus = <&apps_smmu 0x520 0x0>; 1712 dma-coherent; 1713 1714 bus-width = <8>; 1715 1716 resets = <&gcc GCC_SDCC1_BCR>; 1717 1718 status = "disabled"; 1719 1720 sdhc1_opp_table: opp-table { 1721 compatible = "operating-points-v2"; 1722 1723 opp-100000000 { 1724 opp-hz = /bits/ 64 <100000000>; 1725 required-opps = <&rpmhpd_opp_low_svs>; 1726 }; 1727 1728 opp-384000000 { 1729 opp-hz = /bits/ 64 <384000000>; 1730 required-opps = <&rpmhpd_opp_svs_l1>; 1731 }; 1732 }; 1733 }; 1734 1735 cnoc_main: interconnect@1500000 { 1736 compatible = "qcom,eliza-cnoc-main"; 1737 reg = <0x0 0x01500000 0x0 0x16080>; 1738 qcom,bcm-voters = <&apps_bcm_voter>; 1739 #interconnect-cells = <2>; 1740 }; 1741 1742 config_noc: interconnect@1600000 { 1743 compatible = "qcom,eliza-cnoc-cfg"; 1744 reg = <0x0 0x01600000 0x0 0x5200>; 1745 qcom,bcm-voters = <&apps_bcm_voter>; 1746 #interconnect-cells = <2>; 1747 }; 1748 1749 system_noc: interconnect@1680000 { 1750 compatible = "qcom,eliza-system-noc"; 1751 reg = <0x0 0x01680000 0x0 0x40000>; 1752 qcom,bcm-voters = <&apps_bcm_voter>; 1753 #interconnect-cells = <2>; 1754 }; 1755 1756 pcie_noc: interconnect@16c0000 { 1757 compatible = "qcom,eliza-pcie-anoc"; 1758 reg = <0x0 0x016c0000 0x0 0x11400>; 1759 qcom,bcm-voters = <&apps_bcm_voter>; 1760 clocks = <&gcc GCC_AGGRE_NOC_PCIE_AXI_CLK>, 1761 <&gcc GCC_CFG_NOC_PCIE_ANOC_AHB_CLK>; 1762 #interconnect-cells = <2>; 1763 }; 1764 1765 aggre1_noc: interconnect@16e0000 { 1766 compatible = "qcom,eliza-aggre1-noc"; 1767 reg = <0x0 0x016e0000 0x0 0x16400>; 1768 qcom,bcm-voters = <&apps_bcm_voter>; 1769 clocks = <&gcc GCC_AGGRE_UFS_PHY_AXI_CLK>, 1770 <&gcc GCC_AGGRE_USB3_PRIM_AXI_CLK>; 1771 #interconnect-cells = <2>; 1772 }; 1773 1774 aggre2_noc: interconnect@1700000 { 1775 compatible = "qcom,eliza-aggre2-noc"; 1776 reg = <0x0 0x01700000 0x0 0x1f400>; 1777 qcom,bcm-voters = <&apps_bcm_voter>; 1778 clocks = <&rpmhcc RPMH_IPA_CLK>; 1779 #interconnect-cells = <2>; 1780 }; 1781 1782 mmss_noc: interconnect@1780000 { 1783 compatible = "qcom,eliza-mmss-noc"; 1784 reg = <0x0 0x01780000 0x0 0x7d800>; 1785 qcom,bcm-voters = <&apps_bcm_voter>; 1786 #interconnect-cells = <2>; 1787 }; 1788 1789 ufs_mem_phy: phy@1d80000 { 1790 compatible = "qcom,eliza-qmp-ufs-phy", 1791 "qcom,sm8650-qmp-ufs-phy"; 1792 reg = <0x0 0x01d80000 0x0 0x2000>; 1793 1794 clocks = <&rpmhcc RPMH_CXO_CLK>, 1795 <&gcc GCC_UFS_PHY_PHY_AUX_CLK>, 1796 <&tcsr TCSR_UFS_CLKREF_EN>; 1797 clock-names = "ref", 1798 "ref_aux", 1799 "qref"; 1800 1801 resets = <&ufs_mem_hc 0>; 1802 reset-names = "ufsphy"; 1803 1804 power-domains = <&gcc GCC_UFS_MEM_PHY_GDSC>; 1805 1806 #clock-cells = <1>; 1807 #phy-cells = <0>; 1808 1809 status = "disabled"; 1810 }; 1811 1812 ufs_mem_hc: ufshc@1d84000 { 1813 compatible = "qcom,eliza-ufshc", 1814 "qcom,ufshc", 1815 "jedec,ufs-2.0"; 1816 reg = <0x0 0x01d84000 0x0 0x3000>, 1817 <0x0 0x01da0000 0x0 0x15000>; 1818 reg-names = "std", 1819 "mcq"; 1820 1821 interrupts = <GIC_SPI 265 IRQ_TYPE_LEVEL_HIGH>; 1822 1823 clocks = <&gcc GCC_UFS_PHY_AXI_CLK>, 1824 <&gcc GCC_AGGRE_UFS_PHY_AXI_CLK>, 1825 <&gcc GCC_UFS_PHY_AHB_CLK>, 1826 <&gcc GCC_UFS_PHY_UNIPRO_CORE_CLK>, 1827 <&rpmhcc RPMH_LN_BB_CLK3>, 1828 <&gcc GCC_UFS_PHY_TX_SYMBOL_0_CLK>, 1829 <&gcc GCC_UFS_PHY_RX_SYMBOL_0_CLK>, 1830 <&gcc GCC_UFS_PHY_RX_SYMBOL_1_CLK>; 1831 clock-names = "core_clk", 1832 "bus_aggr_clk", 1833 "iface_clk", 1834 "core_clk_unipro", 1835 "ref_clk", 1836 "tx_lane0_sync_clk", 1837 "rx_lane0_sync_clk", 1838 "rx_lane1_sync_clk"; 1839 1840 operating-points-v2 = <&ufs_opp_table>; 1841 1842 resets = <&gcc GCC_UFS_PHY_BCR>; 1843 reset-names = "rst"; 1844 1845 interconnects = <&aggre1_noc MASTER_UFS_MEM QCOM_ICC_TAG_ALWAYS 1846 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>, 1847 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY 1848 &config_noc SLAVE_UFS_MEM_CFG QCOM_ICC_TAG_ACTIVE_ONLY>; 1849 interconnect-names = "ufs-ddr", 1850 "cpu-ufs"; 1851 1852 power-domains = <&gcc GCC_UFS_PHY_GDSC>; 1853 required-opps = <&rpmhpd_opp_nom>; 1854 1855 iommus = <&apps_smmu 0x60 0x0>; 1856 dma-coherent; 1857 1858 msi-parent = <&gic_its 0x60>; 1859 1860 lanes-per-direction = <2>; 1861 qcom,ice = <&ice>; 1862 1863 phys = <&ufs_mem_phy>; 1864 phy-names = "ufsphy"; 1865 1866 #reset-cells = <1>; 1867 1868 status = "disabled"; 1869 1870 ufs_opp_table: opp-table { 1871 compatible = "operating-points-v2"; 1872 1873 opp-100000000 { 1874 opp-hz = /bits/ 64 <100000000>, 1875 /bits/ 64 <0>, 1876 /bits/ 64 <0>, 1877 /bits/ 64 <100000000>, 1878 /bits/ 64 <0>, 1879 /bits/ 64 <0>, 1880 /bits/ 64 <0>, 1881 /bits/ 64 <0>; 1882 required-opps = <&rpmhpd_opp_low_svs>; 1883 }; 1884 1885 opp-201500000 { 1886 opp-hz = /bits/ 64 <201500000>, 1887 /bits/ 64 <0>, 1888 /bits/ 64 <0>, 1889 /bits/ 64 <201500000>, 1890 /bits/ 64 <0>, 1891 /bits/ 64 <0>, 1892 /bits/ 64 <0>, 1893 /bits/ 64 <0>; 1894 required-opps = <&rpmhpd_opp_svs_l1>; 1895 }; 1896 1897 opp-403000000 { 1898 opp-hz = /bits/ 64 <403000000>, 1899 /bits/ 64 <0>, 1900 /bits/ 64 <0>, 1901 /bits/ 64 <403000000>, 1902 /bits/ 64 <0>, 1903 /bits/ 64 <0>, 1904 /bits/ 64 <0>, 1905 /bits/ 64 <0>; 1906 required-opps = <&rpmhpd_opp_nom>; 1907 }; 1908 }; 1909 }; 1910 1911 ice: crypto@1d88000 { 1912 compatible = "qcom,eliza-inline-crypto-engine", 1913 "qcom,inline-crypto-engine"; 1914 reg = <0x0 0x01d88000 0x0 0x18000>; 1915 1916 clocks = <&gcc GCC_UFS_PHY_ICE_CORE_CLK>, 1917 <&gcc GCC_UFS_PHY_AHB_CLK>; 1918 clock-names = "core", 1919 "iface"; 1920 power-domains = <&gcc GCC_UFS_PHY_GDSC>; 1921 }; 1922 1923 cryptobam: dma-controller@1dc4000 { 1924 compatible = "qcom,bam-v1.7.4", "qcom,bam-v1.7.0"; 1925 reg = <0x0 0x01dc4000 0x0 0x28000>; 1926 1927 interrupts = <GIC_SPI 272 IRQ_TYPE_LEVEL_HIGH>; 1928 1929 #dma-cells = <1>; 1930 1931 iommus = <&apps_smmu 0x480 0>, 1932 <&apps_smmu 0x481 0>; 1933 1934 qcom,ee = <0>; 1935 qcom,num-ees = <4>; 1936 num-channels = <20>; 1937 qcom,controlled-remotely; 1938 }; 1939 1940 crypto: crypto@1dfa000 { 1941 compatible = "qcom,eliza-qce", "qcom,sm8150-qce", "qcom,qce"; 1942 reg = <0x0 0x01dfa000 0x0 0x6000>; 1943 1944 interconnects = <&aggre2_noc MASTER_CRYPTO QCOM_ICC_TAG_ALWAYS 1945 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 1946 interconnect-names = "memory"; 1947 1948 dmas = <&cryptobam 4>, <&cryptobam 5>; 1949 dma-names = "rx", "tx"; 1950 1951 iommus = <&apps_smmu 0x480 0>, 1952 <&apps_smmu 0x481 0>; 1953 }; 1954 1955 tcsr_mutex: hwlock@1f40000 { 1956 compatible = "qcom,tcsr-mutex"; 1957 reg = <0x0 0x01f40000 0x0 0x20000>; 1958 #hwlock-cells = <1>; 1959 }; 1960 1961 tcsr: clock-controller@1fbf000 { 1962 compatible = "qcom,eliza-tcsr", "syscon"; 1963 reg = <0x0 0x01fbf000 0x0 0x21000>; 1964 1965 clocks = <&rpmhcc RPMH_CXO_CLK>; 1966 1967 #clock-cells = <1>; 1968 #reset-cells = <1>; 1969 }; 1970 1971 remoteproc_adsp: remoteproc@3000000 { 1972 compatible = "qcom,eliza-adsp-pas"; 1973 reg = <0x0 0x03000000 0x0 0x10000>; 1974 1975 interrupts-extended = <&pdc 6 IRQ_TYPE_EDGE_RISING>, 1976 <&smp2p_adsp_in 0 IRQ_TYPE_EDGE_RISING>, 1977 <&smp2p_adsp_in 1 IRQ_TYPE_EDGE_RISING>, 1978 <&smp2p_adsp_in 2 IRQ_TYPE_EDGE_RISING>, 1979 <&smp2p_adsp_in 3 IRQ_TYPE_EDGE_RISING>, 1980 <&smp2p_adsp_in 7 IRQ_TYPE_EDGE_RISING>; 1981 interrupt-names = "wdog", 1982 "fatal", 1983 "ready", 1984 "handover", 1985 "stop-ack", 1986 "shutdown-ack"; 1987 1988 clocks = <&rpmhcc RPMH_CXO_CLK>; 1989 clock-names = "xo"; 1990 1991 power-domains = <&rpmhpd RPMHPD_LCX>, 1992 <&rpmhpd RPMHPD_LMX>; 1993 power-domain-names = "lcx", 1994 "lmx"; 1995 1996 interconnects = <&lpass_lpicx_noc MASTER_LPASS_PROC QCOM_ICC_TAG_ALWAYS 1997 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 1998 1999 memory-region = <&adspslpi_mem>, <&q6_adsp_dtb_mem>; 2000 2001 qcom,qmp = <&aoss_qmp>; 2002 2003 qcom,smem-states = <&smp2p_adsp_out 0>; 2004 qcom,smem-state-names = "stop"; 2005 2006 status = "disabled"; 2007 2008 glink-edge { 2009 interrupts-extended = <&ipcc IPCC_CLIENT_LPASS 2010 IPCC_MPROC_SIGNAL_GLINK_QMP 2011 IRQ_TYPE_EDGE_RISING>; 2012 mboxes = <&ipcc IPCC_CLIENT_LPASS 2013 IPCC_MPROC_SIGNAL_GLINK_QMP>; 2014 2015 label = "lpass"; 2016 qcom,remote-pid = <2>; 2017 }; 2018 }; 2019 2020 lpass_lpiaon_noc: interconnect@7400000 { 2021 compatible = "qcom,eliza-lpass-lpiaon-noc"; 2022 reg = <0x0 0x07400000 0x0 0x19080>; 2023 qcom,bcm-voters = <&apps_bcm_voter>; 2024 #interconnect-cells = <2>; 2025 }; 2026 2027 lpass_lpicx_noc: interconnect@7420000 { 2028 compatible = "qcom,eliza-lpass-lpicx-noc"; 2029 reg = <0x0 0x07420000 0x0 0x44080>; 2030 qcom,bcm-voters = <&apps_bcm_voter>; 2031 #interconnect-cells = <2>; 2032 }; 2033 2034 sdhc_2: mmc@8804000 { 2035 compatible = "qcom,eliza-sdhci", "qcom,sdhci-msm-v5"; 2036 reg = <0x0 0x08804000 0x0 0x1000>; 2037 2038 interrupts = <GIC_SPI 207 IRQ_TYPE_LEVEL_HIGH>, 2039 <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>; 2040 interrupt-names = "hc_irq", 2041 "pwr_irq"; 2042 2043 clocks = <&gcc GCC_SDCC2_AHB_CLK>, 2044 <&gcc GCC_SDCC2_APPS_CLK>, 2045 <&rpmhcc RPMH_CXO_CLK>; 2046 clock-names = "iface", 2047 "core", 2048 "xo"; 2049 2050 interconnects = <&aggre2_noc MASTER_SDCC_2 QCOM_ICC_TAG_ALWAYS 2051 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>, 2052 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY 2053 &config_noc SLAVE_SDCC_2 QCOM_ICC_TAG_ACTIVE_ONLY>; 2054 interconnect-names = "sdhc-ddr", 2055 "cpu-sdhc"; 2056 2057 power-domains = <&rpmhpd RPMHPD_CX>; 2058 operating-points-v2 = <&sdhc2_opp_table>; 2059 2060 qcom,dll-config = <0x0007442c>; 2061 qcom,ddr-config = <0x80040868>; 2062 2063 iommus = <&apps_smmu 0x540 0x0>; 2064 dma-coherent; 2065 2066 bus-width = <4>; 2067 2068 resets = <&gcc GCC_SDCC2_BCR>; 2069 2070 status = "disabled"; 2071 2072 sdhc2_opp_table: opp-table { 2073 compatible = "operating-points-v2"; 2074 2075 opp-100000000 { 2076 opp-hz = /bits/ 64 <100000000>; 2077 required-opps = <&rpmhpd_opp_low_svs>; 2078 }; 2079 2080 opp-202000000 { 2081 opp-hz = /bits/ 64 <202000000>; 2082 required-opps = <&rpmhpd_opp_svs_l1>; 2083 }; 2084 }; 2085 }; 2086 2087 usb_hsphy: phy@88e3000 { 2088 compatible = "qcom,eliza-snps-eusb2-phy", 2089 "qcom,sm8550-snps-eusb2-phy"; 2090 reg = <0x0 0x088e3000 0x0 0x154>; 2091 #phy-cells = <0>; 2092 2093 clocks = <&tcsr TCSR_USB2_CLKREF_EN>; 2094 clock-names = "ref"; 2095 2096 resets = <&gcc GCC_QUSB2PHY_PRIM_BCR>; 2097 2098 status = "disabled"; 2099 }; 2100 2101 usb_dp_qmpphy: phy@88e8000 { 2102 compatible = "qcom,eliza-qmp-usb3-dp-phy", 2103 "qcom,sm8650-qmp-usb3-dp-phy"; 2104 reg = <0x0 0x088e8000 0x0 0x4000>; 2105 2106 clocks = <&gcc GCC_USB3_PRIM_PHY_AUX_CLK>, 2107 <&tcsr TCSR_USB3_CLKREF_EN>, 2108 <&gcc GCC_USB3_PRIM_PHY_COM_AUX_CLK>, 2109 <&gcc GCC_USB3_PRIM_PHY_PIPE_CLK>; 2110 clock-names = "aux", 2111 "ref", 2112 "com_aux", 2113 "usb3_pipe"; 2114 2115 resets = <&gcc GCC_USB3_PHY_PRIM_BCR>, 2116 <&gcc GCC_USB3_DP_PHY_PRIM_BCR>; 2117 reset-names = "phy", 2118 "common"; 2119 2120 power-domains = <&gcc GCC_USB3_PHY_GDSC>; 2121 2122 #clock-cells = <1>; 2123 #phy-cells = <1>; 2124 2125 mode-switch; 2126 orientation-switch; 2127 2128 status = "disabled"; 2129 2130 ports { 2131 #address-cells = <1>; 2132 #size-cells = <0>; 2133 2134 port@0 { 2135 reg = <0>; 2136 2137 usb_dp_qmpphy_out: endpoint { 2138 }; 2139 }; 2140 2141 port@1 { 2142 reg = <1>; 2143 2144 usb_dp_qmpphy_usb_ss_in: endpoint { 2145 remote-endpoint = <&usb_dwc3_ss>; 2146 }; 2147 }; 2148 2149 port@2 { 2150 reg = <2>; 2151 2152 usb_dp_qmpphy_dp_in: endpoint { 2153 remote-endpoint = <&mdss_dp0_out>; 2154 }; 2155 }; 2156 }; 2157 }; 2158 2159 usb: usb@a600000 { 2160 compatible = "qcom,eliza-dwc3", "qcom,snps-dwc3"; 2161 reg = <0x0 0x0a600000 0x0 0xfc100>; 2162 2163 interrupts-extended = <&intc GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>, 2164 <&intc GIC_SPI 130 IRQ_TYPE_LEVEL_HIGH>, 2165 <&intc GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>, 2166 <&pdc 14 IRQ_TYPE_EDGE_BOTH>, 2167 <&pdc 15 IRQ_TYPE_EDGE_BOTH>, 2168 <&pdc 17 IRQ_TYPE_LEVEL_HIGH>; 2169 interrupt-names = "dwc_usb3", 2170 "pwr_event", 2171 "hs_phy_irq", 2172 "dp_hs_phy_irq", 2173 "dm_hs_phy_irq", 2174 "ss_phy_irq"; 2175 2176 clocks = <&gcc GCC_CFG_NOC_USB3_PRIM_AXI_CLK>, 2177 <&gcc GCC_USB30_PRIM_MASTER_CLK>, 2178 <&gcc GCC_AGGRE_USB3_PRIM_AXI_CLK>, 2179 <&gcc GCC_USB30_PRIM_SLEEP_CLK>, 2180 <&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>, 2181 <&rpmhcc RPMH_CXO_CLK>; 2182 clock-names = "cfg_noc", 2183 "core", 2184 "iface", 2185 "sleep", 2186 "mock_utmi", 2187 "xo"; 2188 2189 assigned-clocks = <&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>, 2190 <&gcc GCC_USB30_PRIM_MASTER_CLK>; 2191 assigned-clock-rates = <19200000>, 2192 <200000000>; 2193 2194 resets = <&gcc GCC_USB30_PRIM_BCR>; 2195 2196 phys = <&usb_hsphy>, 2197 <&usb_dp_qmpphy QMP_USB43DP_USB3_PHY>; 2198 phy-names = "usb2-phy", 2199 "usb3-phy"; 2200 2201 interconnects = <&aggre1_noc MASTER_USB3_0 QCOM_ICC_TAG_ALWAYS 2202 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>, 2203 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY 2204 &config_noc SLAVE_USB3_0 QCOM_ICC_TAG_ACTIVE_ONLY>; 2205 interconnect-names = "usb-ddr", "apps-usb"; 2206 2207 iommus = <&apps_smmu 0x40 0x0>; 2208 2209 power-domains = <&gcc GCC_USB30_PRIM_GDSC>; 2210 required-opps = <&rpmhpd_opp_nom>; 2211 2212 snps,hird-threshold = /bits/ 8 <0x0>; 2213 snps,usb2-gadget-lpm-disable; 2214 snps,dis_u2_susphy_quirk; 2215 snps,dis_enblslpm_quirk; 2216 snps,dis-u1-entry-quirk; 2217 snps,dis-u2-entry-quirk; 2218 snps,is-utmi-l1-suspend; 2219 snps,usb3_lpm_capable; 2220 snps,usb2-lpm-disable; 2221 snps,has-lpm-erratum; 2222 tx-fifo-resize; 2223 2224 dma-coherent; 2225 usb-role-switch; 2226 2227 status = "disabled"; 2228 2229 ports { 2230 #address-cells = <1>; 2231 #size-cells = <0>; 2232 2233 port@0 { 2234 reg = <0>; 2235 2236 usb_dwc3_hs: endpoint { 2237 }; 2238 }; 2239 2240 port@1 { 2241 reg = <1>; 2242 2243 usb_dwc3_ss: endpoint { 2244 remote-endpoint = <&usb_dp_qmpphy_usb_ss_in>; 2245 }; 2246 }; 2247 }; 2248 }; 2249 2250 mdss: display-subsystem@ae00000 { 2251 compatible = "qcom,eliza-mdss"; 2252 reg = <0x0 0x0ae00000 0x0 0x1000>; 2253 reg-names = "mdss"; 2254 ranges; 2255 2256 interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>; 2257 2258 clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>, 2259 <&gcc GCC_DISP_HF_AXI_CLK>, 2260 <&dispcc DISP_CC_MDSS_MDP_CLK>; 2261 2262 resets = <&dispcc DISP_CC_MDSS_CORE_BCR>; 2263 2264 interconnects = <&mmss_noc MASTER_MDP QCOM_ICC_TAG_ALWAYS 2265 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>, 2266 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY 2267 &config_noc SLAVE_DISPLAY_CFG QCOM_ICC_TAG_ACTIVE_ONLY>; 2268 interconnect-names = "mdp0-mem", 2269 "cpu-cfg"; 2270 2271 power-domains = <&dispcc MDSS_GDSC>; 2272 2273 iommus = <&apps_smmu 0x800 0x2>; 2274 2275 interrupt-controller; 2276 #interrupt-cells = <1>; 2277 2278 #address-cells = <2>; 2279 #size-cells = <2>; 2280 2281 status = "disabled"; 2282 2283 mdss_mdp: display-controller@ae01000 { 2284 compatible = "qcom,eliza-dpu"; 2285 reg = <0x0 0x0ae01000 0x0 0x93000>, 2286 <0x0 0x0aeb0000 0x0 0x3000>; 2287 reg-names = "mdp", 2288 "vbif"; 2289 2290 interrupts-extended = <&mdss 0>; 2291 2292 clocks = <&gcc GCC_DISP_HF_AXI_CLK>, 2293 <&dispcc DISP_CC_MDSS_AHB_CLK>, 2294 <&dispcc DISP_CC_MDSS_MDP_LUT_CLK>, 2295 <&dispcc DISP_CC_MDSS_MDP_CLK>, 2296 <&dispcc DISP_CC_MDSS_VSYNC_CLK>; 2297 clock-names = "nrt_bus", 2298 "iface", 2299 "lut", 2300 "core", 2301 "vsync"; 2302 2303 assigned-clocks = <&dispcc DISP_CC_MDSS_VSYNC_CLK>; 2304 assigned-clock-rates = <19200000>; 2305 2306 operating-points-v2 = <&mdp_opp_table>; 2307 2308 power-domains = <&rpmhpd RPMHPD_CX>; 2309 2310 ports { 2311 #address-cells = <1>; 2312 #size-cells = <0>; 2313 2314 port@0 { 2315 reg = <0>; 2316 2317 dpu_intf1_out: endpoint { 2318 remote-endpoint = <&mdss_dsi0_in>; 2319 }; 2320 }; 2321 2322 port@1 { 2323 reg = <1>; 2324 2325 dpu_intf2_out: endpoint { 2326 remote-endpoint = <&mdss_dsi1_in>; 2327 }; 2328 }; 2329 2330 port@2 { 2331 reg = <2>; 2332 2333 dpu_intf0_out: endpoint { 2334 remote-endpoint = <&mdss_dp0_in>; 2335 }; 2336 }; 2337 /* TODO: HDMI */ 2338 }; 2339 2340 mdp_opp_table: opp-table { 2341 compatible = "operating-points-v2"; 2342 2343 opp-150000000 { 2344 opp-hz = /bits/ 64 <150000000>; 2345 required-opps = <&rpmhpd_opp_low_svs_d1>; 2346 }; 2347 2348 opp-207000000 { 2349 opp-hz = /bits/ 64 <207000000>; 2350 required-opps = <&rpmhpd_opp_low_svs>; 2351 }; 2352 2353 opp-342000000 { 2354 opp-hz = /bits/ 64 <342000000>; 2355 required-opps = <&rpmhpd_opp_svs>; 2356 }; 2357 2358 opp-417000000 { 2359 opp-hz = /bits/ 64 <417000000>; 2360 required-opps = <&rpmhpd_opp_svs_l1>; 2361 }; 2362 2363 opp-532000000 { 2364 opp-hz = /bits/ 64 <532000000>; 2365 required-opps = <&rpmhpd_opp_nom>; 2366 }; 2367 2368 opp-600000000 { 2369 opp-hz = /bits/ 64 <600000000>; 2370 required-opps = <&rpmhpd_opp_nom_l1>; 2371 }; 2372 2373 opp-660000000 { 2374 opp-hz = /bits/ 64 <660000000>; 2375 required-opps = <&rpmhpd_opp_turbo>; 2376 }; 2377 }; 2378 }; 2379 2380 mdss_dsi0: dsi@ae94000 { 2381 compatible = "qcom,eliza-dsi-ctrl", "qcom,sm8750-dsi-ctrl", 2382 "qcom,mdss-dsi-ctrl"; 2383 reg = <0x0 0x0ae94000 0x0 0x400>; 2384 reg-names = "dsi_ctrl"; 2385 2386 interrupts-extended = <&mdss 4>; 2387 2388 clocks = <&dispcc DISP_CC_MDSS_BYTE0_CLK>, 2389 <&dispcc DISP_CC_MDSS_BYTE0_INTF_CLK>, 2390 <&dispcc DISP_CC_MDSS_PCLK0_CLK>, 2391 <&dispcc DISP_CC_MDSS_ESC0_CLK>, 2392 <&dispcc DISP_CC_MDSS_AHB_CLK>, 2393 <&gcc GCC_DISP_HF_AXI_CLK>, 2394 <&mdss_dsi0_phy DSI_PIXEL_PLL_CLK>, 2395 <&mdss_dsi0_phy DSI_BYTE_PLL_CLK>, 2396 <&dispcc DISP_CC_ESYNC0_CLK>, 2397 <&dispcc DISP_CC_OSC_CLK>, 2398 <&dispcc DISP_CC_MDSS_BYTE0_CLK_SRC>, 2399 <&dispcc DISP_CC_MDSS_PCLK0_CLK_SRC>; 2400 clock-names = "byte", 2401 "byte_intf", 2402 "pixel", 2403 "core", 2404 "iface", 2405 "bus", 2406 "dsi_pll_pixel", 2407 "dsi_pll_byte", 2408 "esync", 2409 "osc", 2410 "byte_src", 2411 "pixel_src"; 2412 2413 operating-points-v2 = <&mdss_dsi_opp_table>; 2414 2415 phys = <&mdss_dsi0_phy>; 2416 phy-names = "dsi"; 2417 2418 #address-cells = <1>; 2419 #size-cells = <0>; 2420 2421 status = "disabled"; 2422 2423 ports { 2424 #address-cells = <1>; 2425 #size-cells = <0>; 2426 2427 port@0 { 2428 reg = <0>; 2429 2430 mdss_dsi0_in: endpoint { 2431 remote-endpoint = <&dpu_intf1_out>; 2432 }; 2433 }; 2434 2435 port@1 { 2436 reg = <1>; 2437 2438 mdss_dsi0_out: endpoint { 2439 }; 2440 }; 2441 }; 2442 2443 mdss_dsi_opp_table: opp-table { 2444 compatible = "operating-points-v2"; 2445 2446 opp-140630000 { 2447 opp-hz = /bits/ 64 <140630000>; 2448 required-opps = <&rpmhpd_opp_low_svs_d1>; 2449 }; 2450 2451 opp-187500000 { 2452 opp-hz = /bits/ 64 <187500000>; 2453 required-opps = <&rpmhpd_opp_low_svs>; 2454 }; 2455 2456 opp-300000000 { 2457 opp-hz = /bits/ 64 <300000000>; 2458 required-opps = <&rpmhpd_opp_svs>; 2459 }; 2460 2461 opp-358000000 { 2462 opp-hz = /bits/ 64 <358000000>; 2463 required-opps = <&rpmhpd_opp_svs_l1>; 2464 }; 2465 }; 2466 }; 2467 2468 mdss_dsi0_phy: phy@ae95000 { 2469 compatible = "qcom,eliza-dsi-phy-4nm", "qcom,sm8650-dsi-phy-4nm"; 2470 reg = <0x0 0x0ae95000 0x0 0x200>, 2471 <0x0 0x0ae95200 0x0 0x300>, 2472 <0x0 0x0ae95500 0x0 0x400>; 2473 reg-names = "dsi_phy", 2474 "dsi_phy_lane", 2475 "dsi_pll"; 2476 2477 clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>, 2478 <&bi_tcxo_div2>; 2479 clock-names = "iface", 2480 "ref"; 2481 2482 #clock-cells = <1>; 2483 #phy-cells = <0>; 2484 2485 status = "disabled"; 2486 }; 2487 2488 mdss_dsi1: dsi@ae96000 { 2489 compatible = "qcom,eliza-dsi-ctrl", "qcom,sm8750-dsi-ctrl", 2490 "qcom,mdss-dsi-ctrl"; 2491 reg = <0x0 0x0ae96000 0x0 0x400>; 2492 reg-names = "dsi_ctrl"; 2493 2494 interrupts-extended = <&mdss 5>; 2495 2496 clocks = <&dispcc DISP_CC_MDSS_BYTE1_CLK>, 2497 <&dispcc DISP_CC_MDSS_BYTE1_INTF_CLK>, 2498 <&dispcc DISP_CC_MDSS_PCLK1_CLK>, 2499 <&dispcc DISP_CC_MDSS_ESC1_CLK>, 2500 <&dispcc DISP_CC_MDSS_AHB_CLK>, 2501 <&gcc GCC_DISP_HF_AXI_CLK>, 2502 <&mdss_dsi1_phy DSI_PIXEL_PLL_CLK>, 2503 <&mdss_dsi1_phy DSI_BYTE_PLL_CLK>, 2504 <&dispcc DISP_CC_ESYNC1_CLK>, 2505 <&dispcc DISP_CC_OSC_CLK>, 2506 <&dispcc DISP_CC_MDSS_BYTE1_CLK_SRC>, 2507 <&dispcc DISP_CC_MDSS_PCLK1_CLK_SRC>; 2508 clock-names = "byte", 2509 "byte_intf", 2510 "pixel", 2511 "core", 2512 "iface", 2513 "bus", 2514 "dsi_pll_pixel", 2515 "dsi_pll_byte", 2516 "esync", 2517 "osc", 2518 "byte_src", 2519 "pixel_src"; 2520 2521 operating-points-v2 = <&mdss_dsi_opp_table>; 2522 2523 phys = <&mdss_dsi1_phy>; 2524 phy-names = "dsi"; 2525 2526 #address-cells = <1>; 2527 #size-cells = <0>; 2528 2529 status = "disabled"; 2530 2531 ports { 2532 #address-cells = <1>; 2533 #size-cells = <0>; 2534 2535 port@0 { 2536 reg = <0>; 2537 2538 mdss_dsi1_in: endpoint { 2539 remote-endpoint = <&dpu_intf2_out>; 2540 }; 2541 }; 2542 2543 port@1 { 2544 reg = <1>; 2545 2546 mdss_dsi1_out: endpoint { 2547 }; 2548 }; 2549 }; 2550 }; 2551 2552 mdss_dsi1_phy: phy@ae97000 { 2553 compatible = "qcom,eliza-dsi-phy-4nm", "qcom,sm8650-dsi-phy-4nm"; 2554 reg = <0x0 0x0ae97000 0x0 0x200>, 2555 <0x0 0x0ae97200 0x0 0x300>, 2556 <0x0 0x0ae97500 0x0 0x400>; 2557 reg-names = "dsi_phy", 2558 "dsi_phy_lane", 2559 "dsi_pll"; 2560 2561 clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>, 2562 <&rpmhcc RPMH_CXO_CLK>; 2563 clock-names = "iface", 2564 "ref"; 2565 2566 #clock-cells = <1>; 2567 #phy-cells = <0>; 2568 2569 status = "disabled"; 2570 }; 2571 2572 mdss_dp0: displayport-controller@af54000 { 2573 compatible = "qcom,eliza-dp", "qcom,sm8650-dp"; 2574 reg = <0x0 0x0af54000 0x0 0x200>, 2575 <0x0 0x0af54200 0x0 0x200>, 2576 <0x0 0x0af55000 0x0 0xc00>, 2577 <0x0 0x0af56000 0x0 0x400>, 2578 <0x0 0x0af57000 0x0 0x400>, 2579 <0x0 0x0af58000 0x0 0x400>, 2580 <0x0 0x0af59000 0x0 0x400>, 2581 <0x0 0x0af5a000 0x0 0x600>, 2582 <0x0 0x0af5b000 0x0 0x600>; 2583 2584 interrupts-extended = <&mdss 12>; 2585 2586 clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>, 2587 <&dispcc DISP_CC_MDSS_DPTX0_AUX_CLK>, 2588 <&dispcc DISP_CC_MDSS_DPTX0_LINK_CLK>, 2589 <&dispcc DISP_CC_MDSS_DPTX0_LINK_INTF_CLK>, 2590 <&dispcc DISP_CC_MDSS_DPTX0_PIXEL0_CLK>, 2591 <&dispcc DISP_CC_MDSS_DPTX0_PIXEL1_CLK>; 2592 clock-names = "core_iface", 2593 "core_aux", 2594 "ctrl_link", 2595 "ctrl_link_iface", 2596 "stream_pixel", 2597 "stream_1_pixel"; 2598 2599 assigned-clocks = <&dispcc DISP_CC_MDSS_DPTX0_LINK_CLK_SRC>, 2600 <&dispcc DISP_CC_MDSS_DPTX0_PIXEL0_CLK_SRC>, 2601 <&dispcc DISP_CC_MDSS_DPTX0_PIXEL1_CLK_SRC>; 2602 assigned-clock-parents = <&usb_dp_qmpphy QMP_USB43DP_DP_LINK_CLK>, 2603 <&usb_dp_qmpphy QMP_USB43DP_DP_VCO_DIV_CLK>, 2604 <&usb_dp_qmpphy QMP_USB43DP_DP_VCO_DIV_CLK>; 2605 2606 operating-points-v2 = <&dp_opp_table>; 2607 2608 power-domains = <&rpmhpd RPMHPD_CX>; 2609 2610 phys = <&usb_dp_qmpphy QMP_USB43DP_DP_PHY>; 2611 phy-names = "dp"; 2612 2613 #sound-dai-cells = <0>; 2614 2615 status = "disabled"; 2616 2617 dp_opp_table: opp-table { 2618 compatible = "operating-points-v2"; 2619 2620 opp-270000000 { 2621 opp-hz = /bits/ 64 <270000000>; 2622 required-opps = <&rpmhpd_opp_low_svs>; 2623 }; 2624 2625 opp-540000000 { 2626 opp-hz = /bits/ 64 <540000000>; 2627 required-opps = <&rpmhpd_opp_svs_l1>; 2628 }; 2629 2630 opp-810000000 { 2631 opp-hz = /bits/ 64 <810000000>; 2632 required-opps = <&rpmhpd_opp_nom>; 2633 }; 2634 }; 2635 2636 ports { 2637 #address-cells = <1>; 2638 #size-cells = <0>; 2639 2640 port@0 { 2641 reg = <0>; 2642 2643 mdss_dp0_in: endpoint { 2644 remote-endpoint = <&dpu_intf0_out>; 2645 }; 2646 }; 2647 2648 port@1 { 2649 reg = <1>; 2650 2651 mdss_dp0_out: endpoint { 2652 data-lanes = <0 1 2 3>; 2653 remote-endpoint = <&usb_dp_qmpphy_dp_in>; 2654 }; 2655 }; 2656 }; 2657 }; 2658 }; 2659 2660 dispcc: clock-controller@af00000 { 2661 compatible = "qcom,eliza-dispcc"; 2662 reg = <0x0 0x0af00000 0x0 0x20000>; 2663 2664 clocks = <&bi_tcxo_div2>, 2665 <&bi_tcxo_ao_div2>, 2666 <&gcc GCC_DISP_AHB_CLK>, 2667 <&sleep_clk>, 2668 <&mdss_dsi0_phy DSI_BYTE_PLL_CLK>, 2669 <&mdss_dsi0_phy DSI_PIXEL_PLL_CLK>, 2670 <&mdss_dsi1_phy DSI_BYTE_PLL_CLK>, 2671 <&mdss_dsi1_phy DSI_PIXEL_PLL_CLK>, 2672 <&usb_dp_qmpphy QMP_USB43DP_DP_LINK_CLK>, 2673 <&usb_dp_qmpphy QMP_USB43DP_DP_VCO_DIV_CLK>, 2674 <0>, /* dp1 */ 2675 <0>, 2676 <0>, /* dp2 */ 2677 <0>, 2678 <0>, /* dp3 */ 2679 <0>, 2680 <0>; /* HDMI phy */ 2681 2682 power-domains = <&rpmhpd RPMHPD_MX>; 2683 required-opps = <&rpmhpd_opp_low_svs>; 2684 2685 #clock-cells = <1>; 2686 #reset-cells = <1>; 2687 #power-domain-cells = <1>; 2688 }; 2689 2690 lpass_ag_noc: interconnect@7e40000 { 2691 compatible = "qcom,eliza-lpass-ag-noc"; 2692 reg = <0x0 0x07e40000 0x0 0xe080>; 2693 qcom,bcm-voters = <&apps_bcm_voter>; 2694 #interconnect-cells = <2>; 2695 }; 2696 2697 pdc: interrupt-controller@b220000 { 2698 compatible = "qcom,eliza-pdc", "qcom,pdc"; 2699 reg = <0x0 0x0b220000 0x0 0x40000>, 2700 <0x0 0x174000f0 0x0 0x64>; 2701 2702 qcom,pdc-ranges = <0 480 8>, <8 719 1>, <9 718 1>, 2703 <10 230 1>, <11 724 1>, <12 716 1>, 2704 <13 727 1>, <14 720 1>, <15 726 1>, 2705 <16 721 1>, <17 262 1>, <18 70 1>, 2706 <19 723 1>, <20 234 1>, <22 725 1>, 2707 <23 231 1>, <24 504 5>, <30 510 8>, 2708 <40 520 6>, <51 531 4>, <58 538 2>, 2709 <61 541 5>, <66 92 1>, <67 547 13>, 2710 <80 240 1>, <81 235 1>, <82 310 2>, 2711 <84 248 1>, <85 241 1>, <86 238 2>, 2712 <88 254 1>, <89 509 1>, <90 563 1>, 2713 <91 259 2>, <93 201 1>, <94 246 1>, 2714 <95 93 1>, <96 611 29>, <125 63 1>, 2715 <126 366 2>, <128 374 1>, <129 377 1>, 2716 <130 428 1>, <131 434 2>, <133 437 1>, 2717 <134 452 2>, <136 458 2>, <138 464 11>, 2718 <149 671 1>, <150 688 1>, <151 714 2>, 2719 <153 722 1>, <154 255 1>, <155 269 2>, 2720 <157 276 1>, <158 287 1>, <159 306 4>; 2721 #interrupt-cells = <2>; 2722 interrupt-parent = <&intc>; 2723 interrupt-controller; 2724 }; 2725 2726 tsens0: thermal-sensor@c228000 { 2727 compatible = "qcom,eliza-tsens", "qcom,tsens-v2"; 2728 reg = <0x0 0x0c228000 0x0 0x1000>, 2729 <0x0 0x0c222000 0x0 0x1000>; 2730 2731 interrupts = <GIC_SPI 506 IRQ_TYPE_LEVEL_HIGH>, 2732 <GIC_SPI 560 IRQ_TYPE_LEVEL_HIGH>; 2733 interrupt-names = "uplow", 2734 "critical"; 2735 2736 #qcom,sensors = <13>; 2737 2738 #thermal-sensor-cells = <1>; 2739 }; 2740 2741 tsens1: thermal-sensor@c229000 { 2742 compatible = "qcom,eliza-tsens", "qcom,tsens-v2"; 2743 reg = <0x0 0x0c229000 0x0 0x1000>, 2744 <0x0 0x0c223000 0x0 0x1000>; 2745 2746 interrupts = <GIC_SPI 507 IRQ_TYPE_LEVEL_HIGH>, 2747 <GIC_SPI 561 IRQ_TYPE_LEVEL_HIGH>; 2748 interrupt-names = "uplow", 2749 "critical"; 2750 2751 #qcom,sensors = <14>; 2752 2753 #thermal-sensor-cells = <1>; 2754 }; 2755 2756 tsens2: thermal-sensor@c22a000 { 2757 compatible = "qcom,eliza-tsens", "qcom,tsens-v2"; 2758 reg = <0x0 0x0c22a000 0x0 0x1000>, 2759 <0x0 0x0c224000 0x0 0x1000>; 2760 2761 interrupts = <GIC_SPI 508 IRQ_TYPE_LEVEL_HIGH>, 2762 <GIC_SPI 562 IRQ_TYPE_LEVEL_HIGH>; 2763 interrupt-names = "uplow", 2764 "critical"; 2765 2766 #qcom,sensors = <5>; 2767 2768 #thermal-sensor-cells = <1>; 2769 }; 2770 2771 aoss_qmp: power-management@c300000 { 2772 compatible = "qcom,eliza-aoss-qmp", "qcom,aoss-qmp"; 2773 reg = <0x0 0x0c300000 0x0 0x400>; 2774 2775 interrupts-extended = <&ipcc IPCC_CLIENT_AOP IPCC_MPROC_SIGNAL_GLINK_QMP 2776 IRQ_TYPE_EDGE_RISING>; 2777 2778 mboxes = <&ipcc IPCC_CLIENT_AOP IPCC_MPROC_SIGNAL_GLINK_QMP>; 2779 2780 #clock-cells = <0>; 2781 }; 2782 2783 spmi: arbiter@c400000 { 2784 compatible = "qcom,eliza-spmi-pmic-arb", 2785 "qcom,x1e80100-spmi-pmic-arb"; 2786 reg = <0x0 0x0c400000 0x0 0x3000>, 2787 <0x0 0x0c500000 0x0 0x400000>, 2788 <0x0 0x0c440000 0x0 0x80000>; 2789 reg-names = "core", 2790 "chnls", 2791 "obsrvr"; 2792 2793 qcom,ee = <0>; 2794 qcom,channel = <0>; 2795 2796 #address-cells = <2>; 2797 #size-cells = <2>; 2798 ranges; 2799 2800 spmi_bus0: spmi@c42d000 { 2801 reg = <0x0 0x0c42d000 0x0 0x4000>, 2802 <0x0 0x0c4c0000 0x0 0x10000>; 2803 reg-names = "cnfg", 2804 "intr"; 2805 2806 interrupt-names = "periph_irq"; 2807 interrupts-extended = <&pdc 1 IRQ_TYPE_LEVEL_HIGH>; 2808 interrupt-controller; 2809 #interrupt-cells = <4>; 2810 2811 #address-cells = <2>; 2812 #size-cells = <0>; 2813 }; 2814 2815 spmi_bus1: spmi@c432000 { 2816 reg = <0x0 0x0c432000 0x0 0x4000>, 2817 <0x0 0x0c4d0000 0x0 0x10000>; 2818 reg-names = "cnfg", 2819 "intr"; 2820 2821 interrupt-names = "periph_irq"; 2822 interrupts-extended = <&pdc 3 IRQ_TYPE_LEVEL_HIGH>; 2823 interrupt-controller; 2824 #interrupt-cells = <4>; 2825 2826 #address-cells = <2>; 2827 #size-cells = <0>; 2828 }; 2829 }; 2830 2831 tlmm: pinctrl@f100000 { 2832 compatible = "qcom,eliza-tlmm"; 2833 reg = <0x0 0x0f100000 0x0 0xf00000>; 2834 2835 interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>; 2836 2837 gpio-controller; 2838 #gpio-cells = <2>; 2839 2840 interrupt-controller; 2841 #interrupt-cells = <2>; 2842 2843 gpio-ranges = <&tlmm 0 0 184>; 2844 wakeup-parent = <&pdc>; 2845 2846 qup_i2c0_data_clk: qup-i2c0-data-clk-state { 2847 pins = "gpio28", "gpio29"; 2848 function = "qup1_se0"; 2849 drive-strength = <2>; 2850 bias-pull-up; 2851 }; 2852 2853 qup_spi0_cs: qup-spi0-cs-state { 2854 pins = "gpio31"; 2855 function = "qup1_se0"; 2856 drive-strength = <6>; 2857 bias-disable; 2858 }; 2859 2860 qup_spi0_data_clk: qup-spi0-data-clk-state { 2861 /* MISO, MOSI, CLK */ 2862 pins = "gpio28", "gpio29", "gpio30"; 2863 function = "qup1_se0"; 2864 drive-strength = <6>; 2865 bias-disable; 2866 }; 2867 2868 qup_i2c1_data_clk: qup-i2c1-data-clk-state { 2869 pins = "gpio32", "gpio33"; 2870 function = "qup1_se1"; 2871 drive-strength = <2>; 2872 bias-pull-up; 2873 }; 2874 2875 qup_spi1_cs: qup-spi1-cs-state { 2876 pins = "gpio35"; 2877 function = "qup1_se1"; 2878 drive-strength = <6>; 2879 bias-disable; 2880 }; 2881 2882 qup_spi1_data_clk: qup-spi1-data-clk-state { 2883 /* MISO, MOSI, CLK */ 2884 pins = "gpio32", "gpio33", "gpio34"; 2885 function = "qup1_se1"; 2886 drive-strength = <6>; 2887 bias-disable; 2888 }; 2889 2890 qup_i2c2_data_clk: qup-i2c2-data-clk-state { 2891 pins = "gpio52", "gpio53"; 2892 function = "qup1_se2"; 2893 drive-strength = <2>; 2894 bias-pull-up; 2895 }; 2896 2897 qup_spi2_cs: qup-spi2-cs-state { 2898 pins = "gpio55"; 2899 function = "qup1_se2"; 2900 drive-strength = <6>; 2901 bias-disable; 2902 }; 2903 2904 qup_spi2_data_clk: qup-spi2-data-clk-state { 2905 /* MISO, MOSI, CLK */ 2906 pins = "gpio52", "gpio53", "gpio54"; 2907 function = "qup1_se2"; 2908 drive-strength = <6>; 2909 bias-disable; 2910 }; 2911 2912 qup_i2c3_data_clk: qup-i2c3-data-clk-state { 2913 pins = "gpio44", "gpio45"; 2914 function = "qup1_se3"; 2915 drive-strength = <2>; 2916 bias-pull-up; 2917 }; 2918 2919 qup_spi3_cs: qup-spi3-cs-state { 2920 pins = "gpio47"; 2921 function = "qup1_se3"; 2922 drive-strength = <6>; 2923 bias-disable; 2924 }; 2925 2926 qup_spi3_data_clk: qup-spi3-data-clk-state { 2927 /* MISO, MOSI, CLK */ 2928 pins = "gpio44", "gpio45", "gpio46"; 2929 function = "qup1_se3"; 2930 drive-strength = <6>; 2931 bias-disable; 2932 }; 2933 2934 qup_i2c4_data_clk: qup-i2c4-data-clk-state { 2935 pins = "gpio36", "gpio37"; 2936 function = "qup1_se4_01"; 2937 drive-strength = <2>; 2938 bias-pull-up; 2939 }; 2940 2941 qup_spi4_clk: qup-spi4-clk-state { 2942 pins = "gpio37"; 2943 function = "qup1_se4_23"; 2944 drive-strength = <6>; 2945 bias-disable; 2946 }; 2947 2948 qup_spi4_cs: qup-spi4-cs-state { 2949 pins = "gpio36"; 2950 function = "qup1_se4_23"; 2951 drive-strength = <6>; 2952 bias-disable; 2953 }; 2954 2955 qup_spi4_data: qup-spi4-data-state { 2956 pins = "gpio36", "gpio37"; 2957 function = "qup1_se4_01"; 2958 drive-strength = <6>; 2959 bias-disable; 2960 }; 2961 2962 qup_uart5_default: qup-uart5-default-state { 2963 /* TX, RX */ 2964 pins = "gpio134", "gpio135"; 2965 function = "qup1_se5"; 2966 drive-strength = <2>; 2967 bias-pull-up; 2968 }; 2969 2970 qup_uart5_cts_rts: qup-uart5-cts-rts-state { 2971 /* CTS, RTS */ 2972 pins = "gpio132", "gpio133"; 2973 function = "qup1_se5"; 2974 drive-strength = <2>; 2975 bias-pull-down; 2976 }; 2977 2978 qup_uart6_default: qup-uart6-default-state { 2979 /* TX, RX */ 2980 pins = "gpio42", "gpio40"; 2981 function = "qup1_se6"; 2982 drive-strength = <2>; 2983 bias-pull-up; 2984 }; 2985 2986 qup_uart6_cts_rts: qup-uart6-cts-rts-state { 2987 /* CTS, RTS */ 2988 pins = "gpio40", "gpio42"; 2989 function = "qup1_se6"; 2990 drive-strength = <2>; 2991 bias-pull-down; 2992 }; 2993 2994 qup_i2c7_data_clk: qup-i2c7-data-clk-state { 2995 pins = "gpio81", "gpio80"; 2996 function = "qup1_se7"; 2997 drive-strength = <2>; 2998 bias-pull-up; 2999 }; 3000 3001 qup_spi7_cs: qup-spi7-cs-state { 3002 pins = "gpio78"; 3003 function = "qup1_se7"; 3004 drive-strength = <6>; 3005 bias-disable; 3006 }; 3007 3008 qup_spi7_data_clk: qup-spi7-data-clk-state { 3009 pins = "gpio81", "gpio80", "gpio114"; 3010 function = "qup1_se7"; 3011 drive-strength = <6>; 3012 bias-disable; 3013 }; 3014 3015 qup_i2c8_data_clk: qup-i2c8-data-clk-state { 3016 pins = "gpio0", "gpio1"; 3017 function = "qup2_se0"; 3018 drive-strength = <2>; 3019 bias-pull-up; 3020 }; 3021 3022 qup_spi8_cs: qup-spi8-cs-state { 3023 pins = "gpio3"; 3024 function = "qup2_se0"; 3025 drive-strength = <6>; 3026 bias-disable; 3027 }; 3028 3029 qup_spi8_data_clk: qup-spi8-data-clk-state { 3030 pins = "gpio0", "gpio1", "gpio2"; 3031 function = "qup2_se0"; 3032 drive-strength = <6>; 3033 bias-disable; 3034 }; 3035 3036 qup_i2c9_data_clk: qup-i2c9-data-clk-state { 3037 pins = "gpio4", "gpio5"; 3038 function = "qup2_se1"; 3039 drive-strength = <2>; 3040 bias-pull-up; 3041 }; 3042 3043 qup_spi9_cs: qup-spi9-cs-state { 3044 pins = "gpio7"; 3045 function = "qup2_se1"; 3046 drive-strength = <6>; 3047 bias-disable; 3048 }; 3049 3050 qup_spi9_data_clk: qup-spi9-data-clk-state { 3051 pins = "gpio4", "gpio5", "gpio6"; 3052 function = "qup2_se1"; 3053 drive-strength = <6>; 3054 bias-disable; 3055 }; 3056 3057 qup_i2c10_data_clk: qup-i2c10-data-clk-state { 3058 pins = "gpio8", "gpio9"; 3059 function = "qup2_se2"; 3060 drive-strength = <2>; 3061 bias-pull-up; 3062 }; 3063 3064 qup_spi10_cs: qup-spi10-cs-state { 3065 pins = "gpio11"; 3066 function = "qup2_se2"; 3067 drive-strength = <6>; 3068 bias-disable; 3069 }; 3070 3071 qup_spi10_data_clk: qup-spi10-data-clk-state { 3072 pins = "gpio8", "gpio9", "gpio10"; 3073 function = "qup2_se2"; 3074 drive-strength = <6>; 3075 bias-disable; 3076 }; 3077 3078 qup_i2c11_data_clk: qup-i2c11-data-clk-state { 3079 pins = "gpio79", "gpio97"; 3080 function = "qup2_se3"; 3081 drive-strength = <2>; 3082 bias-pull-up; 3083 }; 3084 3085 qup_spi11_cs: qup-spi11-cs-state { 3086 pins = "gpio116"; 3087 function = "qup2_se3"; 3088 drive-strength = <6>; 3089 bias-disable; 3090 }; 3091 3092 qup_spi11_data_clk: qup-spi11-data-clk-state { 3093 pins = "gpio79", "gpio97", "gpio100"; 3094 function = "qup2_se3"; 3095 drive-strength = <6>; 3096 bias-disable; 3097 }; 3098 3099 qup_i2c12_data_clk: qup-i2c12-data-clk-state { 3100 pins = "gpio12", "gpio13"; 3101 function = "qup2_se4"; 3102 drive-strength = <2>; 3103 bias-pull-up; 3104 }; 3105 3106 qup_spi12_cs: qup-spi12-cs-state { 3107 pins = "gpio27"; 3108 function = "qup2_se4"; 3109 drive-strength = <6>; 3110 bias-disable; 3111 }; 3112 3113 qup_spi12_data_clk: qup-spi12-data-clk-state { 3114 pins = "gpio12", "gpio13", "gpio26"; 3115 function = "qup2_se4"; 3116 drive-strength = <6>; 3117 bias-disable; 3118 }; 3119 3120 qup_uart13_default: qup-uart13-default-state { 3121 /* TX, RX */ 3122 pins = "gpio18", "gpio19"; 3123 function = "qup2_se5"; 3124 drive-strength = <2>; 3125 bias-pull-up; 3126 }; 3127 3128 qup_i2c14_data_clk: qup-i2c14-data-clk-state { 3129 pins = "gpio20", "gpio21"; 3130 function = "qup2_se6"; 3131 drive-strength = <2>; 3132 bias-pull-up; 3133 }; 3134 3135 qup_spi14_cs: qup-spi14-cs-state { 3136 pins = "gpio23"; 3137 function = "qup2_se6"; 3138 drive-strength = <6>; 3139 bias-disable; 3140 }; 3141 3142 qup_spi14_data_clk: qup-spi14-data-clk-state { 3143 /* MISO, MOSI, CLK */ 3144 pins = "gpio20", "gpio21", "gpio22"; 3145 function = "qup2_se6"; 3146 drive-strength = <6>; 3147 bias-disable; 3148 }; 3149 3150 qup_i2c15_data_clk: qup-i2c15-data-clk-state { 3151 pins = "gpio27", "gpio26"; 3152 function = "qup2_se7"; 3153 drive-strength = <2>; 3154 bias-pull-up; 3155 }; 3156 3157 qup_spi15_cs: qup-spi15-cs-state { 3158 pins = "gpio12"; 3159 function = "qup2_se7"; 3160 drive-strength = <6>; 3161 bias-disable; 3162 }; 3163 3164 qup_spi15_data_clk: qup-spi15-data-clk-state { 3165 /* MISO, MOSI, CLK */ 3166 pins = "gpio27", "gpio26", "gpio13"; 3167 function = "qup2_se7"; 3168 drive-strength = <6>; 3169 bias-disable; 3170 }; 3171 3172 sdc1_default: sdc1-default-state { 3173 clk-pins { 3174 pins = "gpio121"; 3175 function = "sdc1"; 3176 drive-strength = <12>; 3177 bias-disable; 3178 }; 3179 3180 cmd-pins { 3181 pins = "gpio123"; 3182 function = "sdc1"; 3183 drive-strength = <12>; 3184 bias-pull-up; 3185 }; 3186 3187 data-pins { 3188 pins = "gpio124", "gpio125", 3189 "gpio126", "gpio127", 3190 "gpio128", "gpio129", 3191 "gpio130", "gpio131"; 3192 function = "sdc1"; 3193 drive-strength = <12>; 3194 bias-pull-up; 3195 }; 3196 3197 rclk-pins { 3198 pins = "gpio120"; 3199 function = "sdc1"; 3200 bias-pull-down; 3201 }; 3202 }; 3203 3204 sdc1_sleep: sdc1-sleep-state { 3205 clk-pins { 3206 pins = "gpio121"; 3207 function = "sdc1"; 3208 drive-strength = <2>; 3209 bias-disable; 3210 }; 3211 3212 cmd-pins { 3213 pins = "gpio123"; 3214 function = "sdc1"; 3215 drive-strength = <2>; 3216 bias-pull-up; 3217 }; 3218 3219 data-pins { 3220 pins = "gpio124", "gpio125", 3221 "gpio126", "gpio127", 3222 "gpio128", "gpio129", 3223 "gpio130", "gpio131"; 3224 function = "sdc1"; 3225 drive-strength = <2>; 3226 bias-pull-up; 3227 }; 3228 3229 rclk-pins { 3230 pins = "gpio120"; 3231 function = "sdc1"; 3232 bias-pull-down; 3233 }; 3234 }; 3235 3236 sdc2_default: sdc2-default-state { 3237 clk-pins { 3238 pins = "gpio62"; 3239 function = "sdc2"; 3240 drive-strength = <16>; 3241 bias-disable; 3242 }; 3243 3244 cmd-pins { 3245 pins = "gpio51"; 3246 function = "sdc2"; 3247 drive-strength = <10>; 3248 bias-pull-up; 3249 }; 3250 3251 data-pins { 3252 pins = "gpio38", "gpio39", 3253 "gpio48", "gpio49"; 3254 function = "sdc2"; 3255 drive-strength = <10>; 3256 bias-pull-up; 3257 }; 3258 }; 3259 3260 sdc2_sleep: sdc2-sleep-state { 3261 clk-pins { 3262 pins = "gpio62"; 3263 function = "sdc2"; 3264 drive-strength = <2>; 3265 bias-disable; 3266 }; 3267 3268 cmd-pins { 3269 pins = "gpio51"; 3270 function = "sdc2"; 3271 drive-strength = <2>; 3272 bias-pull-up; 3273 }; 3274 3275 data-pins { 3276 pins = "gpio38", "gpio39", 3277 "gpio48", "gpio49"; 3278 function = "sdc2"; 3279 drive-strength = <2>; 3280 bias-pull-up; 3281 }; 3282 }; 3283 }; 3284 3285 sram@14680000 { 3286 compatible = "qcom,eliza-imem", "mmio-sram"; 3287 reg = <0x0 0x14680000 0x0 0x2c000>; 3288 ranges = <0x0 0x0 0x14680000 0x2c000>; 3289 3290 no-memory-wc; 3291 3292 #address-cells = <1>; 3293 #size-cells = <1>; 3294 3295 pil-reloc-sram@94c { 3296 compatible = "qcom,pil-reloc-info"; 3297 reg = <0x94c 0xc8>; 3298 }; 3299 3300 ipa_modem_tables: modem-tables-sram@3000 { 3301 reg = <0x3000 0x2000>; 3302 }; 3303 }; 3304 3305 apps_smmu: iommu@15000000 { 3306 compatible = "qcom,eliza-smmu-500", "qcom,smmu-500", "arm,mmu-500"; 3307 reg = <0x0 0x15000000 0x0 0x100000>; 3308 3309 interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>, 3310 <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>, 3311 <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>, 3312 <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>, 3313 <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>, 3314 <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>, 3315 <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>, 3316 <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>, 3317 <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>, 3318 <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>, 3319 <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>, 3320 <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>, 3321 <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>, 3322 <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>, 3323 <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>, 3324 <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>, 3325 <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>, 3326 <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>, 3327 <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>, 3328 <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>, 3329 <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>, 3330 <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>, 3331 <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>, 3332 <GIC_SPI 181 IRQ_TYPE_LEVEL_HIGH>, 3333 <GIC_SPI 182 IRQ_TYPE_LEVEL_HIGH>, 3334 <GIC_SPI 183 IRQ_TYPE_LEVEL_HIGH>, 3335 <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>, 3336 <GIC_SPI 185 IRQ_TYPE_LEVEL_HIGH>, 3337 <GIC_SPI 186 IRQ_TYPE_LEVEL_HIGH>, 3338 <GIC_SPI 187 IRQ_TYPE_LEVEL_HIGH>, 3339 <GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>, 3340 <GIC_SPI 189 IRQ_TYPE_LEVEL_HIGH>, 3341 <GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>, 3342 <GIC_SPI 191 IRQ_TYPE_LEVEL_HIGH>, 3343 <GIC_SPI 192 IRQ_TYPE_LEVEL_HIGH>, 3344 <GIC_SPI 315 IRQ_TYPE_LEVEL_HIGH>, 3345 <GIC_SPI 316 IRQ_TYPE_LEVEL_HIGH>, 3346 <GIC_SPI 317 IRQ_TYPE_LEVEL_HIGH>, 3347 <GIC_SPI 318 IRQ_TYPE_LEVEL_HIGH>, 3348 <GIC_SPI 319 IRQ_TYPE_LEVEL_HIGH>, 3349 <GIC_SPI 320 IRQ_TYPE_LEVEL_HIGH>, 3350 <GIC_SPI 321 IRQ_TYPE_LEVEL_HIGH>, 3351 <GIC_SPI 322 IRQ_TYPE_LEVEL_HIGH>, 3352 <GIC_SPI 323 IRQ_TYPE_LEVEL_HIGH>, 3353 <GIC_SPI 324 IRQ_TYPE_LEVEL_HIGH>, 3354 <GIC_SPI 325 IRQ_TYPE_LEVEL_HIGH>, 3355 <GIC_SPI 326 IRQ_TYPE_LEVEL_HIGH>, 3356 <GIC_SPI 327 IRQ_TYPE_LEVEL_HIGH>, 3357 <GIC_SPI 328 IRQ_TYPE_LEVEL_HIGH>, 3358 <GIC_SPI 329 IRQ_TYPE_LEVEL_HIGH>, 3359 <GIC_SPI 330 IRQ_TYPE_LEVEL_HIGH>, 3360 <GIC_SPI 331 IRQ_TYPE_LEVEL_HIGH>, 3361 <GIC_SPI 332 IRQ_TYPE_LEVEL_HIGH>, 3362 <GIC_SPI 333 IRQ_TYPE_LEVEL_HIGH>, 3363 <GIC_SPI 334 IRQ_TYPE_LEVEL_HIGH>, 3364 <GIC_SPI 335 IRQ_TYPE_LEVEL_HIGH>, 3365 <GIC_SPI 336 IRQ_TYPE_LEVEL_HIGH>, 3366 <GIC_SPI 337 IRQ_TYPE_LEVEL_HIGH>, 3367 <GIC_SPI 338 IRQ_TYPE_LEVEL_HIGH>, 3368 <GIC_SPI 339 IRQ_TYPE_LEVEL_HIGH>, 3369 <GIC_SPI 340 IRQ_TYPE_LEVEL_HIGH>, 3370 <GIC_SPI 341 IRQ_TYPE_LEVEL_HIGH>, 3371 <GIC_SPI 342 IRQ_TYPE_LEVEL_HIGH>, 3372 <GIC_SPI 343 IRQ_TYPE_LEVEL_HIGH>, 3373 <GIC_SPI 344 IRQ_TYPE_LEVEL_HIGH>, 3374 <GIC_SPI 345 IRQ_TYPE_LEVEL_HIGH>, 3375 <GIC_SPI 395 IRQ_TYPE_LEVEL_HIGH>, 3376 <GIC_SPI 396 IRQ_TYPE_LEVEL_HIGH>, 3377 <GIC_SPI 397 IRQ_TYPE_LEVEL_HIGH>, 3378 <GIC_SPI 398 IRQ_TYPE_LEVEL_HIGH>, 3379 <GIC_SPI 399 IRQ_TYPE_LEVEL_HIGH>, 3380 <GIC_SPI 400 IRQ_TYPE_LEVEL_HIGH>, 3381 <GIC_SPI 401 IRQ_TYPE_LEVEL_HIGH>, 3382 <GIC_SPI 402 IRQ_TYPE_LEVEL_HIGH>, 3383 <GIC_SPI 403 IRQ_TYPE_LEVEL_HIGH>, 3384 <GIC_SPI 404 IRQ_TYPE_LEVEL_HIGH>, 3385 <GIC_SPI 405 IRQ_TYPE_LEVEL_HIGH>, 3386 <GIC_SPI 406 IRQ_TYPE_LEVEL_HIGH>, 3387 <GIC_SPI 407 IRQ_TYPE_LEVEL_HIGH>, 3388 <GIC_SPI 408 IRQ_TYPE_LEVEL_HIGH>, 3389 <GIC_SPI 409 IRQ_TYPE_LEVEL_HIGH>, 3390 <GIC_SPI 418 IRQ_TYPE_LEVEL_HIGH>, 3391 <GIC_SPI 419 IRQ_TYPE_LEVEL_HIGH>, 3392 <GIC_SPI 412 IRQ_TYPE_LEVEL_HIGH>, 3393 <GIC_SPI 421 IRQ_TYPE_LEVEL_HIGH>, 3394 <GIC_SPI 707 IRQ_TYPE_LEVEL_HIGH>, 3395 <GIC_SPI 423 IRQ_TYPE_LEVEL_HIGH>, 3396 <GIC_SPI 424 IRQ_TYPE_LEVEL_HIGH>, 3397 <GIC_SPI 425 IRQ_TYPE_LEVEL_HIGH>, 3398 <GIC_SPI 690 IRQ_TYPE_LEVEL_HIGH>, 3399 <GIC_SPI 691 IRQ_TYPE_LEVEL_HIGH>, 3400 <GIC_SPI 692 IRQ_TYPE_LEVEL_HIGH>, 3401 <GIC_SPI 693 IRQ_TYPE_LEVEL_HIGH>, 3402 <GIC_SPI 694 IRQ_TYPE_LEVEL_HIGH>, 3403 <GIC_SPI 695 IRQ_TYPE_LEVEL_HIGH>, 3404 <GIC_SPI 696 IRQ_TYPE_LEVEL_HIGH>, 3405 <GIC_SPI 697 IRQ_TYPE_LEVEL_HIGH>, 3406 <GIC_SPI 410 IRQ_TYPE_LEVEL_HIGH>, 3407 <GIC_SPI 488 IRQ_TYPE_LEVEL_HIGH>, 3408 <GIC_SPI 489 IRQ_TYPE_LEVEL_HIGH>, 3409 <GIC_SPI 490 IRQ_TYPE_LEVEL_HIGH>, 3410 <GIC_SPI 491 IRQ_TYPE_LEVEL_HIGH>, 3411 <GIC_SPI 492 IRQ_TYPE_LEVEL_HIGH>, 3412 <GIC_SPI 493 IRQ_TYPE_LEVEL_HIGH>, 3413 <GIC_SPI 494 IRQ_TYPE_LEVEL_HIGH>, 3414 <GIC_SPI 495 IRQ_TYPE_LEVEL_HIGH>, 3415 <GIC_SPI 496 IRQ_TYPE_LEVEL_HIGH>, 3416 <GIC_SPI 497 IRQ_TYPE_LEVEL_HIGH>, 3417 <GIC_SPI 498 IRQ_TYPE_LEVEL_HIGH>, 3418 <GIC_SPI 499 IRQ_TYPE_LEVEL_HIGH>, 3419 <GIC_SPI 500 IRQ_TYPE_LEVEL_HIGH>, 3420 <GIC_SPI 501 IRQ_TYPE_LEVEL_HIGH>, 3421 <GIC_SPI 502 IRQ_TYPE_LEVEL_HIGH>; 3422 3423 #iommu-cells = <2>; 3424 #global-interrupts = <1>; 3425 3426 dma-coherent; 3427 }; 3428 3429 intc: interrupt-controller@17100000 { 3430 compatible = "arm,gic-v3"; 3431 reg = <0x0 0x17100000 0x0 0x10000>, 3432 <0x0 0x17180000 0x0 0x200000>; 3433 3434 interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>; 3435 3436 #interrupt-cells = <3>; 3437 interrupt-controller; 3438 3439 #redistributor-regions = <1>; 3440 redistributor-stride = <0x0 0x40000>; 3441 3442 #address-cells = <2>; 3443 #size-cells = <2>; 3444 ranges; 3445 3446 gic_its: msi-controller@17140000 { 3447 compatible = "arm,gic-v3-its"; 3448 reg = <0x0 0x17140000 0x0 0x40000>; 3449 3450 msi-controller; 3451 #msi-cells = <1>; 3452 }; 3453 }; 3454 3455 apps_rsc: rsc@17a00000 { 3456 compatible = "qcom,rpmh-rsc"; 3457 reg = <0x0 0x17a00000 0x0 0x10000>, 3458 <0x0 0x17a10000 0x0 0x10000>, 3459 <0x0 0x17a20000 0x0 0x10000>; 3460 reg-names = "drv-0", 3461 "drv-1", 3462 "drv-2"; 3463 3464 interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>, 3465 <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>, 3466 <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>; 3467 3468 power-domains = <&cluster_pd>; 3469 label = "apps_rsc"; 3470 3471 qcom,tcs-offset = <0xd00>; 3472 qcom,drv-id = <2>; 3473 qcom,tcs-config = <ACTIVE_TCS 3>, 3474 <SLEEP_TCS 2>, 3475 <WAKE_TCS 2>, 3476 <CONTROL_TCS 0>; 3477 3478 apps_bcm_voter: bcm-voter { 3479 compatible = "qcom,bcm-voter"; 3480 }; 3481 3482 rpmhcc: clock-controller { 3483 compatible = "qcom,eliza-rpmh-clk"; 3484 #clock-cells = <1>; 3485 clocks = <&xo_board>; 3486 clock-names = "xo"; 3487 }; 3488 3489 rpmhpd: power-controller { 3490 compatible = "qcom,eliza-rpmhpd"; 3491 3492 operating-points-v2 = <&rpmhpd_opp_table>; 3493 3494 #power-domain-cells = <1>; 3495 3496 rpmhpd_opp_table: opp-table { 3497 compatible = "operating-points-v2"; 3498 3499 rpmhpd_opp_ret: opp-16 { 3500 opp-level = <RPMH_REGULATOR_LEVEL_RETENTION>; 3501 }; 3502 3503 rpmhpd_opp_min_svs: opp-48 { 3504 opp-level = <RPMH_REGULATOR_LEVEL_MIN_SVS>; 3505 }; 3506 3507 rpmhpd_opp_low_svs_d3: opp-50 { 3508 opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS_D3>; 3509 }; 3510 3511 rpmhpd_opp_low_svs_d2: opp-52 { 3512 opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS_D2>; 3513 }; 3514 3515 rpmhpd_opp_low_svs_d1: opp-56 { 3516 opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS_D1>; 3517 }; 3518 3519 rpmhpd_opp_low_svs_d0: opp-60 { 3520 opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS_D0>; 3521 }; 3522 3523 rpmhpd_opp_low_svs: opp-64 { 3524 opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS>; 3525 }; 3526 3527 rpmhpd_opp_low_svs_l1: opp-80 { 3528 opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS_L1>; 3529 }; 3530 3531 rpmhpd_opp_svs: opp-128 { 3532 opp-level = <RPMH_REGULATOR_LEVEL_SVS>; 3533 }; 3534 3535 rpmhpd_opp_svs_l0: opp-144 { 3536 opp-level = <RPMH_REGULATOR_LEVEL_SVS_L0>; 3537 }; 3538 3539 rpmhpd_opp_svs_l1: opp-192 { 3540 opp-level = <RPMH_REGULATOR_LEVEL_SVS_L1>; 3541 }; 3542 3543 rpmhpd_opp_svs_l2: opp-224 { 3544 opp-level = <RPMH_REGULATOR_LEVEL_SVS_L2>; 3545 }; 3546 3547 rpmhpd_opp_nom: opp-256 { 3548 opp-level = <RPMH_REGULATOR_LEVEL_NOM>; 3549 }; 3550 3551 rpmhpd_opp_nom_l1: opp-320 { 3552 opp-level = <RPMH_REGULATOR_LEVEL_NOM_L1>; 3553 }; 3554 3555 rpmhpd_opp_nom_l2: opp-336 { 3556 opp-level = <RPMH_REGULATOR_LEVEL_NOM_L2>; 3557 }; 3558 3559 rpmhpd_opp_turbo: opp-384 { 3560 opp-level = <RPMH_REGULATOR_LEVEL_TURBO>; 3561 }; 3562 3563 rpmhpd_opp_turbo_l1: opp-416 { 3564 opp-level = <RPMH_REGULATOR_LEVEL_TURBO_L1>; 3565 }; 3566 3567 rpmhpd_opp_turbo_l2: opp-432 { 3568 opp-level = <RPMH_REGULATOR_LEVEL_TURBO_L2>; 3569 }; 3570 3571 rpmhpd_opp_turbo_l3: opp-448 { 3572 opp-level = <RPMH_REGULATOR_LEVEL_TURBO_L3>; 3573 }; 3574 3575 rpmhpd_opp_turbo_l4: opp-452 { 3576 opp-level = <RPMH_REGULATOR_LEVEL_TURBO_L4>; 3577 }; 3578 3579 rpmhpd_opp_super_turbo_no_cpr: opp-480 { 3580 opp-level = <RPMH_REGULATOR_LEVEL_SUPER_TURBO_NO_CPR>; 3581 }; 3582 }; 3583 }; 3584 }; 3585 3586 epss_l3: interconnect@17d90000 { 3587 compatible = "qcom,eliza-epss-l3", "qcom,epss-l3"; 3588 reg = <0x0 0x17d90000 0x0 0x1000>; 3589 3590 clocks = <&bi_tcxo_div2>, <&gcc GCC_GPLL0>; 3591 clock-names = "xo", "alternate"; 3592 3593 #interconnect-cells = <1>; 3594 }; 3595 3596 cpufreq_hw: cpufreq@17d91000 { 3597 compatible = "qcom,eliza-cpufreq-epss", "qcom,cpufreq-epss"; 3598 reg = <0x0 0x17d91000 0x0 0x1000>, 3599 <0x0 0x17d92000 0x0 0x1000>, 3600 <0x0 0x17d93000 0x0 0x1000>; 3601 reg-names = "freq-domain0", 3602 "freq-domain1", 3603 "freq-domain2"; 3604 3605 interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>, 3606 <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>, 3607 <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>; 3608 interrupt-names = "dcvsh-irq-0", 3609 "dcvsh-irq-1", 3610 "dcvsh-irq-2"; 3611 3612 clocks = <&bi_tcxo_div2>, <&gcc GCC_GPLL0>; 3613 clock-names = "xo", "alternate"; 3614 3615 #freq-domain-cells = <1>; 3616 #clock-cells = <1>; 3617 }; 3618 3619 gem_noc: interconnect@24100000 { 3620 compatible = "qcom,eliza-gem-noc"; 3621 reg = <0x0 0x24100000 0x0 0x163080>; 3622 qcom,bcm-voters = <&apps_bcm_voter>; 3623 #interconnect-cells = <2>; 3624 }; 3625 3626 system-cache-controller@24800000 { 3627 compatible = "qcom,eliza-llcc"; 3628 reg = <0x0 0x24800000 0x0 0x200000>, 3629 <0x0 0x24c00000 0x0 0x200000>, 3630 <0x0 0x26800000 0x0 0x200000>, 3631 <0x0 0x26c00000 0x0 0x200000>; 3632 reg-names = "llcc0_base", 3633 "llcc2_base", 3634 "llcc_broadcast_base", 3635 "llcc_broadcast_and_base"; 3636 3637 interrupts = <GIC_SPI 266 IRQ_TYPE_LEVEL_HIGH>; 3638 }; 3639 3640 nsp_noc: interconnect@320c0000 { 3641 compatible = "qcom,eliza-nsp-noc"; 3642 reg = <0x0 0x320c0000 0x0 0xe080>; 3643 qcom,bcm-voters = <&apps_bcm_voter>; 3644 #interconnect-cells = <2>; 3645 }; 3646 }; 3647 3648 thermal-zones { 3649 aoss0-thermal { 3650 thermal-sensors = <&tsens0 0>; 3651 3652 trips { 3653 aoss-hot { 3654 temperature = <110000>; 3655 hysteresis = <1000>; 3656 type = "hot"; 3657 }; 3658 3659 aoss-critical { 3660 temperature = <115000>; 3661 hysteresis = <0>; 3662 type = "critical"; 3663 }; 3664 }; 3665 }; 3666 3667 aoss1-thermal { 3668 thermal-sensors = <&tsens1 0>; 3669 3670 trips { 3671 aoss-hot { 3672 temperature = <110000>; 3673 hysteresis = <1000>; 3674 type = "hot"; 3675 }; 3676 3677 aoss-critical { 3678 temperature = <115000>; 3679 hysteresis = <0>; 3680 type = "critical"; 3681 }; 3682 }; 3683 }; 3684 3685 aoss2-thermal { 3686 thermal-sensors = <&tsens2 0>; 3687 3688 trips { 3689 aoss-hot { 3690 temperature = <110000>; 3691 hysteresis = <1000>; 3692 type = "hot"; 3693 }; 3694 3695 aoss-critical { 3696 temperature = <115000>; 3697 hysteresis = <0>; 3698 type = "critical"; 3699 }; 3700 }; 3701 }; 3702 3703 camera0-thermal { 3704 thermal-sensors = <&tsens1 12>; 3705 3706 trips { 3707 camera-hot { 3708 temperature = <110000>; 3709 hysteresis = <1000>; 3710 type = "hot"; 3711 }; 3712 3713 camera-critical { 3714 temperature = <115000>; 3715 hysteresis = <0>; 3716 type = "critical"; 3717 }; 3718 }; 3719 }; 3720 3721 camera1-thermal { 3722 thermal-sensors = <&tsens1 13>; 3723 3724 trips { 3725 camera-hot { 3726 temperature = <110000>; 3727 hysteresis = <1000>; 3728 type = "hot"; 3729 }; 3730 3731 camera-critical { 3732 temperature = <115000>; 3733 hysteresis = <0>; 3734 type = "critical"; 3735 }; 3736 }; 3737 }; 3738 3739 cpu0-thermal { 3740 thermal-sensors = <&tsens1 1>; 3741 3742 trips { 3743 cpu-critical { 3744 temperature = <110000>; 3745 hysteresis = <1000>; 3746 type = "critical"; 3747 }; 3748 }; 3749 }; 3750 3751 cpu1-thermal { 3752 thermal-sensors = <&tsens1 2>; 3753 3754 trips { 3755 cpu-critical { 3756 temperature = <110000>; 3757 hysteresis = <1000>; 3758 type = "critical"; 3759 }; 3760 }; 3761 }; 3762 3763 cpu2-thermal { 3764 thermal-sensors = <&tsens1 3>; 3765 3766 trips { 3767 cpu-critical { 3768 temperature = <110000>; 3769 hysteresis = <1000>; 3770 type = "critical"; 3771 }; 3772 }; 3773 }; 3774 3775 cpu3-top-thermal { 3776 thermal-sensors = <&tsens0 3>; 3777 3778 trips { 3779 cpu-critical { 3780 temperature = <110000>; 3781 hysteresis = <1000>; 3782 type = "critical"; 3783 }; 3784 }; 3785 }; 3786 3787 cpu3-bottom-thermal { 3788 thermal-sensors = <&tsens0 4>; 3789 3790 trips { 3791 cpu-critical { 3792 temperature = <110000>; 3793 hysteresis = <1000>; 3794 type = "critical"; 3795 }; 3796 }; 3797 }; 3798 3799 cpu4-top-thermal { 3800 thermal-sensors = <&tsens0 5>; 3801 3802 trips { 3803 cpu-critical { 3804 temperature = <110000>; 3805 hysteresis = <1000>; 3806 type = "critical"; 3807 }; 3808 }; 3809 }; 3810 3811 cpu4-bottom-thermal { 3812 thermal-sensors = <&tsens0 6>; 3813 3814 trips { 3815 cpu-critical { 3816 temperature = <110000>; 3817 hysteresis = <1000>; 3818 type = "critical"; 3819 }; 3820 }; 3821 }; 3822 3823 cpu5-top-thermal { 3824 thermal-sensors = <&tsens0 7>; 3825 3826 trips { 3827 cpu-critical { 3828 temperature = <110000>; 3829 hysteresis = <1000>; 3830 type = "critical"; 3831 }; 3832 }; 3833 }; 3834 3835 cpu5-bottom-thermal { 3836 thermal-sensors = <&tsens0 8>; 3837 3838 trips { 3839 cpu-critical { 3840 temperature = <110000>; 3841 hysteresis = <1000>; 3842 type = "critical"; 3843 }; 3844 }; 3845 }; 3846 3847 cpu6-top-thermal { 3848 thermal-sensors = <&tsens0 9>; 3849 3850 trips { 3851 cpu-critical { 3852 temperature = <110000>; 3853 hysteresis = <1000>; 3854 type = "critical"; 3855 }; 3856 }; 3857 }; 3858 3859 cpu6-bottom-thermal { 3860 thermal-sensors = <&tsens0 10>; 3861 3862 trips { 3863 cpu-critical { 3864 temperature = <110000>; 3865 hysteresis = <1000>; 3866 type = "critical"; 3867 }; 3868 }; 3869 }; 3870 3871 cpu7-top-thermal { 3872 thermal-sensors = <&tsens0 11>; 3873 3874 trips { 3875 cpu-critical { 3876 temperature = <110000>; 3877 hysteresis = <1000>; 3878 type = "critical"; 3879 }; 3880 }; 3881 }; 3882 3883 cpu7-bottom-thermal { 3884 thermal-sensors = <&tsens0 12>; 3885 3886 trips { 3887 cpu-critical { 3888 temperature = <110000>; 3889 hysteresis = <1000>; 3890 type = "critical"; 3891 }; 3892 }; 3893 }; 3894 3895 cpuss0-thermal { 3896 thermal-sensors = <&tsens0 1>; 3897 3898 trips { 3899 cpuss-hot { 3900 temperature = <110000>; 3901 hysteresis = <1000>; 3902 type = "hot"; 3903 }; 3904 3905 cpuss-critical { 3906 temperature = <115000>; 3907 hysteresis = <0>; 3908 type = "critical"; 3909 }; 3910 }; 3911 }; 3912 3913 cpuss1-thermal { 3914 thermal-sensors = <&tsens0 2>; 3915 3916 trips { 3917 cpuss-hot { 3918 temperature = <110000>; 3919 hysteresis = <1000>; 3920 type = "hot"; 3921 }; 3922 3923 cpuss-critical { 3924 temperature = <115000>; 3925 hysteresis = <0>; 3926 type = "critical"; 3927 }; 3928 }; 3929 }; 3930 3931 ddr-thermal { 3932 thermal-sensors = <&tsens1 11>; 3933 3934 trips { 3935 ddr-hot { 3936 temperature = <110000>; 3937 hysteresis = <1000>; 3938 type = "hot"; 3939 }; 3940 3941 ddr-critical { 3942 temperature = <115000>; 3943 hysteresis = <0>; 3944 type = "critical"; 3945 }; 3946 }; 3947 }; 3948 3949 gpuss0-thermal { 3950 polling-delay-passive = <10>; 3951 3952 thermal-sensors = <&tsens1 8>; 3953 3954 trips { 3955 gpu-alert { 3956 temperature = <95000>; 3957 hysteresis = <1000>; 3958 type = "passive"; 3959 }; 3960 3961 gpu-hot { 3962 temperature = <110000>; 3963 hysteresis = <1000>; 3964 type = "hot"; 3965 }; 3966 3967 gpu-critical { 3968 temperature = <115000>; 3969 hysteresis = <0>; 3970 type = "critical"; 3971 }; 3972 }; 3973 }; 3974 3975 gpuss1-thermal { 3976 polling-delay-passive = <10>; 3977 3978 thermal-sensors = <&tsens1 9>; 3979 3980 trips { 3981 gpu-alert { 3982 temperature = <95000>; 3983 hysteresis = <1000>; 3984 type = "passive"; 3985 }; 3986 3987 gpu-hot { 3988 temperature = <110000>; 3989 hysteresis = <1000>; 3990 type = "hot"; 3991 }; 3992 3993 gpu-critical { 3994 temperature = <115000>; 3995 hysteresis = <0>; 3996 type = "critical"; 3997 }; 3998 }; 3999 }; 4000 4001 modem0-thermal { 4002 thermal-sensors = <&tsens2 1>; 4003 4004 trips { 4005 modem-hot { 4006 temperature = <110000>; 4007 hysteresis = <1000>; 4008 type = "hot"; 4009 }; 4010 4011 modem-critical { 4012 temperature = <115000>; 4013 hysteresis = <0>; 4014 type = "critical"; 4015 }; 4016 }; 4017 }; 4018 4019 modem1-thermal { 4020 thermal-sensors = <&tsens2 2>; 4021 4022 trips { 4023 modem-hot { 4024 temperature = <110000>; 4025 hysteresis = <1000>; 4026 type = "hot"; 4027 }; 4028 4029 modem-critical { 4030 temperature = <115000>; 4031 hysteresis = <0>; 4032 type = "critical"; 4033 }; 4034 }; 4035 }; 4036 4037 modem2-thermal { 4038 thermal-sensors = <&tsens2 3>; 4039 4040 trips { 4041 modem-hot { 4042 temperature = <110000>; 4043 hysteresis = <1000>; 4044 type = "hot"; 4045 }; 4046 4047 modem-critical { 4048 temperature = <115000>; 4049 hysteresis = <0>; 4050 type = "critical"; 4051 }; 4052 }; 4053 }; 4054 4055 modem3-thermal { 4056 thermal-sensors = <&tsens2 4>; 4057 4058 trips { 4059 modem-hot { 4060 temperature = <110000>; 4061 hysteresis = <1000>; 4062 type = "hot"; 4063 }; 4064 4065 modem-critical { 4066 temperature = <115000>; 4067 hysteresis = <0>; 4068 type = "critical"; 4069 }; 4070 }; 4071 }; 4072 4073 nsphmx0-thermal { 4074 thermal-sensors = <&tsens1 6>; 4075 4076 trips { 4077 nsphmx-hot { 4078 temperature = <110000>; 4079 hysteresis = <1000>; 4080 type = "hot"; 4081 }; 4082 4083 nsphmx-critical { 4084 temperature = <115000>; 4085 hysteresis = <0>; 4086 type = "critical"; 4087 }; 4088 }; 4089 }; 4090 4091 nsphmx1-thermal { 4092 thermal-sensors = <&tsens1 7>; 4093 4094 trips { 4095 nsphmx-hot { 4096 temperature = <110000>; 4097 hysteresis = <1000>; 4098 type = "hot"; 4099 }; 4100 4101 nsphmx-critical { 4102 temperature = <115000>; 4103 hysteresis = <0>; 4104 type = "critical"; 4105 }; 4106 }; 4107 }; 4108 4109 nsphvx0-thermal { 4110 thermal-sensors = <&tsens1 4>; 4111 4112 trips { 4113 nsphvx-hot { 4114 temperature = <110000>; 4115 hysteresis = <1000>; 4116 type = "hot"; 4117 }; 4118 4119 nsphvx-critical { 4120 temperature = <115000>; 4121 hysteresis = <0>; 4122 type = "critical"; 4123 }; 4124 }; 4125 }; 4126 4127 nsphvx1-thermal { 4128 thermal-sensors = <&tsens1 5>; 4129 4130 trips { 4131 nsphvx-hot { 4132 temperature = <110000>; 4133 hysteresis = <1000>; 4134 type = "hot"; 4135 }; 4136 4137 nsphvx-critical { 4138 temperature = <115000>; 4139 hysteresis = <0>; 4140 type = "critical"; 4141 }; 4142 }; 4143 }; 4144 4145 video-thermal { 4146 thermal-sensors = <&tsens1 10>; 4147 4148 trips { 4149 video-hot { 4150 temperature = <110000>; 4151 hysteresis = <1000>; 4152 type = "hot"; 4153 }; 4154 4155 video-critical { 4156 temperature = <115000>; 4157 hysteresis = <0>; 4158 type = "critical"; 4159 }; 4160 }; 4161 }; 4162 }; 4163 4164 timer { 4165 compatible = "arm,armv8-timer"; 4166 4167 interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_LOW>, 4168 <GIC_PPI 14 IRQ_TYPE_LEVEL_LOW>, 4169 <GIC_PPI 11 IRQ_TYPE_LEVEL_LOW>, 4170 <GIC_PPI 10 IRQ_TYPE_LEVEL_LOW>; 4171 }; 4172}; 4173