1 // SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause 2 /* 3 * Copyright (C) 2024-2026 Intel Corporation 4 */ 5 #include <linux/module.h> 6 #include <linux/stringify.h> 7 #include "iwl-config.h" 8 #include "iwl-prph.h" 9 #include "fw/api/txq.h" 10 11 /* Highest firmware core release supported */ 12 #define IWL_DR_UCODE_CORE_MAX 107 13 14 /* Lowest firmware core release supported */ 15 #define IWL_DR_UCODE_CORE_MIN 102 16 17 #define IWL_DR_A_PE_A_FW_PRE "iwlwifi-dr-a0-pe-a0" 18 19 static const struct iwl_family_base_params iwl_dr_base = { 20 .num_of_queues = 512, 21 .max_tfd_queue_size = 65536, 22 .wd_timeout = IWL_LONG_WD_TIMEOUT, 23 .shadow_reg_enable = true, 24 .pcie_l1_allowed = true, 25 .apmg_not_supported = true, 26 .mac_addr_from_csr = 0x30, 27 .d3_debug_data_base_addr = 0x401000, 28 .d3_debug_data_length = 60 * 1024, 29 .mon_smem_regs = { 30 .write_ptr = { 31 .addr = LDBG_M2S_BUF_WPTR, 32 .mask = LDBG_M2S_BUF_WPTR_VAL_MSK, 33 }, 34 .cycle_cnt = { 35 .addr = LDBG_M2S_BUF_WRAP_CNT, 36 .mask = LDBG_M2S_BUF_WRAP_CNT_VAL_MSK, 37 }, 38 }, 39 .min_txq_size = 128, 40 .gp2_reg_addr = 0xd02c68, 41 .min_ba_txq_size = IWL_DEFAULT_QUEUE_SIZE_EHT, 42 .mon_dram_regs = { 43 .write_ptr = { 44 .addr = DBGC_CUR_DBGBUF_STATUS, 45 .mask = DBGC_CUR_DBGBUF_STATUS_OFFSET_MSK, 46 }, 47 .cycle_cnt = { 48 .addr = DBGC_DBGBUF_WRAP_AROUND, 49 .mask = 0xffffffff, 50 }, 51 .cur_frag = { 52 .addr = DBGC_CUR_DBGBUF_STATUS, 53 .mask = DBGC_CUR_DBGBUF_STATUS_IDX_MSK, 54 }, 55 }, 56 .mon_dbgi_regs = { 57 .write_ptr = { 58 .addr = DBGI_SRAM_FIFO_POINTERS, 59 .mask = DBGI_SRAM_FIFO_POINTERS_WR_PTR_MSK, 60 }, 61 }, 62 .features = IWL_TX_CSUM_NETIF_FLAGS | NETIF_F_RXCSUM, 63 .ucode_api_max = ENCODE_CORE_AS_API(IWL_DR_UCODE_CORE_MAX), 64 .ucode_api_min = ENCODE_CORE_AS_API(IWL_DR_UCODE_CORE_MIN), 65 }; 66 67 const struct iwl_mac_cfg iwl_dr_mac_cfg = { 68 .device_family = IWL_DEVICE_FAMILY_DR, 69 .base = &iwl_dr_base, 70 .mq_rx_supported = true, 71 .gen2 = true, 72 .integrated = true, 73 .umac_prph_offset = 0x300000, 74 .xtal_latency = 12000, 75 .low_latency_xtal = true, 76 .ltr_delay = IWL_CFG_TRANS_LTR_DELAY_2500US, 77 }; 78 79 IWL_CORE_FW(IWL_DR_A_PE_A_FW_PRE, IWL_DR_UCODE_CORE_MAX); 80 81