1 /*
2 * Copyright 2012-15 Advanced Micro Devices, Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
21 *
22 * Authors: AMD
23 *
24 */
25
26 #include "dm_services.h"
27
28 #include "link_encoder.h"
29 #include "stream_encoder.h"
30
31 #include "resource.h"
32 #include "include/irq_service_interface.h"
33 #include "dce110/dce110_resource.h"
34 #include "dce110/dce110_timing_generator.h"
35
36 #include "irq/dce110/irq_service_dce110.h"
37 #include "dce/dce_mem_input.h"
38 #include "dce/dce_transform.h"
39 #include "dce/dce_link_encoder.h"
40 #include "dce/dce_stream_encoder.h"
41 #include "dce/dce_audio.h"
42 #include "dce/dce_opp.h"
43 #include "dce/dce_ipp.h"
44 #include "dce/dce_clock_source.h"
45
46 #include "dce/dce_hwseq.h"
47 #include "dce112/dce112_hwseq.h"
48 #include "dce/dce_abm.h"
49 #include "dce/dce_dmcu.h"
50 #include "dce/dce_aux.h"
51 #include "dce/dce_i2c.h"
52 #include "dce/dce_panel_cntl.h"
53
54 #include "reg_helper.h"
55
56 #include "dce/dce_11_2_d.h"
57 #include "dce/dce_11_2_sh_mask.h"
58
59 #include "dce100/dce100_resource.h"
60 #include "dce112_resource.h"
61
62 #define DC_LOGGER \
63 dc->ctx->logger
64
65 #ifndef mmDP_DPHY_INTERNAL_CTRL
66 #define mmDP_DPHY_INTERNAL_CTRL 0x4aa7
67 #define mmDP0_DP_DPHY_INTERNAL_CTRL 0x4aa7
68 #define mmDP1_DP_DPHY_INTERNAL_CTRL 0x4ba7
69 #define mmDP2_DP_DPHY_INTERNAL_CTRL 0x4ca7
70 #define mmDP3_DP_DPHY_INTERNAL_CTRL 0x4da7
71 #define mmDP4_DP_DPHY_INTERNAL_CTRL 0x4ea7
72 #define mmDP5_DP_DPHY_INTERNAL_CTRL 0x4fa7
73 #define mmDP6_DP_DPHY_INTERNAL_CTRL 0x54a7
74 #define mmDP7_DP_DPHY_INTERNAL_CTRL 0x56a7
75 #define mmDP8_DP_DPHY_INTERNAL_CTRL 0x57a7
76 #endif
77
78 #ifndef mmBIOS_SCRATCH_2
79 #define mmBIOS_SCRATCH_0 0x05C9
80 #define mmBIOS_SCRATCH_2 0x05CB
81 #define mmBIOS_SCRATCH_3 0x05CC
82 #define mmBIOS_SCRATCH_6 0x05CF
83 #endif
84
85 #ifndef mmDP_DPHY_BS_SR_SWAP_CNTL
86 #define mmDP_DPHY_BS_SR_SWAP_CNTL 0x4ADC
87 #define mmDP0_DP_DPHY_BS_SR_SWAP_CNTL 0x4ADC
88 #define mmDP1_DP_DPHY_BS_SR_SWAP_CNTL 0x4BDC
89 #define mmDP2_DP_DPHY_BS_SR_SWAP_CNTL 0x4CDC
90 #define mmDP3_DP_DPHY_BS_SR_SWAP_CNTL 0x4DDC
91 #define mmDP4_DP_DPHY_BS_SR_SWAP_CNTL 0x4EDC
92 #define mmDP5_DP_DPHY_BS_SR_SWAP_CNTL 0x4FDC
93 #define mmDP6_DP_DPHY_BS_SR_SWAP_CNTL 0x54DC
94 #endif
95
96 #ifndef mmDP_DPHY_FAST_TRAINING
97 #define mmDP_DPHY_FAST_TRAINING 0x4ABC
98 #define mmDP0_DP_DPHY_FAST_TRAINING 0x4ABC
99 #define mmDP1_DP_DPHY_FAST_TRAINING 0x4BBC
100 #define mmDP2_DP_DPHY_FAST_TRAINING 0x4CBC
101 #define mmDP3_DP_DPHY_FAST_TRAINING 0x4DBC
102 #define mmDP4_DP_DPHY_FAST_TRAINING 0x4EBC
103 #define mmDP5_DP_DPHY_FAST_TRAINING 0x4FBC
104 #define mmDP6_DP_DPHY_FAST_TRAINING 0x54BC
105 #endif
106
107 enum dce112_clk_src_array_id {
108 DCE112_CLK_SRC_PLL0,
109 DCE112_CLK_SRC_PLL1,
110 DCE112_CLK_SRC_PLL2,
111 DCE112_CLK_SRC_PLL3,
112 DCE112_CLK_SRC_PLL4,
113 DCE112_CLK_SRC_PLL5,
114
115 DCE112_CLK_SRC_TOTAL
116 };
117
118 static const struct dce110_timing_generator_offsets dce112_tg_offsets[] = {
119 {
120 .crtc = (mmCRTC0_CRTC_CONTROL - mmCRTC_CONTROL),
121 .dcp = (mmDCP0_GRPH_CONTROL - mmGRPH_CONTROL),
122 },
123 {
124 .crtc = (mmCRTC1_CRTC_CONTROL - mmCRTC_CONTROL),
125 .dcp = (mmDCP1_GRPH_CONTROL - mmGRPH_CONTROL),
126 },
127 {
128 .crtc = (mmCRTC2_CRTC_CONTROL - mmCRTC_CONTROL),
129 .dcp = (mmDCP2_GRPH_CONTROL - mmGRPH_CONTROL),
130 },
131 {
132 .crtc = (mmCRTC3_CRTC_CONTROL - mmCRTC_CONTROL),
133 .dcp = (mmDCP3_GRPH_CONTROL - mmGRPH_CONTROL),
134 },
135 {
136 .crtc = (mmCRTC4_CRTC_CONTROL - mmCRTC_CONTROL),
137 .dcp = (mmDCP4_GRPH_CONTROL - mmGRPH_CONTROL),
138 },
139 {
140 .crtc = (mmCRTC5_CRTC_CONTROL - mmCRTC_CONTROL),
141 .dcp = (mmDCP5_GRPH_CONTROL - mmGRPH_CONTROL),
142 }
143 };
144
145 /* set register offset */
146 #define SR(reg_name)\
147 .reg_name = mm ## reg_name
148
149 /* set register offset with instance */
150 #define SRI(reg_name, block, id)\
151 .reg_name = mm ## block ## id ## _ ## reg_name
152
153 static const struct dce_dmcu_registers dmcu_regs = {
154 DMCU_DCE110_COMMON_REG_LIST()
155 };
156
157 static const struct dce_dmcu_shift dmcu_shift = {
158 DMCU_MASK_SH_LIST_DCE110(__SHIFT)
159 };
160
161 static const struct dce_dmcu_mask dmcu_mask = {
162 DMCU_MASK_SH_LIST_DCE110(_MASK)
163 };
164
165 static const struct dce_abm_registers abm_regs = {
166 ABM_DCE110_COMMON_REG_LIST()
167 };
168
169 static const struct dce_abm_shift abm_shift = {
170 ABM_MASK_SH_LIST_DCE110(__SHIFT)
171 };
172
173 static const struct dce_abm_mask abm_mask = {
174 ABM_MASK_SH_LIST_DCE110(_MASK)
175 };
176
177 static const struct dce110_aux_registers_shift aux_shift = {
178 DCE_AUX_MASK_SH_LIST(__SHIFT)
179 };
180
181 static const struct dce110_aux_registers_mask aux_mask = {
182 DCE_AUX_MASK_SH_LIST(_MASK)
183 };
184
185 #define ipp_regs(id)\
186 [id] = {\
187 IPP_DCE110_REG_LIST_DCE_BASE(id)\
188 }
189
190 static const struct dce_ipp_registers ipp_regs[] = {
191 ipp_regs(0),
192 ipp_regs(1),
193 ipp_regs(2),
194 ipp_regs(3),
195 ipp_regs(4),
196 ipp_regs(5)
197 };
198
199 static const struct dce_ipp_shift ipp_shift = {
200 IPP_DCE100_MASK_SH_LIST_DCE_COMMON_BASE(__SHIFT)
201 };
202
203 static const struct dce_ipp_mask ipp_mask = {
204 IPP_DCE100_MASK_SH_LIST_DCE_COMMON_BASE(_MASK)
205 };
206
207 #define transform_regs(id)\
208 [id] = {\
209 XFM_COMMON_REG_LIST_DCE110(id)\
210 }
211
212 static const struct dce_transform_registers xfm_regs[] = {
213 transform_regs(0),
214 transform_regs(1),
215 transform_regs(2),
216 transform_regs(3),
217 transform_regs(4),
218 transform_regs(5)
219 };
220
221 static const struct dce_transform_shift xfm_shift = {
222 XFM_COMMON_MASK_SH_LIST_DCE110(__SHIFT)
223 };
224
225 static const struct dce_transform_mask xfm_mask = {
226 XFM_COMMON_MASK_SH_LIST_DCE110(_MASK)
227 };
228
229 #define aux_regs(id)\
230 [id] = {\
231 AUX_REG_LIST(id)\
232 }
233
234 static const struct dce110_link_enc_aux_registers link_enc_aux_regs[] = {
235 aux_regs(0),
236 aux_regs(1),
237 aux_regs(2),
238 aux_regs(3),
239 aux_regs(4),
240 aux_regs(5)
241 };
242
243 static const struct dce_panel_cntl_registers panel_cntl_regs[] = {
244 { DCE_PANEL_CNTL_REG_LIST() }
245 };
246
247 static const struct dce_panel_cntl_shift panel_cntl_shift = {
248 DCE_PANEL_CNTL_MASK_SH_LIST(__SHIFT)
249 };
250
251 static const struct dce_panel_cntl_mask panel_cntl_mask = {
252 DCE_PANEL_CNTL_MASK_SH_LIST(_MASK)
253 };
254
255 #define hpd_regs(id)\
256 [id] = {\
257 HPD_REG_LIST(id)\
258 }
259
260 static const struct dce110_link_enc_hpd_registers link_enc_hpd_regs[] = {
261 hpd_regs(0),
262 hpd_regs(1),
263 hpd_regs(2),
264 hpd_regs(3),
265 hpd_regs(4),
266 hpd_regs(5)
267 };
268
269 #define link_regs(id)\
270 [id] = {\
271 LE_DCE110_REG_LIST(id)\
272 }
273
274 static const struct dce110_link_enc_registers link_enc_regs[] = {
275 link_regs(0),
276 link_regs(1),
277 link_regs(2),
278 link_regs(3),
279 link_regs(4),
280 link_regs(5),
281 link_regs(6),
282 };
283
284 #define stream_enc_regs(id)\
285 [id] = {\
286 SE_COMMON_REG_LIST(id),\
287 .TMDS_CNTL = 0,\
288 }
289
290 static const struct dce110_stream_enc_registers stream_enc_regs[] = {
291 stream_enc_regs(0),
292 stream_enc_regs(1),
293 stream_enc_regs(2),
294 stream_enc_regs(3),
295 stream_enc_regs(4),
296 stream_enc_regs(5)
297 };
298
299 static const struct dce_stream_encoder_shift se_shift = {
300 SE_COMMON_MASK_SH_LIST_DCE112(__SHIFT)
301 };
302
303 static const struct dce_stream_encoder_mask se_mask = {
304 SE_COMMON_MASK_SH_LIST_DCE112(_MASK)
305 };
306
307 #define opp_regs(id)\
308 [id] = {\
309 OPP_DCE_112_REG_LIST(id),\
310 }
311
312 static const struct dce_opp_registers opp_regs[] = {
313 opp_regs(0),
314 opp_regs(1),
315 opp_regs(2),
316 opp_regs(3),
317 opp_regs(4),
318 opp_regs(5)
319 };
320
321 static const struct dce_opp_shift opp_shift = {
322 OPP_COMMON_MASK_SH_LIST_DCE_112(__SHIFT)
323 };
324
325 static const struct dce_opp_mask opp_mask = {
326 OPP_COMMON_MASK_SH_LIST_DCE_112(_MASK)
327 };
328
329 #define aux_engine_regs(id)\
330 [id] = {\
331 AUX_COMMON_REG_LIST(id), \
332 .AUX_RESET_MASK = 0 \
333 }
334
335 static const struct dce110_aux_registers aux_engine_regs[] = {
336 aux_engine_regs(0),
337 aux_engine_regs(1),
338 aux_engine_regs(2),
339 aux_engine_regs(3),
340 aux_engine_regs(4),
341 aux_engine_regs(5)
342 };
343
344 #define audio_regs(id)\
345 [id] = {\
346 AUD_COMMON_REG_LIST(id)\
347 }
348
349 static const struct dce_audio_registers audio_regs[] = {
350 audio_regs(0),
351 audio_regs(1),
352 audio_regs(2),
353 audio_regs(3),
354 audio_regs(4),
355 audio_regs(5)
356 };
357
358 static const struct dce_audio_shift audio_shift = {
359 AUD_COMMON_MASK_SH_LIST(__SHIFT)
360 };
361
362 static const struct dce_audio_mask audio_mask = {
363 AUD_COMMON_MASK_SH_LIST(_MASK)
364 };
365
366 #define clk_src_regs(index, id)\
367 [index] = {\
368 CS_COMMON_REG_LIST_DCE_112(id),\
369 }
370
371 static const struct dce110_clk_src_regs clk_src_regs[] = {
372 clk_src_regs(0, A),
373 clk_src_regs(1, B),
374 clk_src_regs(2, C),
375 clk_src_regs(3, D),
376 clk_src_regs(4, E),
377 clk_src_regs(5, F)
378 };
379
380 static const struct dce110_clk_src_shift cs_shift = {
381 CS_COMMON_MASK_SH_LIST_DCE_112(__SHIFT)
382 };
383
384 static const struct dce110_clk_src_mask cs_mask = {
385 CS_COMMON_MASK_SH_LIST_DCE_112(_MASK)
386 };
387
388 static const struct bios_registers bios_regs = {
389 .BIOS_SCRATCH_0 = mmBIOS_SCRATCH_0,
390 .BIOS_SCRATCH_3 = mmBIOS_SCRATCH_3,
391 .BIOS_SCRATCH_6 = mmBIOS_SCRATCH_6
392 };
393
394 static const struct resource_caps polaris_10_resource_cap = {
395 .num_timing_generator = 6,
396 .num_audio = 6,
397 .num_stream_encoder = 6,
398 .num_pll = 8, /* why 8? 6 combo PHY PLL + 2 regular PLLs? */
399 .num_ddc = 6,
400 };
401
402 static const struct resource_caps polaris_11_resource_cap = {
403 .num_timing_generator = 5,
404 .num_audio = 5,
405 .num_stream_encoder = 5,
406 .num_pll = 8, /* why 8? 6 combo PHY PLL + 2 regular PLLs? */
407 .num_ddc = 5,
408 };
409
410 static const struct dc_plane_cap plane_cap = {
411 .type = DC_PLANE_TYPE_DCE_RGB,
412
413 .pixel_format_support = {
414 .argb8888 = true,
415 .nv12 = false,
416 .fp16 = true
417 },
418
419 .max_upscale_factor = {
420 .argb8888 = 16000,
421 .nv12 = 1,
422 .fp16 = 1
423 },
424
425 .max_downscale_factor = {
426 .argb8888 = 250,
427 .nv12 = 1,
428 .fp16 = 1
429 },
430 64,
431 64
432 };
433
434 static const struct dc_debug_options debug_defaults = { 0 };
435
436 static const struct dc_check_config config_defaults = {
437 .enable_legacy_fast_update = true,
438 };
439
440 #define CTX ctx
441 #define REG(reg) mm ## reg
442
443 #ifndef mmCC_DC_HDMI_STRAPS
444 #define mmCC_DC_HDMI_STRAPS 0x4819
445 #define CC_DC_HDMI_STRAPS__HDMI_DISABLE_MASK 0x40
446 #define CC_DC_HDMI_STRAPS__HDMI_DISABLE__SHIFT 0x6
447 #define CC_DC_HDMI_STRAPS__AUDIO_STREAM_NUMBER_MASK 0x700
448 #define CC_DC_HDMI_STRAPS__AUDIO_STREAM_NUMBER__SHIFT 0x8
449 #endif
450
map_transmitter_id_to_phy_instance(enum transmitter transmitter)451 static int map_transmitter_id_to_phy_instance(
452 enum transmitter transmitter)
453 {
454 switch (transmitter) {
455 case TRANSMITTER_UNIPHY_A:
456 return 0;
457 case TRANSMITTER_UNIPHY_B:
458 return 1;
459 case TRANSMITTER_UNIPHY_C:
460 return 2;
461 case TRANSMITTER_UNIPHY_D:
462 return 3;
463 case TRANSMITTER_UNIPHY_E:
464 return 4;
465 case TRANSMITTER_UNIPHY_F:
466 return 5;
467 case TRANSMITTER_UNIPHY_G:
468 return 6;
469 default:
470 ASSERT(0);
471 return 0;
472 }
473 }
474
read_dce_straps(struct dc_context * ctx,struct resource_straps * straps)475 static void read_dce_straps(
476 struct dc_context *ctx,
477 struct resource_straps *straps)
478 {
479 REG_GET_2(CC_DC_HDMI_STRAPS,
480 HDMI_DISABLE, &straps->hdmi_disable,
481 AUDIO_STREAM_NUMBER, &straps->audio_stream_number);
482
483 REG_GET(DC_PINSTRAPS, DC_PINSTRAPS_AUDIO, &straps->dc_pinstraps_audio);
484 }
485
create_audio(struct dc_context * ctx,unsigned int inst)486 static struct audio *create_audio(
487 struct dc_context *ctx, unsigned int inst)
488 {
489 return dce_audio_create(ctx, inst,
490 &audio_regs[inst], &audio_shift, &audio_mask);
491 }
492
493
dce112_timing_generator_create(struct dc_context * ctx,uint32_t instance,const struct dce110_timing_generator_offsets * offsets)494 static struct timing_generator *dce112_timing_generator_create(
495 struct dc_context *ctx,
496 uint32_t instance,
497 const struct dce110_timing_generator_offsets *offsets)
498 {
499 struct dce110_timing_generator *tg110 =
500 kzalloc_obj(struct dce110_timing_generator);
501
502 if (!tg110)
503 return NULL;
504
505 dce110_timing_generator_construct(tg110, ctx, instance, offsets);
506 return &tg110->base;
507 }
508
dce112_stream_encoder_create(enum engine_id eng_id,struct dc_context * ctx)509 static struct stream_encoder *dce112_stream_encoder_create(
510 enum engine_id eng_id,
511 struct dc_context *ctx)
512 {
513 struct dce110_stream_encoder *enc110 =
514 kzalloc_obj(struct dce110_stream_encoder);
515
516 if (!enc110)
517 return NULL;
518
519 dce110_stream_encoder_construct(enc110, ctx, ctx->dc_bios, eng_id,
520 &stream_enc_regs[eng_id],
521 &se_shift, &se_mask);
522 return &enc110->base;
523 }
524
525 #define SRII(reg_name, block, id)\
526 .reg_name[id] = mm ## block ## id ## _ ## reg_name
527
528 static const struct dce_hwseq_registers hwseq_reg = {
529 HWSEQ_DCE112_REG_LIST()
530 };
531
532 static const struct dce_hwseq_shift hwseq_shift = {
533 HWSEQ_DCE112_MASK_SH_LIST(__SHIFT)
534 };
535
536 static const struct dce_hwseq_mask hwseq_mask = {
537 HWSEQ_DCE112_MASK_SH_LIST(_MASK)
538 };
539
dce112_hwseq_create(struct dc_context * ctx)540 static struct dce_hwseq *dce112_hwseq_create(
541 struct dc_context *ctx)
542 {
543 struct dce_hwseq *hws = kzalloc_obj(struct dce_hwseq);
544
545 if (hws) {
546 hws->ctx = ctx;
547 hws->regs = &hwseq_reg;
548 hws->shifts = &hwseq_shift;
549 hws->masks = &hwseq_mask;
550 }
551 return hws;
552 }
553
554 static const struct resource_create_funcs res_create_funcs = {
555 .read_dce_straps = read_dce_straps,
556 .create_audio = create_audio,
557 .create_stream_encoder = dce112_stream_encoder_create,
558 .create_hwseq = dce112_hwseq_create,
559 };
560
561 #define mi_inst_regs(id) { MI_DCE11_2_REG_LIST(id) }
562 static const struct dce_mem_input_registers mi_regs[] = {
563 mi_inst_regs(0),
564 mi_inst_regs(1),
565 mi_inst_regs(2),
566 mi_inst_regs(3),
567 mi_inst_regs(4),
568 mi_inst_regs(5),
569 };
570
571 static const struct dce_mem_input_shift mi_shifts = {
572 MI_DCE11_2_MASK_SH_LIST(__SHIFT)
573 };
574
575 static const struct dce_mem_input_mask mi_masks = {
576 MI_DCE11_2_MASK_SH_LIST(_MASK)
577 };
578
dce112_mem_input_create(struct dc_context * ctx,uint32_t inst)579 static struct mem_input *dce112_mem_input_create(
580 struct dc_context *ctx,
581 uint32_t inst)
582 {
583 struct dce_mem_input *dce_mi = kzalloc_obj(struct dce_mem_input);
584
585 if (!dce_mi) {
586 BREAK_TO_DEBUGGER();
587 return NULL;
588 }
589
590 dce112_mem_input_construct(dce_mi, ctx, inst, &mi_regs[inst], &mi_shifts, &mi_masks);
591 return &dce_mi->base;
592 }
593
dce112_transform_destroy(struct transform ** xfm)594 static void dce112_transform_destroy(struct transform **xfm)
595 {
596 kfree(TO_DCE_TRANSFORM(*xfm));
597 *xfm = NULL;
598 }
599
dce112_transform_create(struct dc_context * ctx,uint32_t inst)600 static struct transform *dce112_transform_create(
601 struct dc_context *ctx,
602 uint32_t inst)
603 {
604 struct dce_transform *transform =
605 kzalloc_obj(struct dce_transform);
606
607 if (!transform)
608 return NULL;
609
610 dce_transform_construct(transform, ctx, inst,
611 &xfm_regs[inst], &xfm_shift, &xfm_mask);
612 transform->lb_memory_size = 0x1404; /*5124*/
613 return &transform->base;
614 }
615
616 static const struct encoder_feature_support link_enc_feature = {
617 .max_hdmi_deep_color = COLOR_DEPTH_121212,
618 .max_hdmi_pixel_clock = 600000,
619 .hdmi_ycbcr420_supported = true,
620 .dp_ycbcr420_supported = false,
621 .flags.bits.IS_HBR2_CAPABLE = true,
622 .flags.bits.IS_HBR3_CAPABLE = true,
623 .flags.bits.IS_TPS3_CAPABLE = true,
624 .flags.bits.IS_TPS4_CAPABLE = true
625 };
626
dce112_link_encoder_create(struct dc_context * ctx,const struct encoder_init_data * enc_init_data)627 static struct link_encoder *dce112_link_encoder_create(
628 struct dc_context *ctx,
629 const struct encoder_init_data *enc_init_data)
630 {
631 (void)ctx;
632 struct dce110_link_encoder *enc110 =
633 kzalloc_obj(struct dce110_link_encoder);
634 int link_regs_id;
635
636 if (!enc110)
637 return NULL;
638
639 link_regs_id =
640 map_transmitter_id_to_phy_instance(enc_init_data->transmitter);
641
642 dce110_link_encoder_construct(enc110,
643 enc_init_data,
644 &link_enc_feature,
645 &link_enc_regs[link_regs_id],
646 &link_enc_aux_regs[enc_init_data->channel - 1],
647 enc_init_data->hpd_source >= ARRAY_SIZE(link_enc_hpd_regs) ?
648 NULL : &link_enc_hpd_regs[enc_init_data->hpd_source]);
649 return &enc110->base;
650 }
651
dce112_panel_cntl_create(const struct panel_cntl_init_data * init_data)652 static struct panel_cntl *dce112_panel_cntl_create(const struct panel_cntl_init_data *init_data)
653 {
654 struct dce_panel_cntl *panel_cntl =
655 kzalloc_obj(struct dce_panel_cntl);
656
657 if (!panel_cntl)
658 return NULL;
659
660 dce_panel_cntl_construct(panel_cntl,
661 init_data,
662 &panel_cntl_regs[init_data->inst],
663 &panel_cntl_shift,
664 &panel_cntl_mask);
665
666 return &panel_cntl->base;
667 }
668
dce112_ipp_create(struct dc_context * ctx,uint32_t inst)669 static struct input_pixel_processor *dce112_ipp_create(
670 struct dc_context *ctx, uint32_t inst)
671 {
672 struct dce_ipp *ipp = kzalloc_obj(struct dce_ipp);
673
674 if (!ipp) {
675 BREAK_TO_DEBUGGER();
676 return NULL;
677 }
678
679 dce_ipp_construct(ipp, ctx, inst,
680 &ipp_regs[inst], &ipp_shift, &ipp_mask);
681 return &ipp->base;
682 }
683
dce112_opp_create(struct dc_context * ctx,uint32_t inst)684 static struct output_pixel_processor *dce112_opp_create(
685 struct dc_context *ctx,
686 uint32_t inst)
687 {
688 struct dce110_opp *opp =
689 kzalloc_obj(struct dce110_opp);
690
691 if (!opp)
692 return NULL;
693
694 dce110_opp_construct(opp,
695 ctx, inst, &opp_regs[inst], &opp_shift, &opp_mask);
696 return &opp->base;
697 }
698
dce112_aux_engine_create(struct dc_context * ctx,uint32_t inst)699 static struct dce_aux *dce112_aux_engine_create(
700 struct dc_context *ctx,
701 uint32_t inst)
702 {
703 struct aux_engine_dce110 *aux_engine =
704 kzalloc_obj(struct aux_engine_dce110);
705
706 if (!aux_engine)
707 return NULL;
708
709 dce110_aux_engine_construct(aux_engine, ctx, inst,
710 SW_AUX_TIMEOUT_PERIOD_MULTIPLIER * AUX_TIMEOUT_PERIOD,
711 &aux_engine_regs[inst],
712 &aux_mask,
713 &aux_shift,
714 ctx->dc->caps.extended_aux_timeout_support);
715
716 return &aux_engine->base;
717 }
718 #define i2c_inst_regs(id) { I2C_HW_ENGINE_COMMON_REG_LIST(id) }
719
720 static const struct dce_i2c_registers i2c_hw_regs[] = {
721 i2c_inst_regs(1),
722 i2c_inst_regs(2),
723 i2c_inst_regs(3),
724 i2c_inst_regs(4),
725 i2c_inst_regs(5),
726 i2c_inst_regs(6),
727 };
728
729 static const struct dce_i2c_shift i2c_shifts = {
730 I2C_COMMON_MASK_SH_LIST_DCE110(__SHIFT)
731 };
732
733 static const struct dce_i2c_mask i2c_masks = {
734 I2C_COMMON_MASK_SH_LIST_DCE110(_MASK)
735 };
736
dce112_i2c_hw_create(struct dc_context * ctx,uint32_t inst)737 static struct dce_i2c_hw *dce112_i2c_hw_create(
738 struct dc_context *ctx,
739 uint32_t inst)
740 {
741 struct dce_i2c_hw *dce_i2c_hw =
742 kzalloc_obj(struct dce_i2c_hw);
743
744 if (!dce_i2c_hw)
745 return NULL;
746
747 dce112_i2c_hw_construct(dce_i2c_hw, ctx, inst,
748 &i2c_hw_regs[inst], &i2c_shifts, &i2c_masks);
749
750 return dce_i2c_hw;
751 }
dce112_clock_source_create(struct dc_context * ctx,struct dc_bios * bios,enum clock_source_id id,const struct dce110_clk_src_regs * regs,bool dp_clk_src)752 static struct clock_source *dce112_clock_source_create(
753 struct dc_context *ctx,
754 struct dc_bios *bios,
755 enum clock_source_id id,
756 const struct dce110_clk_src_regs *regs,
757 bool dp_clk_src)
758 {
759 struct dce110_clk_src *clk_src =
760 kzalloc_obj(struct dce110_clk_src);
761
762 if (!clk_src)
763 return NULL;
764
765 if (dce112_clk_src_construct(clk_src, ctx, bios, id,
766 regs, &cs_shift, &cs_mask)) {
767 clk_src->base.dp_clk_src = dp_clk_src;
768 return &clk_src->base;
769 }
770
771 kfree(clk_src);
772 BREAK_TO_DEBUGGER();
773 return NULL;
774 }
775
dce112_clock_source_destroy(struct clock_source ** clk_src)776 static void dce112_clock_source_destroy(struct clock_source **clk_src)
777 {
778 kfree(TO_DCE110_CLK_SRC(*clk_src));
779 *clk_src = NULL;
780 }
781
dce112_resource_destruct(struct dce110_resource_pool * pool)782 static void dce112_resource_destruct(struct dce110_resource_pool *pool)
783 {
784 unsigned int i;
785
786 for (i = 0; i < pool->base.pipe_count; i++) {
787 if (pool->base.opps[i] != NULL)
788 dce110_opp_destroy(&pool->base.opps[i]);
789
790 if (pool->base.transforms[i] != NULL)
791 dce112_transform_destroy(&pool->base.transforms[i]);
792
793 if (pool->base.ipps[i] != NULL)
794 dce_ipp_destroy(&pool->base.ipps[i]);
795
796 if (pool->base.mis[i] != NULL) {
797 kfree(TO_DCE_MEM_INPUT(pool->base.mis[i]));
798 pool->base.mis[i] = NULL;
799 }
800
801 if (pool->base.timing_generators[i] != NULL) {
802 kfree(DCE110TG_FROM_TG(pool->base.timing_generators[i]));
803 pool->base.timing_generators[i] = NULL;
804 }
805 }
806
807 for (i = 0; i < pool->base.res_cap->num_ddc; i++) {
808 if (pool->base.engines[i] != NULL)
809 dce110_engine_destroy(&pool->base.engines[i]);
810 if (pool->base.hw_i2cs[i] != NULL) {
811 kfree(pool->base.hw_i2cs[i]);
812 pool->base.hw_i2cs[i] = NULL;
813 }
814 if (pool->base.sw_i2cs[i] != NULL) {
815 kfree(pool->base.sw_i2cs[i]);
816 pool->base.sw_i2cs[i] = NULL;
817 }
818 }
819
820 for (i = 0; i < pool->base.stream_enc_count; i++) {
821 if (pool->base.stream_enc[i] != NULL)
822 kfree(DCE110STRENC_FROM_STRENC(pool->base.stream_enc[i]));
823 }
824
825 for (i = 0; i < pool->base.clk_src_count; i++) {
826 if (pool->base.clock_sources[i] != NULL) {
827 dce112_clock_source_destroy(&pool->base.clock_sources[i]);
828 }
829 }
830
831 if (pool->base.dp_clock_source != NULL)
832 dce112_clock_source_destroy(&pool->base.dp_clock_source);
833
834 for (i = 0; i < pool->base.audio_count; i++) {
835 if (pool->base.audios[i] != NULL) {
836 dce_aud_destroy(&pool->base.audios[i]);
837 }
838 }
839
840 if (pool->base.abm != NULL)
841 dce_abm_destroy(&pool->base.abm);
842
843 if (pool->base.dmcu != NULL)
844 dce_dmcu_destroy(&pool->base.dmcu);
845
846 if (pool->base.irqs != NULL) {
847 dal_irq_service_destroy(&pool->base.irqs);
848 }
849 }
850
find_matching_pll(struct resource_context * res_ctx,const struct resource_pool * pool,const struct dc_stream_state * const stream)851 static struct clock_source *find_matching_pll(
852 struct resource_context *res_ctx,
853 const struct resource_pool *pool,
854 const struct dc_stream_state *const stream)
855 {
856 (void)res_ctx;
857 switch (stream->link->link_enc->transmitter) {
858 case TRANSMITTER_UNIPHY_A:
859 return pool->clock_sources[DCE112_CLK_SRC_PLL0];
860 case TRANSMITTER_UNIPHY_B:
861 return pool->clock_sources[DCE112_CLK_SRC_PLL1];
862 case TRANSMITTER_UNIPHY_C:
863 return pool->clock_sources[DCE112_CLK_SRC_PLL2];
864 case TRANSMITTER_UNIPHY_D:
865 return pool->clock_sources[DCE112_CLK_SRC_PLL3];
866 case TRANSMITTER_UNIPHY_E:
867 return pool->clock_sources[DCE112_CLK_SRC_PLL4];
868 case TRANSMITTER_UNIPHY_F:
869 return pool->clock_sources[DCE112_CLK_SRC_PLL5];
870 default:
871 return NULL;
872 }
873 }
874
build_mapped_resource(const struct dc * dc,struct dc_state * context,struct dc_stream_state * stream)875 static enum dc_status build_mapped_resource(
876 const struct dc *dc,
877 struct dc_state *context,
878 struct dc_stream_state *stream)
879 {
880 (void)dc;
881 struct pipe_ctx *pipe_ctx = resource_get_otg_master_for_stream(&context->res_ctx, stream);
882
883 if (!pipe_ctx)
884 return DC_ERROR_UNEXPECTED;
885
886 dce110_resource_build_pipe_hw_param(pipe_ctx);
887
888 resource_build_info_frame(pipe_ctx);
889
890 return DC_OK;
891 }
892
dce112_validate_bandwidth(struct dc * dc,struct dc_state * context,enum dc_validate_mode validate_mode)893 enum dc_status dce112_validate_bandwidth(
894 struct dc *dc,
895 struct dc_state *context,
896 enum dc_validate_mode validate_mode)
897 {
898 (void)validate_mode;
899 bool result = false;
900
901 DC_LOG_BANDWIDTH_CALCS(
902 "%s: start",
903 __func__);
904
905 if (bw_calcs(
906 dc->ctx,
907 dc->bw_dceip,
908 dc->bw_vbios,
909 context->res_ctx.pipe_ctx,
910 dc->res_pool->pipe_count,
911 &context->bw_ctx.bw.dce))
912 result = true;
913
914 if (!result)
915 DC_LOG_BANDWIDTH_VALIDATION(
916 "%s: Bandwidth validation failed!",
917 __func__);
918
919 if (memcmp(&dc->current_state->bw_ctx.bw.dce,
920 &context->bw_ctx.bw.dce, sizeof(context->bw_ctx.bw.dce))) {
921
922 DC_LOG_BANDWIDTH_CALCS(
923 "%s: finish,\n"
924 "nbpMark_b: %d nbpMark_a: %d urgentMark_b: %d urgentMark_a: %d\n"
925 "stutMark_b: %d stutMark_a: %d\n"
926 "nbpMark_b: %d nbpMark_a: %d urgentMark_b: %d urgentMark_a: %d\n"
927 "stutMark_b: %d stutMark_a: %d\n"
928 "nbpMark_b: %d nbpMark_a: %d urgentMark_b: %d urgentMark_a: %d\n"
929 "stutMark_b: %d stutMark_a: %d stutter_mode_enable: %d\n"
930 "cstate: %d pstate: %d nbpstate: %d sync: %d dispclk: %d\n"
931 "sclk: %d sclk_sleep: %d yclk: %d blackout_recovery_time_us: %d\n"
932 ,
933 __func__,
934 context->bw_ctx.bw.dce.nbp_state_change_wm_ns[0].b_mark,
935 context->bw_ctx.bw.dce.nbp_state_change_wm_ns[0].a_mark,
936 context->bw_ctx.bw.dce.urgent_wm_ns[0].b_mark,
937 context->bw_ctx.bw.dce.urgent_wm_ns[0].a_mark,
938 context->bw_ctx.bw.dce.stutter_exit_wm_ns[0].b_mark,
939 context->bw_ctx.bw.dce.stutter_exit_wm_ns[0].a_mark,
940 context->bw_ctx.bw.dce.nbp_state_change_wm_ns[1].b_mark,
941 context->bw_ctx.bw.dce.nbp_state_change_wm_ns[1].a_mark,
942 context->bw_ctx.bw.dce.urgent_wm_ns[1].b_mark,
943 context->bw_ctx.bw.dce.urgent_wm_ns[1].a_mark,
944 context->bw_ctx.bw.dce.stutter_exit_wm_ns[1].b_mark,
945 context->bw_ctx.bw.dce.stutter_exit_wm_ns[1].a_mark,
946 context->bw_ctx.bw.dce.nbp_state_change_wm_ns[2].b_mark,
947 context->bw_ctx.bw.dce.nbp_state_change_wm_ns[2].a_mark,
948 context->bw_ctx.bw.dce.urgent_wm_ns[2].b_mark,
949 context->bw_ctx.bw.dce.urgent_wm_ns[2].a_mark,
950 context->bw_ctx.bw.dce.stutter_exit_wm_ns[2].b_mark,
951 context->bw_ctx.bw.dce.stutter_exit_wm_ns[2].a_mark,
952 context->bw_ctx.bw.dce.stutter_mode_enable,
953 context->bw_ctx.bw.dce.cpuc_state_change_enable,
954 context->bw_ctx.bw.dce.cpup_state_change_enable,
955 context->bw_ctx.bw.dce.nbp_state_change_enable,
956 context->bw_ctx.bw.dce.all_displays_in_sync,
957 context->bw_ctx.bw.dce.dispclk_khz,
958 context->bw_ctx.bw.dce.sclk_khz,
959 context->bw_ctx.bw.dce.sclk_deep_sleep_khz,
960 context->bw_ctx.bw.dce.yclk_khz,
961 context->bw_ctx.bw.dce.blackout_recovery_time_us);
962 }
963 return result ? DC_OK : DC_FAIL_BANDWIDTH_VALIDATE;
964 }
965
resource_map_phy_clock_resources(const struct dc * dc,struct dc_state * context,struct dc_stream_state * stream)966 enum dc_status resource_map_phy_clock_resources(
967 const struct dc *dc,
968 struct dc_state *context,
969 struct dc_stream_state *stream)
970 {
971
972 /* acquire new resources */
973 struct pipe_ctx *pipe_ctx = resource_get_otg_master_for_stream(
974 &context->res_ctx, stream);
975
976 if (!pipe_ctx)
977 return DC_ERROR_UNEXPECTED;
978
979 if (dc_is_dp_signal(pipe_ctx->stream->signal)
980 || dc_is_virtual_signal(pipe_ctx->stream->signal))
981 pipe_ctx->clock_source =
982 dc->res_pool->dp_clock_source;
983 else {
984 if (stream && stream->link && stream->link->link_enc)
985 pipe_ctx->clock_source = find_matching_pll(
986 &context->res_ctx, dc->res_pool,
987 stream);
988 }
989
990 if (pipe_ctx->clock_source == NULL)
991 return DC_NO_CLOCK_SOURCE_RESOURCE;
992
993 resource_reference_clock_source(
994 &context->res_ctx,
995 dc->res_pool,
996 pipe_ctx->clock_source);
997
998 return DC_OK;
999 }
1000
dce112_validate_surface_sets(struct dc_state * context)1001 static bool dce112_validate_surface_sets(
1002 struct dc_state *context)
1003 {
1004 int i;
1005
1006 for (i = 0; i < context->stream_count; i++) {
1007 if (context->stream_status[i].plane_count == 0)
1008 continue;
1009
1010 if (context->stream_status[i].plane_count > 1)
1011 return false;
1012
1013 if (context->stream_status[i].plane_states[0]->format
1014 >= SURFACE_PIXEL_FORMAT_VIDEO_BEGIN)
1015 return false;
1016 }
1017
1018 return true;
1019 }
1020
dce112_add_stream_to_ctx(struct dc * dc,struct dc_state * new_ctx,struct dc_stream_state * dc_stream)1021 enum dc_status dce112_add_stream_to_ctx(
1022 struct dc *dc,
1023 struct dc_state *new_ctx,
1024 struct dc_stream_state *dc_stream)
1025 {
1026 enum dc_status result;
1027
1028 result = resource_map_pool_resources(dc, new_ctx, dc_stream);
1029
1030 if (result == DC_OK)
1031 result = resource_map_phy_clock_resources(dc, new_ctx, dc_stream);
1032
1033
1034 if (result == DC_OK)
1035 result = build_mapped_resource(dc, new_ctx, dc_stream);
1036
1037 return result;
1038 }
1039
dce112_validate_global(struct dc * dc,struct dc_state * context)1040 static enum dc_status dce112_validate_global(
1041 struct dc *dc,
1042 struct dc_state *context)
1043 {
1044 (void)dc;
1045 if (!dce112_validate_surface_sets(context))
1046 return DC_FAIL_SURFACE_VALIDATE;
1047
1048 return DC_OK;
1049 }
1050
dce112_destroy_resource_pool(struct resource_pool ** pool)1051 static void dce112_destroy_resource_pool(struct resource_pool **pool)
1052 {
1053 struct dce110_resource_pool *dce110_pool = TO_DCE110_RES_POOL(*pool);
1054
1055 dce112_resource_destruct(dce110_pool);
1056 kfree(dce110_pool);
1057 *pool = NULL;
1058 }
1059
1060 static const struct resource_funcs dce112_res_pool_funcs = {
1061 .destroy = dce112_destroy_resource_pool,
1062 .link_enc_create = dce112_link_encoder_create,
1063 .panel_cntl_create = dce112_panel_cntl_create,
1064 .validate_bandwidth = dce112_validate_bandwidth,
1065 .validate_plane = dce100_validate_plane,
1066 .add_stream_to_ctx = dce112_add_stream_to_ctx,
1067 .validate_global = dce112_validate_global,
1068 .find_first_free_match_stream_enc_for_link = dce110_find_first_free_match_stream_enc_for_link
1069 };
1070
bw_calcs_data_update_from_pplib(struct dc * dc)1071 static void bw_calcs_data_update_from_pplib(struct dc *dc)
1072 {
1073 struct dm_pp_clock_levels_with_latency eng_clks = {0};
1074 struct dm_pp_clock_levels_with_latency mem_clks = {0};
1075 struct dm_pp_wm_sets_with_clock_ranges clk_ranges = {0};
1076 struct dm_pp_clock_levels clks = {0};
1077 int memory_type_multiplier = MEMORY_TYPE_MULTIPLIER_CZ;
1078
1079 if (!dc->bw_vbios)
1080 return;
1081
1082 if (dc->bw_vbios->memory_type == bw_def_hbm)
1083 memory_type_multiplier = MEMORY_TYPE_HBM;
1084
1085 /*do system clock TODO PPLIB: after PPLIB implement,
1086 * then remove old way
1087 */
1088 if (!dm_pp_get_clock_levels_by_type_with_latency(
1089 dc->ctx,
1090 DM_PP_CLOCK_TYPE_ENGINE_CLK,
1091 &eng_clks)) {
1092
1093 /* This is only for temporary */
1094 dm_pp_get_clock_levels_by_type(
1095 dc->ctx,
1096 DM_PP_CLOCK_TYPE_ENGINE_CLK,
1097 &clks);
1098 /* convert all the clock fro kHz to fix point mHz */
1099 dc->bw_vbios->high_sclk = bw_frc_to_fixed(
1100 clks.clocks_in_khz[clks.num_levels-1], 1000);
1101 dc->bw_vbios->mid1_sclk = bw_frc_to_fixed(
1102 clks.clocks_in_khz[clks.num_levels/8], 1000);
1103 dc->bw_vbios->mid2_sclk = bw_frc_to_fixed(
1104 clks.clocks_in_khz[clks.num_levels*2/8], 1000);
1105 dc->bw_vbios->mid3_sclk = bw_frc_to_fixed(
1106 clks.clocks_in_khz[clks.num_levels*3/8], 1000);
1107 dc->bw_vbios->mid4_sclk = bw_frc_to_fixed(
1108 clks.clocks_in_khz[clks.num_levels*4/8], 1000);
1109 dc->bw_vbios->mid5_sclk = bw_frc_to_fixed(
1110 clks.clocks_in_khz[clks.num_levels*5/8], 1000);
1111 dc->bw_vbios->mid6_sclk = bw_frc_to_fixed(
1112 clks.clocks_in_khz[clks.num_levels*6/8], 1000);
1113 dc->bw_vbios->low_sclk = bw_frc_to_fixed(
1114 clks.clocks_in_khz[0], 1000);
1115
1116 /*do memory clock*/
1117 dm_pp_get_clock_levels_by_type(
1118 dc->ctx,
1119 DM_PP_CLOCK_TYPE_MEMORY_CLK,
1120 &clks);
1121
1122 dc->bw_vbios->low_yclk = bw_frc_to_fixed(
1123 (int64_t)clks.clocks_in_khz[0] * memory_type_multiplier, 1000);
1124 dc->bw_vbios->mid_yclk = bw_frc_to_fixed(
1125 (int64_t)clks.clocks_in_khz[clks.num_levels>>1] * memory_type_multiplier,
1126 1000);
1127 dc->bw_vbios->high_yclk = bw_frc_to_fixed(
1128 (int64_t)clks.clocks_in_khz[clks.num_levels-1] * memory_type_multiplier,
1129 1000);
1130
1131 return;
1132 }
1133
1134 /* convert all the clock fro kHz to fix point mHz TODO: wloop data */
1135 dc->bw_vbios->high_sclk = bw_frc_to_fixed(
1136 eng_clks.data[eng_clks.num_levels-1].clocks_in_khz, 1000);
1137 dc->bw_vbios->mid1_sclk = bw_frc_to_fixed(
1138 eng_clks.data[eng_clks.num_levels/8].clocks_in_khz, 1000);
1139 dc->bw_vbios->mid2_sclk = bw_frc_to_fixed(
1140 eng_clks.data[eng_clks.num_levels*2/8].clocks_in_khz, 1000);
1141 dc->bw_vbios->mid3_sclk = bw_frc_to_fixed(
1142 eng_clks.data[eng_clks.num_levels*3/8].clocks_in_khz, 1000);
1143 dc->bw_vbios->mid4_sclk = bw_frc_to_fixed(
1144 eng_clks.data[eng_clks.num_levels*4/8].clocks_in_khz, 1000);
1145 dc->bw_vbios->mid5_sclk = bw_frc_to_fixed(
1146 eng_clks.data[eng_clks.num_levels*5/8].clocks_in_khz, 1000);
1147 dc->bw_vbios->mid6_sclk = bw_frc_to_fixed(
1148 eng_clks.data[eng_clks.num_levels*6/8].clocks_in_khz, 1000);
1149 dc->bw_vbios->low_sclk = bw_frc_to_fixed(
1150 eng_clks.data[0].clocks_in_khz, 1000);
1151
1152 /*do memory clock*/
1153 dm_pp_get_clock_levels_by_type_with_latency(
1154 dc->ctx,
1155 DM_PP_CLOCK_TYPE_MEMORY_CLK,
1156 &mem_clks);
1157
1158 /* we don't need to call PPLIB for validation clock since they
1159 * also give us the highest sclk and highest mclk (UMA clock).
1160 * ALSO always convert UMA clock (from PPLIB) to YCLK (HW formula):
1161 * YCLK = UMACLK*m_memoryTypeMultiplier
1162 */
1163 dc->bw_vbios->low_yclk = bw_frc_to_fixed(
1164 (int64_t)mem_clks.data[0].clocks_in_khz * memory_type_multiplier, 1000);
1165 dc->bw_vbios->mid_yclk = bw_frc_to_fixed(
1166 (int64_t)mem_clks.data[mem_clks.num_levels>>1].clocks_in_khz * memory_type_multiplier,
1167 1000);
1168 dc->bw_vbios->high_yclk = bw_frc_to_fixed(
1169 (int64_t)mem_clks.data[mem_clks.num_levels-1].clocks_in_khz * memory_type_multiplier,
1170 1000);
1171
1172 /* Now notify PPLib/SMU about which Watermarks sets they should select
1173 * depending on DPM state they are in. And update BW MGR GFX Engine and
1174 * Memory clock member variables for Watermarks calculations for each
1175 * Watermark Set
1176 */
1177 clk_ranges.num_wm_sets = 4;
1178 clk_ranges.wm_clk_ranges[0].wm_set_id = WM_SET_A;
1179 clk_ranges.wm_clk_ranges[0].wm_min_eng_clk_in_khz =
1180 eng_clks.data[0].clocks_in_khz;
1181 clk_ranges.wm_clk_ranges[0].wm_max_eng_clk_in_khz =
1182 eng_clks.data[eng_clks.num_levels*3/8].clocks_in_khz - 1;
1183 clk_ranges.wm_clk_ranges[0].wm_min_mem_clk_in_khz =
1184 mem_clks.data[0].clocks_in_khz;
1185 clk_ranges.wm_clk_ranges[0].wm_max_mem_clk_in_khz =
1186 mem_clks.data[mem_clks.num_levels>>1].clocks_in_khz - 1;
1187
1188 clk_ranges.wm_clk_ranges[1].wm_set_id = WM_SET_B;
1189 clk_ranges.wm_clk_ranges[1].wm_min_eng_clk_in_khz =
1190 eng_clks.data[eng_clks.num_levels*3/8].clocks_in_khz;
1191 /* 5 GHz instead of data[7].clockInKHz to cover Overdrive */
1192 clk_ranges.wm_clk_ranges[1].wm_max_eng_clk_in_khz = 5000000;
1193 clk_ranges.wm_clk_ranges[1].wm_min_mem_clk_in_khz =
1194 mem_clks.data[0].clocks_in_khz;
1195 clk_ranges.wm_clk_ranges[1].wm_max_mem_clk_in_khz =
1196 mem_clks.data[mem_clks.num_levels>>1].clocks_in_khz - 1;
1197
1198 clk_ranges.wm_clk_ranges[2].wm_set_id = WM_SET_C;
1199 clk_ranges.wm_clk_ranges[2].wm_min_eng_clk_in_khz =
1200 eng_clks.data[0].clocks_in_khz;
1201 clk_ranges.wm_clk_ranges[2].wm_max_eng_clk_in_khz =
1202 eng_clks.data[eng_clks.num_levels*3/8].clocks_in_khz - 1;
1203 clk_ranges.wm_clk_ranges[2].wm_min_mem_clk_in_khz =
1204 mem_clks.data[mem_clks.num_levels>>1].clocks_in_khz;
1205 /* 5 GHz instead of data[2].clockInKHz to cover Overdrive */
1206 clk_ranges.wm_clk_ranges[2].wm_max_mem_clk_in_khz = 5000000;
1207
1208 clk_ranges.wm_clk_ranges[3].wm_set_id = WM_SET_D;
1209 clk_ranges.wm_clk_ranges[3].wm_min_eng_clk_in_khz =
1210 eng_clks.data[eng_clks.num_levels*3/8].clocks_in_khz;
1211 /* 5 GHz instead of data[7].clockInKHz to cover Overdrive */
1212 clk_ranges.wm_clk_ranges[3].wm_max_eng_clk_in_khz = 5000000;
1213 clk_ranges.wm_clk_ranges[3].wm_min_mem_clk_in_khz =
1214 mem_clks.data[mem_clks.num_levels>>1].clocks_in_khz;
1215 /* 5 GHz instead of data[2].clockInKHz to cover Overdrive */
1216 clk_ranges.wm_clk_ranges[3].wm_max_mem_clk_in_khz = 5000000;
1217
1218 /* Notify PP Lib/SMU which Watermarks to use for which clock ranges */
1219 dm_pp_notify_wm_clock_changes(dc->ctx, &clk_ranges);
1220 }
1221
dce112_resource_cap(struct hw_asic_id * asic_id)1222 static const struct resource_caps *dce112_resource_cap(
1223 struct hw_asic_id *asic_id)
1224 {
1225 if (ASIC_REV_IS_POLARIS11_M(asic_id->hw_internal_rev) ||
1226 ASIC_REV_IS_POLARIS12_V(asic_id->hw_internal_rev))
1227 return &polaris_11_resource_cap;
1228 else
1229 return &polaris_10_resource_cap;
1230 }
1231
dce112_resource_construct(uint8_t num_virtual_links,struct dc * dc,struct dce110_resource_pool * pool)1232 static bool dce112_resource_construct(
1233 uint8_t num_virtual_links,
1234 struct dc *dc,
1235 struct dce110_resource_pool *pool)
1236 {
1237 unsigned int i;
1238 struct dc_context *ctx = dc->ctx;
1239
1240 ctx->dc_bios->regs = &bios_regs;
1241
1242 pool->base.res_cap = dce112_resource_cap(&ctx->asic_id);
1243 pool->base.funcs = &dce112_res_pool_funcs;
1244
1245 /*************************************************
1246 * Resource + asic cap harcoding *
1247 *************************************************/
1248 pool->base.underlay_pipe_index = (unsigned int)NO_UNDERLAY_PIPE;
1249 pool->base.pipe_count = pool->base.res_cap->num_timing_generator;
1250 pool->base.timing_generator_count = pool->base.res_cap->num_timing_generator;
1251 dc->caps.max_downscale_ratio = 200;
1252 dc->caps.i2c_speed_in_khz = 100;
1253 dc->caps.i2c_speed_in_khz_hdcp = 100; /*1.4 w/a not applied by default*/
1254 dc->caps.max_cursor_size = 128;
1255 dc->caps.min_horizontal_blanking_period = 80;
1256 dc->caps.dual_link_dvi = true;
1257 dc->caps.extended_aux_timeout_support = false;
1258 dc->debug = debug_defaults;
1259 dc->check_config = config_defaults;
1260
1261 /*************************************************
1262 * Create resources *
1263 *************************************************/
1264
1265 pool->base.clock_sources[DCE112_CLK_SRC_PLL0] =
1266 dce112_clock_source_create(
1267 ctx, ctx->dc_bios,
1268 CLOCK_SOURCE_COMBO_PHY_PLL0,
1269 &clk_src_regs[0], false);
1270 pool->base.clock_sources[DCE112_CLK_SRC_PLL1] =
1271 dce112_clock_source_create(
1272 ctx, ctx->dc_bios,
1273 CLOCK_SOURCE_COMBO_PHY_PLL1,
1274 &clk_src_regs[1], false);
1275 pool->base.clock_sources[DCE112_CLK_SRC_PLL2] =
1276 dce112_clock_source_create(
1277 ctx, ctx->dc_bios,
1278 CLOCK_SOURCE_COMBO_PHY_PLL2,
1279 &clk_src_regs[2], false);
1280 pool->base.clock_sources[DCE112_CLK_SRC_PLL3] =
1281 dce112_clock_source_create(
1282 ctx, ctx->dc_bios,
1283 CLOCK_SOURCE_COMBO_PHY_PLL3,
1284 &clk_src_regs[3], false);
1285 pool->base.clock_sources[DCE112_CLK_SRC_PLL4] =
1286 dce112_clock_source_create(
1287 ctx, ctx->dc_bios,
1288 CLOCK_SOURCE_COMBO_PHY_PLL4,
1289 &clk_src_regs[4], false);
1290 pool->base.clock_sources[DCE112_CLK_SRC_PLL5] =
1291 dce112_clock_source_create(
1292 ctx, ctx->dc_bios,
1293 CLOCK_SOURCE_COMBO_PHY_PLL5,
1294 &clk_src_regs[5], false);
1295 pool->base.clk_src_count = DCE112_CLK_SRC_TOTAL;
1296
1297 pool->base.dp_clock_source = dce112_clock_source_create(
1298 ctx, ctx->dc_bios,
1299 CLOCK_SOURCE_ID_DP_DTO, &clk_src_regs[0], true);
1300
1301
1302 for (i = 0; i < pool->base.clk_src_count; i++) {
1303 if (pool->base.clock_sources[i] == NULL) {
1304 dm_error("DC: failed to create clock sources!\n");
1305 BREAK_TO_DEBUGGER();
1306 goto res_create_fail;
1307 }
1308 }
1309
1310 pool->base.dmcu = dce_dmcu_create(ctx,
1311 &dmcu_regs,
1312 &dmcu_shift,
1313 &dmcu_mask);
1314 if (pool->base.dmcu == NULL) {
1315 dm_error("DC: failed to create dmcu!\n");
1316 BREAK_TO_DEBUGGER();
1317 goto res_create_fail;
1318 }
1319
1320 pool->base.abm = dce_abm_create(ctx,
1321 &abm_regs,
1322 &abm_shift,
1323 &abm_mask);
1324 if (pool->base.abm == NULL) {
1325 dm_error("DC: failed to create abm!\n");
1326 BREAK_TO_DEBUGGER();
1327 goto res_create_fail;
1328 }
1329
1330 {
1331 struct irq_service_init_data init_data;
1332 init_data.ctx = dc->ctx;
1333 pool->base.irqs = dal_irq_service_dce110_create(&init_data);
1334 if (!pool->base.irqs)
1335 goto res_create_fail;
1336 }
1337
1338 for (i = 0; i < pool->base.pipe_count; i++) {
1339 pool->base.timing_generators[i] =
1340 dce112_timing_generator_create(
1341 ctx,
1342 i,
1343 &dce112_tg_offsets[i]);
1344 if (pool->base.timing_generators[i] == NULL) {
1345 BREAK_TO_DEBUGGER();
1346 dm_error("DC: failed to create tg!\n");
1347 goto res_create_fail;
1348 }
1349
1350 pool->base.mis[i] = dce112_mem_input_create(ctx, i);
1351 if (pool->base.mis[i] == NULL) {
1352 BREAK_TO_DEBUGGER();
1353 dm_error(
1354 "DC: failed to create memory input!\n");
1355 goto res_create_fail;
1356 }
1357
1358 pool->base.ipps[i] = dce112_ipp_create(ctx, i);
1359 if (pool->base.ipps[i] == NULL) {
1360 BREAK_TO_DEBUGGER();
1361 dm_error(
1362 "DC:failed to create input pixel processor!\n");
1363 goto res_create_fail;
1364 }
1365
1366 pool->base.transforms[i] = dce112_transform_create(ctx, i);
1367 if (pool->base.transforms[i] == NULL) {
1368 BREAK_TO_DEBUGGER();
1369 dm_error(
1370 "DC: failed to create transform!\n");
1371 goto res_create_fail;
1372 }
1373
1374 pool->base.opps[i] = dce112_opp_create(
1375 ctx,
1376 i);
1377 if (pool->base.opps[i] == NULL) {
1378 BREAK_TO_DEBUGGER();
1379 dm_error(
1380 "DC:failed to create output pixel processor!\n");
1381 goto res_create_fail;
1382 }
1383 }
1384
1385 for (i = 0; i < pool->base.res_cap->num_ddc; i++) {
1386 pool->base.engines[i] = dce112_aux_engine_create(ctx, i);
1387 if (pool->base.engines[i] == NULL) {
1388 BREAK_TO_DEBUGGER();
1389 dm_error(
1390 "DC:failed to create aux engine!!\n");
1391 goto res_create_fail;
1392 }
1393 pool->base.hw_i2cs[i] = dce112_i2c_hw_create(ctx, i);
1394 if (pool->base.hw_i2cs[i] == NULL) {
1395 BREAK_TO_DEBUGGER();
1396 dm_error(
1397 "DC:failed to create i2c engine!!\n");
1398 goto res_create_fail;
1399 }
1400 pool->base.sw_i2cs[i] = NULL;
1401 }
1402
1403 if (!resource_construct(num_virtual_links, dc, &pool->base,
1404 &res_create_funcs))
1405 goto res_create_fail;
1406
1407 dc->caps.max_planes = pool->base.pipe_count;
1408
1409 for (i = 0; i < dc->caps.max_planes; ++i)
1410 dc->caps.planes[i] = plane_cap;
1411
1412 /* Create hardware sequencer */
1413 dce112_hw_sequencer_construct(dc);
1414
1415 bw_calcs_init(dc->bw_dceip, dc->bw_vbios, dc->ctx->asic_id);
1416
1417 bw_calcs_data_update_from_pplib(dc);
1418
1419 return true;
1420
1421 res_create_fail:
1422 dce112_resource_destruct(pool);
1423 return false;
1424 }
1425
dce112_create_resource_pool(uint8_t num_virtual_links,struct dc * dc)1426 struct resource_pool *dce112_create_resource_pool(
1427 uint8_t num_virtual_links,
1428 struct dc *dc)
1429 {
1430 struct dce110_resource_pool *pool =
1431 kzalloc_obj(struct dce110_resource_pool);
1432
1433 if (!pool)
1434 return NULL;
1435
1436 if (dce112_resource_construct(num_virtual_links, dc, pool))
1437 return &pool->base;
1438
1439 kfree(pool);
1440 BREAK_TO_DEBUGGER();
1441 return NULL;
1442 }
1443