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/freebsd/sys/contrib/device-tree/Bindings/dma/
H A Dmarvell,xor-v2.yaml1 # SPDX-License-Identifier: GPL-2.0
3 ---
4 $id: http://devicetree.org/schemas/dma/marvell,xor-v2.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Marvell XOR v2 engines
10 - Andrew Lunn <andrew@lunn.ch>
15 - const: marvell,xor-v2
16 - items:
17 - enum:
18 - marvell,armada-7k-xor
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H A Dmv-xor-v2.txt1 * Marvell XOR v2 engines
4 - compatible: one of the following values:
5 "marvell,armada-7k-xor"
6 "marvell,xor-v2"
7 - reg: Should contain registers location and length (two sets)
10 - msi-parent: Phandle to the MSI-capable interrupt controller used for
14 - clocks: Optional reference to the clocks used by the XOR engine.
15 - clock-names: mandatory if there is a second clock, in this case the
23 compatible = "marvell,xor-v2";
26 msi-parent = <&gic_v2m0>;
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/freebsd/sys/contrib/device-tree/src/arm64/marvell/
H A Darmada-ap810-ap0.dtsi1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
8 #include <dt-bindings/interrupt-controller/arm-gic.h>
10 /dts-v1/;
14 compatible = "marvell,armada-ap810";
15 #address-cells = <2>;
16 #size-cells = <2>;
24 compatible = "arm,psci-0.2";
28 ap810-ap0 {
29 #address-cells = <2>;
30 #size-cells = <2>;
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H A Darmada-ap80x.dtsi1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
8 #include <dt-bindings/interrupt-controller/arm-gic.h>
9 #include <dt-bindings/thermal/thermal.h>
11 /dts-v1/;
14 #address-cells = <2>;
15 #size-cells = <2>;
25 compatible = "arm,psci-0.2";
29 reserved-memory {
30 #address-cells = <2>;
31 #size-cells = <2>;
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H A Darmada-cp11x.dtsi1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
8 #include <dt-bindings/interrupt-controller/mvebu-icu.h>
9 #include <dt-bindings/thermal/thermal.h>
11 #include "armada-common.dtsi"
27 thermal-zones {
28 CP11X_LABEL(thermal_ic): CP11X_NODE_NAME(ic-thermal) {
29 polling-delay-passive = <0>; /* Interrupt driven */
30 polling-delay = <0>; /* Interrupt driven */
32 thermal-sensors = <&CP11X_LABEL(thermal) 0>;
42 cooling-maps { };
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/freebsd/contrib/llvm-project/llvm/lib/Target/Lanai/
H A DLanaiAluCode.h1 //===-- LanaiAluCode.h - ALU operator encoding -------
29 XOR = 0x06, global() enumerator
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/freebsd/contrib/llvm-project/llvm/lib/Target/PowerPC/
H A DPPCMacroFusion.def1 //=== ---- PPCMacroFusion.def - PowerPC MacroFuson Candidates -v-*- C++ -*-===//
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
5 // SPDX-License-Identifier) Apache-2.0 WITH LLVM-exception
7 //===----------------------------------------------------------------------===//
9 // This file contains descriptions of the macro-fusion pair for PowerPC.
11 //===----------------------------------------------------------------------===//
45 // {add, mulld} - add
46 FUSION_FEATURE(ArithAdd, hasArithAddFusion, -1,
49 // {add, subf} - {and, nand, nor, or}
50 FUSION_FEATURE(ArithLogical, hasAddLogicalFusion, -1,
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H A DPPCExpandAtomicPseudoInsts.cpp1 //===-- PPCExpandAtomicPseudoInsts.cpp - Expand atomic pseudo instrs. -----===//
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
7 //===----------------------------------------------------------------------===//
13 //===----------------------------------------------------------------------===//
26 #define DEBUG_TYPE "ppc-atomic-expand"
55 const MCInstrDesc &OR = TII->get(PPC::OR8); in PairedCopy()
56 const MCInstrDesc &XOR = TII->get(PPC::XOR8); in PairedCopy() local
59 BuildMI(MBB, MBBI, DL, XOR, Dest0).addReg(Dest0).addReg(Dest1); in PairedCopy()
60 BuildMI(MBB, MBBI, DL, XOR, Dest1).addReg(Dest0).addReg(Dest1); in PairedCopy()
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/freebsd/contrib/llvm-project/llvm/lib/Target/X86/
H A DX86InstCombineIntrinsic.cpp1 //===-- X86InstCombineIntrinsic.cpp - X86 specific InstCombine pass -------===//
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
7 //===----------------------------------------------------------------------===//
14 //===----------------------------------------------------------------------===//
31 VectorType *IntTy = VectorType::getInteger(cast<VectorType>(V->getType())); in getNegativeIsTrueBoolVec()
49 ExtMask->getType()->isIntOrIntVectorTy(1)) in getBoolVecFromMask()
63 // Zero Mask - masked load instruction creates a zero vector. in simplifyX86MaskedLoad()
68 // intrinsic to the LLVM intrinsic to allow target-independent optimizations. in simplifyX86MaskedLoad()
72 unsigned AddrSpace = cast<PointerType>(Ptr->getType())->getAddressSpace(); in simplifyX86MaskedLoad()
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H A DX86InstrRAOINT.td1 //===---- X86InstrRAOINT.td -------------------------------*- tablegen -*--===//
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
7 //===----------------------------------------------------------------------===//
9 // This file describes the instructions that make up the Intel RAO-INT
12 //===----------------------------------------------------------------------===//
14 //===----------------------------------------------------------------------===//
15 // RAO-INT instructions
39 defm AXOR : RaoInt<"xor">, T8, XS;
46 defm AXOR : RaoInt<"xor", "_EVEX">, EVEX, T_MAP4, XS;
H A DX86FixupSetCC.cpp1 //===- X86FixupSetCC.cpp - fix zero-extension of setcc patterns -----------===//
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
7 //===----------------------------------------------------------------------===//
9 // This file defines a pass that fixes zero-extension of setcc patterns.
18 // xor %eax, %eax; seta %al
23 // if feature zero-upper is available. It's faster than the xor+setcc sequence.
24 // When r16-r31 is used, it even encodes shorter.
25 //===----------------------------------------------------------------------===//
37 #define DEBUG_TYPE "x86-fixup-setcc"
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/freebsd/crypto/openssl/crypto/camellia/asm/
H A Dcmll-x86_64.pl2 # Copyright 2008-2020 The OpenSSL Project Authors. All Rights Reserved.
25 # -evp camellia-128-ecb 16.7 21.0 22.7
28 # camellia-128-cbc 15.7 20.4 21.1
30 # 128-bit key setup 128 216 205 cycles/key
35 # thanks to 64-bit operations being covertly deployed. Improvement on
36 # EM64T, pre-Core2 Intel x86_64 CPU, is not as impressive, because it
37 # apparently emulates some of 64-bit operations in [32-bit] microcode.
47 ( $xlate="${dir}x86_64-xlate.pl" and -f $xlate ) or
48 ( $xlate="${dir}../../perlasm/x86_64-xlate.pl" and -f $xlate) or
49 die "can't locate x86_64-xlate.pl";
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/freebsd/contrib/llvm-project/llvm/lib/Target/VE/
H A DVVPNodes.def1 //===-- VVPNodes.def - Lists & properties of VE Vector Predication Nodes --===//
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
7 //===----------------------------------------------------------------------===//
11 //===----------------------------------------------------------------------===//
84 HELPER_REDUCTION(XOR, XOR)
108 ADD_BINARY_VVP_OP_COMPACT(XOR) REGISTER_PACKED(VVP_XOR)
/freebsd/contrib/llvm-project/compiler-rt/lib/builtins/hexagon/
H A Ddivsi3.S1 //===----------------------Hexagon builtin routine ------------------------===//
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
7 //===----------------------------------------------------------------------===//
20 .size \name, . - \name
40 p1 = xor(p0,p1)
47 p1 = xor(p0,p1)
53 r0 = mux(p1,#-1,#1)
/freebsd/contrib/wpa/src/crypto/
H A Dsha1-pbkdf2.c2 * SHA1-based key derivation function (PBKDF2) for IEEE 802.11i
3 * Copyright (c) 2003-2005, Jouni Malinen <j@w1.fi>
30 /* F(P, S, c, i) = U1 xor U2 xor ... Uc in pbkdf2_sha1_f()
33 * Uc = PRF(P, Uc-1) in pbkdf2_sha1_f()
42 return -1; in pbkdf2_sha1_f()
48 return -1; in pbkdf2_sha1_f()
61 * pbkdf2_sha1 - SHA1-based key derivation function (PBKDF2) for IEEE 802.11i
68 * Returns: 0 on success, -1 of failure
70 * This function is used to derive PSK for WPA-PSK. For this protocol,
72 * IEEE Std 802.11-2004, Clause H.4. The main construction is from PKCS#5 v2.0.
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/freebsd/contrib/llvm-project/llvm/lib/Target/Mips/
H A DMipsCondMov.td1 //===-- MipsCondMov.td - Describe Mips Conditional Moves --*- tablegen -*--===//
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
7 //===----------------------------------------------------------------------===//
11 //===----------------------------------------------------------------------===//
201 defm : MovzPats1<GPR32, GPR32, MOVZ_I_I, XOR>, INSN_MIPS4_32_NOT_32R6_64R6;
210 defm : MovzPats1<GPR32, GPR64, MOVZ_I_I64, XOR>,
223 defm : MovnPats<GPR32, GPR32, MOVN_I_I, XOR>, INSN_MIPS4_32_NOT_32R6_64R6;
225 defm : MovnPats<GPR32, GPR64, MOVN_I_I64, XOR>, INSN_MIPS4_32_NOT_32R6_64R6,
234 defm : MovzPats1<GPR32, FGR32, MOVZ_I_S, XOR>, INSN_MIPS4_32_NOT_32R6_64R6;
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/freebsd/contrib/llvm-project/clang/lib/Headers/
H A Draointintrin.h1 /*===----------------------- raointintrin.h - RAOINT ------------------------===
3 * Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
5 * SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
7 *===-----------------------------------------------------------------------===
20 /// Atomically add a 32-bit value at memory operand \a __A and a 32-bit \a __B,
31 /// A pointer to a 32-bit memory location.
33 /// A 32-bit integer value.
42 /// Atomically and a 32-bit value at memory operand \a __A and a 32-bit \a __B,
53 /// A pointer to a 32-bit memory location.
55 /// A 32-bit integer value.
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H A Diso646.h1 /*===---- iso646.h - Standard header for alternate spellings of operators---===
3 * Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
5 * SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
7 *===-----------------------------------------------------------------------===
26 #define xor ^ macro
/freebsd/crypto/openssl/crypto/aes/asm/
H A Dvpaes-armv8.pl2 # Copyright 2015-2020 The OpenSSL Project Authors. All Rights Reserved.
11 ## Constant-time SSSE3 AES core implementation.
24 # SoC based on Cortex-A53 that doesn't have crypto extensions.
26 # CBC enc ECB enc/dec(*) [bit-sliced enc/dec]
27 # Cortex-A53 21.5 18.1/20.6 [17.5/19.8 ]
28 # Cortex-A57 36.0(**) 20.4/24.9(**) [14.4/16.6 ]
29 # X-Gene 45.9(**) 45.8/57.7(**) [33.1/37.6(**) ]
37 # (**) these results are worse than scalar compiler-generated
38 # code, but it's constant-time and therefore preferred;
47 ( $xlate="${dir}arm-xlate.pl" and -f $xlate ) or
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H A Dvpaes-ppc.pl2 # Copyright 2013-2020 The OpenSSL Project Authors. All Rights Reserved.
11 ## Constant-time SSSE3 AES core implementation.
21 # 128-bit key.
23 # aes-ppc.pl this
32 # it in-line. Secondly it, being transliterated from
33 # vpaes-x86_64.pl, relies on "nested inversion" better suited
60 $FRAME=6*$SIZE_T+13*16; # 13*16 is for v20-v31 offload
63 ( $xlate="${dir}ppc-xlate.pl" and -f $xlate ) or
64 ( $xlate="${dir}../../perlasm/ppc-xlate.pl" and -f $xlate) or
65 die "can't locate ppc-xlate.pl";
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/freebsd/sys/crypto/openssl/aarch64/
H A Dvpaes-armv8.S1 /* Do not modify. This file is auto-generated from vpaes-armv8.pl. */
94 .size _vpaes_consts,.-_vpaes_consts
99 // Fills register %r10 -> .aes_consts (so you can -fPIC)
100 // and %xmm9-%xmm15 as specified below.
111 .size _vpaes_encrypt_preheat,.-_vpaes_encrypt_preheat
116 // AES-encrypt %xmm0.
120 // %xmm9-%xmm15 as in _vpaes_preheat
124 // Clobbers %xmm1-%xmm5, %r9, %r10, %r11, %rax
125 // Preserves %xmm6 - %xmm8 so you get some local vectors
140 tbl v2.16b, {v21.16b}, v0.16b // vpshufb %xmm0, %xmm3, %xmm2
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/freebsd/contrib/bearssl/src/symcipher/
H A Daes_pwr8_cbcenc.c35 ctx->vtable = &br_aes_pwr8_cbcenc_vtable; in br_aes_pwr8_cbcenc_init()
36 ctx->num_rounds = br_aes_pwr8_keysched(ctx->skey.skni, key, len); in br_aes_pwr8_cbcenc_init()
96 * Load next plaintext word and XOR with current IV. in cbcenc_128()
137 : "v0", "v1", "v2", "v3", "v4", "v5", "v6", "v7", "v8", "v9", in cbcenc_128()
204 * Load next plaintext word and XOR with current IV. in cbcenc_192()
247 : "v0", "v1", "v2", "v3", "v4", "v5", "v6", "v7", "v8", "v9", in cbcenc_192()
318 * Load next plaintext word and XOR with current IV. in cbcenc_256()
363 : "v0", "v1", "v2", "v3", "v4", "v5", "v6", "v7", "v8", "v9", in cbcenc_256()
375 switch (ctx->num_rounds) { in br_aes_pwr8_cbcenc_run()
377 cbcenc_128(ctx->skey.skni, iv, data, len); in br_aes_pwr8_cbcenc_run()
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H A Daes_pwr8.c58 * v0 = all-zero word in key_schedule_128()
59 * v1 = constant -8 / +8, copied into four words in key_schedule_128()
60 * v2 = current subkey in key_schedule_128()
68 vspltisw(1, -8) in key_schedule_128()
99 /* Compute SubWord(RotWord(temp)) xor Rcon (into v4, splat) */ in key_schedule_128()
110 /* XOR words for next subkey */ in key_schedule_128()
141 : "v0", "v1", "v2", "v3", "v4", "v5", "v6", "v7", "ctr", "memory" in key_schedule_128()
167 * v0 = all-zero word in key_schedule_192()
168 * v1 = constant -8 / +8, copied into four words in key_schedule_192()
169 * v2, v3 = current subkey in key_schedule_192()
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/freebsd/contrib/llvm-project/llvm/lib/Target/SystemZ/
H A DSystemZTDC.cpp1 //===-- SystemZTDC.cpp - Utilize Test Data Class instruction --------------===//
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
7 //===----------------------------------------------------------------------===//
14 // 1: fcmp pred X, 0 -> tdc X, mask
15 // 2: fcmp pred X, +-inf -> tdc X, mask
16 // 3: fcmp pred X, +-minnorm -> tdc X, mask
17 // 4: tdc (fabs X), mask -> tdc X, newmask
18 // 5: icmp slt (bitcast float X to int), 0 -> tdc X, mask [ie. signbit]
19 // 6: icmp sgt (bitcast float X to int), -1 -> tdc X, mask
[all …]
/freebsd/contrib/llvm-project/llvm/lib/Target/LoongArch/
H A DLoongArchExpandAtomicPseudoInsts.cpp1 //==- LoongArchExpandAtomicPseudoInsts.cpp - Expand atomic pseudo instrs. -===//
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
7 //===--
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