Lines Matching +full:xor +full:- +full:v2

1 //===- X86FixupSetCC.cpp - fix zero-extension of setcc patterns -----------===//
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
7 //===----------------------------------------------------------------------===//
9 // This file defines a pass that fixes zero-extension of setcc patterns.
18 // xor %eax, %eax; seta %al
23 // if feature zero-upper is available. It's faster than the xor+setcc sequence.
24 // When r16-r31 is used, it even encodes shorter.
25 //===----------------------------------------------------------------------===//
37 #define DEBUG_TYPE "x86-fixup-setcc"
71   TII = ST->getInstrInfo();  in runOnMachineFunction()
90       for (auto &Use : MRI->use_instructions(Reg0))  in runOnMachineFunction()
105       if (FlagsDefMI->readsRegister(X86::EFLAGS, /*TRI=*/nullptr))  in runOnMachineFunction()
108       // On 32-bit, we need to be careful to force an ABCD register.  in runOnMachineFunction()
110           ST->is64Bit() ? &X86::GR32RegClass : &X86::GR32_ABCDRegClass;  in runOnMachineFunction()
111       if (!MRI->constrainRegClass(ZExt->getOperand(0).getReg(), RC)) {  in runOnMachineFunction()
123       Register ZeroReg = MRI->createVirtualRegister(RC);  in runOnMachineFunction()
124       if (ST->hasZU()) {  in runOnMachineFunction()
125         MI.setDesc(TII->get(X86::SETZUCCr));  in runOnMachineFunction()
126         BuildMI(*ZExt->getParent(), ZExt, ZExt->getDebugLoc(),  in runOnMachineFunction()
127                 TII->get(TargetOpcode::IMPLICIT_DEF), ZeroReg);  in runOnMachineFunction()
130         BuildMI(MBB, FlagsDefMI, MI.getDebugLoc(), TII->get(X86::MOV32r0),  in runOnMachineFunction()
134       BuildMI(*ZExt->getParent(), ZExt, ZExt->getDebugLoc(),  in runOnMachineFunction()
135               TII->get(X86::INSERT_SUBREG), ZExt->getOperand(0).getReg())  in runOnMachineFunction()
144     I->eraseFromParent();  in runOnMachineFunction()