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/freebsd/sys/dev/clk/rockchip/
H A Drk3568_pmucru.c74 PLIST(mux_pll_p) = { "xin24m" };
75 PLIST(xin24m_32k_p) = { "xin24m", "clk_rtc_32k" };
76 PLIST(sclk_uart0_p) = { "sclk_uart0_div", "sclk_uart0_frac", "xin24m" };
89 PLIST(clk_pwm0_p) = { "xin24m", "clk_pdpmu" };
94 LINK("xin24m"),
110 CDIV(0, "xin_osc0_div_div", "xin24m", 0, 0, 0, 5),
114 FRACT(0, "clk_osc0_div32k", "xin24m", 0, 1),
167 GATE(CLK_PMU, "clk_pmu", "xin24m", 0, 7),
178 GATE(CLK_CAPTURE_PWM0_NDFT, "clk_capture_pwm0_ndft", "xin24m", 1, 8),
182 GATE(CLK_PMUPVTM, "clk_pmupvtm", "xin24m", 1, 12),
[all …]
H A Drk3568_cru.c165 PLIST(mux_pll_p) = { "xin24m" };
166 PLIST(mux_usb480m_p) = { "xin24m", "usb480m_phy", "clk_rtc_32k" };
184 PLIST(sclk_uart1_p) = { "clk_uart1_src", "clk_uart1_frac", "xin24m" };
185 PLIST(sclk_uart2_p) = { "clk_uart2_src", "clk_uart2_frac", "xin24m" };
186 PLIST(sclk_uart3_p) = { "clk_uart3_src", "clk_uart3_frac", "xin24m" };
187 PLIST(sclk_uart4_p) = { "clk_uart4_src", "clk_uart4_frac", "xin24m" };
188 PLIST(sclk_uart5_p) = { "clk_uart5_src", "clk_uart5_frac", "xin24m" };
189 PLIST(sclk_uart6_p) = { "clk_uart6_src", "clk_uart6_frac", "xin24m" };
190 PLIST(sclk_uart7_p) = { "clk_uart7_src", "clk_uart7_frac", "xin24m" };
191 PLIST(sclk_uart8_p) = { "clk_uart8_src", "clk_uart8_frac", "xin24m" };
[all …]
H A Drk3288_cru.c89 GATE(0, "sclk_acc_efuse", "xin24m", 0, 12),
111 GATE(SCLK_TIMER5, "sclk_timer5", "xin24m", 1, 5),
112 GATE(SCLK_TIMER4, "sclk_timer4", "xin24m", 1, 4),
113 GATE(SCLK_TIMER3, "sclk_timer3", "xin24m", 1, 3),
114 GATE(SCLK_TIMER2, "sclk_timer2", "xin24m", 1, 2),
115 GATE(SCLK_TIMER1, "sclk_timer1", "xin24m", 1, 1),
116 GATE(SCLK_TIMER0, "sclk_timer0", "xin24m", 1, 0),
169 GATE(SCLK_MIPIDSI_24M, "sclk_mipidsi_24m", "xin24m", 5, 15),
171 GATE(SCLK_PS2C, "sclk_ps2c", "xin24m", 5, 13),
172 GATE(SCLK_HDMI_HDCP, "sclk_hdmi_hdcp", "xin24m", 5, 12),
[all …]
H A Drk3399_cru.c58 GATE(SCLK_PVTM_CORE_L, "clk_pvtm_core_l", "xin24m", 0, 7),
69 GATE(SCLK_PVTM_CORE_B, "clk_pvtm_core_b", "xin24m", 1, 7),
105 GATE(SCLK_PVTM_DDR, "clk_pvtm_ddr", "xin24m", 4, 11),
141 GATE(SCLK_USB2PHY1_REF, "clk_usb2phy1_ref", "xin24m", 6, 6),
142 GATE(SCLK_USB2PHY0_REF, "clk_usb2phy0_ref", "xin24m", 6, 5),
216 GATE(SCLK_MIPIDPHY_CFG, "clk_mipidphy_cfg", "xin24m", 11, 15),
217 GATE(SCLK_MIPIDPHY_REF, "clk_mipidphy_ref", "xin24m", 11, 14),
224 GATE(SCLK_HDMI_SFR, "clk_hdmi_sfr", "xin24m", 11, 6),
245 GATE(SCLK_USB3OTG1_REF, "clk_usb3otg1_ref", "xin24m", 12, 2),
246 GATE(SCLK_USB3OTG0_REF, "clk_usb3otg0_ref", "xin24m", 12, 1),
[all …]
H A Drk3328_cru.c322 GATE(SCLK_USB3OTG_REF, "clk_usb3_otg0_ref", "xin24m", 4, 7),
333 GATE(SCLK_HDMI_SFC, "clk_hdmi_sfc", "xin24m", 5, 4),
363 GATE(SCLK_TIMER0, "sclk_timer0", "xin24m", 8, 5),
364 GATE(SCLK_TIMER1, "sclk_timer1", "xin24m", 8, 6),
365 GATE(SCLK_TIMER2, "sclk_timer2", "xin24m", 8, 7),
366 GATE(SCLK_TIMER3, "sclk_timer3", "xin24m", 8, 8),
367 GATE(SCLK_TIMER4, "sclk_timer4", "xin24m", 8, 9),
368 GATE(SCLK_TIMER5, "sclk_timer5", "xin24m", 8, 10),
639 PLIST(pll_src_p) = {"xin24m"};
640 PLIST(xin24m_rtc32k_p) = {"xin24m", "clk_rtc32k"};
[all …]
H A Drk3399_pmucru.c758 PLIST(xin24m_p) = {"xin24m"};
759 PLIST(xin24m_xin32k_p) = {"xin24m", "xin32k"};
760 PLIST(xin24m_ppll_p) = {"xin24m", "ppll"};
761 PLIST(uart4_p) = {"clk_uart4_c", "clk_uart4_frac", "xin24m"};
/freebsd/sys/contrib/device-tree/Bindings/clock/
H A Drockchip,px30-cru.yaml25 - "xin24m" - crystal input - required
54 - const: xin24m
104 clocks = <&xin24m>;
105 clock-names = "xin24m";
114 clocks = <&xin24m>, <&pmucru PLL_GPLL>;
115 clock-names = "xin24m", "gpll";
H A Drockchip,rk3228-cru.yaml25 - "xin24m" - crystal input - required
49 const: xin24m
H A Drockchip,rk3036-cru.yaml25 - "xin24m" - crystal input - required
47 const: xin24m
H A Drockchip,rk3308-cru.yaml25 - "xin24m" - crystal input - required
51 const: xin24m
H A Drockchip,rk3368-cru.yaml25 - "xin24m" - crystal input - required
53 const: xin24m
H A Drockchip,rk3188-cru.yaml25 - "xin24m" - crystal input - required
53 const: xin24m
H A Drockchip,rv1108-cru.yaml25 - "xin24m" - crystal input - required
50 const: xin24m
H A Drockchip,rk3399-cru.yaml25 - "xin24m" - crystal input - required,
52 const: xin24m
H A Drockchip,rk3288-cru.yaml32 - "xin24m" - crystal input - required,
60 const: xin24m
H A Drockchip,px30-cru.txt16 - "xin24m" for both PMUCRU and CRU
37 - "xin24m" - crystal input - required,
H A Drockchip,rk3576-cru.yaml38 - const: xin24m
H A Drockchip,rv1126-cru.yaml37 const: xin24m
H A Drockchip,rk3036-cru.txt31 - "xin24m" - crystal input - required,
H A Drockchip,rk3588-cru.yaml42 - const: xin24m
/freebsd/sys/contrib/device-tree/src/arm/rockchip/
H A Drk3036.dtsi83 xin24m: oscillator { label
86 clock-output-names = "xin24m";
333 clocks = <&xin24m>;
334 clock-names = "xin24m";
430 clocks = <&cru PCLK_TIMER>, <&xin24m>;
H A Drv1108.dtsi81 xin24m: oscillator { label
84 clock-output-names = "xin24m";
292 clocks = <&cru PCLK_TIMER>, <&xin24m>;
444 clocks = <&xin24m>;
445 clock-names = "xin24m";
/freebsd/sys/contrib/device-tree/Bindings/timer/
H A Drockchip,rk-timer.txt25 clocks = <&xin24m>, <&cru PCLK_TIMER>;
H A Drockchip,rk-timer.yaml64 clocks = <&cru PCLK_TIMER>, <&xin24m>;
/freebsd/sys/contrib/device-tree/Bindings/phy/
H A Dphy-rockchip-inno-hdmi.txt28 clocks = <&cru PCLK_HDMI_PHY>, <&xin24m>, <&cru DCLK_HDMIPHY>;

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