Lines Matching full:xin24m
58 GATE(SCLK_PVTM_CORE_L, "clk_pvtm_core_l", "xin24m", 0, 7),
69 GATE(SCLK_PVTM_CORE_B, "clk_pvtm_core_b", "xin24m", 1, 7),
105 GATE(SCLK_PVTM_DDR, "clk_pvtm_ddr", "xin24m", 4, 11),
141 GATE(SCLK_USB2PHY1_REF, "clk_usb2phy1_ref", "xin24m", 6, 6),
142 GATE(SCLK_USB2PHY0_REF, "clk_usb2phy0_ref", "xin24m", 6, 5),
216 GATE(SCLK_MIPIDPHY_CFG, "clk_mipidphy_cfg", "xin24m", 11, 15),
217 GATE(SCLK_MIPIDPHY_REF, "clk_mipidphy_ref", "xin24m", 11, 14),
224 GATE(SCLK_HDMI_SFR, "clk_hdmi_sfr", "xin24m", 11, 6),
245 GATE(SCLK_USB3OTG1_REF, "clk_usb3otg1_ref", "xin24m", 12, 2),
246 GATE(SCLK_USB3OTG0_REF, "clk_usb3otg0_ref", "xin24m", 12, 1),
264 GATE(SCLK_PVTM_GPU, "aclk_pvtm_gpu", "xin24m", 13, 1),
319 GATE(0, "clk_ddr_mon_timer", "xin24m", 18, 14),
431 GATE(SCLK_TIMER11, "clk_timer11", "xin24m", 26, 11),
432 GATE(SCLK_TIMER10, "clk_timer10", "xin24m", 26, 10),
433 GATE(SCLK_TIMER09, "clk_timer09", "xin24m", 26, 9),
434 GATE(SCLK_TIMER08, "clk_timer08", "xin24m", 26, 8),
435 GATE(SCLK_TIMER07, "clk_timer07", "xin24m", 26, 7),
436 GATE(SCLK_TIMER06, "clk_timer06", "xin24m", 26, 6),
437 GATE(SCLK_TIMER05, "clk_timer05", "xin24m", 26, 5),
438 GATE(SCLK_TIMER04, "clk_timer04", "xin24m", 26, 4),
439 GATE(SCLK_TIMER03, "clk_timer03", "xin24m", 26, 3),
440 GATE(SCLK_TIMER02, "clk_timer02", "xin24m", 26, 2),
441 GATE(SCLK_TIMER01, "clk_timer01", "xin24m", 26, 1),
442 GATE(SCLK_TIMER00, "clk_timer00", "xin24m", 26, 0),
697 PLIST(pll_src_p) = {"xin24m", "xin32k"};
711 PLIST(pll_src_cpll_gpll_npll_24m_p) = {"cpll", "gpll", "npll", "xin24m" };
714 PLIST(pll_src_cpll_gpll_npll_upll_24m_p)= { "cpll", "gpll", "npll", "upll", "xin24m" };
715 PLIST(pll_src_cpll_gpll_npll_ppll_upll_24m_p) = { "cpll", "gpll", "npll", "ppll", "upll", "xin24m"…
727 PLIST(clk_cif_p) = {"clk_cifout_src", "xin24m"};
729 PLIST(pll_src_24m_usbphy480m_p) = { "xin24m", "clk_usbphy_480m"};
730 PLIST(pll_src_24m_pciephy_p) = { "xin24m", "clk_pciephy_ref100m"};
731 PLIST(pll_src_24m_32k_cpll_gpll_p)= {"xin24m", "xin32k", "cpll", "gpll"};
745 PLIST(clk_testout1_p) = { "clk_testout1_pll_src", "xin24m" };
746 PLIST(clk_testout2_p) = { "clk_testout2_pll_src", "xin24m" };
764 PLIST(uart0_p)= {"clk_uart0_div", "clk_uart0_frac", "xin24m"};
765 PLIST(uart1_p)= {"clk_uart1_div", "clk_uart1_frac", "xin24m"};
766 PLIST(uart2_p)= {"clk_uart2_div", "clk_uart2_frac", "xin24m"};
767 PLIST(uart3_p)= {"clk_uart3_div", "clk_uart3_frac", "xin24m"};
771 LINK("xin24m"),
773 FFACT(0, "xin12m", "xin24m", 1, 2),
951 CDIV(0, "clk_saradc_c", "xin24m", 0,
1130 CDIV(0, "clk_test_24m", "xin24m", 0,