Lines Matching full:xin24m

89 	GATE(0, "sclk_acc_efuse", "xin24m",			0, 12),
111 	GATE(SCLK_TIMER5, "sclk_timer5", "xin24m",		1, 5),
112 	GATE(SCLK_TIMER4, "sclk_timer4", "xin24m",		1, 4),
113 	GATE(SCLK_TIMER3, "sclk_timer3", "xin24m",		1, 3),
114 	GATE(SCLK_TIMER2, "sclk_timer2", "xin24m",		1, 2),
115 	GATE(SCLK_TIMER1, "sclk_timer1", "xin24m",		1, 1),
116 	GATE(SCLK_TIMER0, "sclk_timer0", "xin24m",		1, 0),
169 	GATE(SCLK_MIPIDSI_24M, "sclk_mipidsi_24m", "xin24m",	5, 15),
171 	GATE(SCLK_PS2C, "sclk_ps2c", "xin24m",			5, 13),
172 	GATE(SCLK_HDMI_HDCP, "sclk_hdmi_hdcp", "xin24m",	5, 12),
174 	GATE(SCLK_PVTM_GPU, "sclk_pvtm_gpu", "xin24m",		5, 10),
175 	GATE(SCLK_PVTM_CORE, "sclk_pvtm_core", "xin24m",	5, 9),
291 	GATE(SCLK_LCDC_PWM1, "sclk_lcdc_pwm1", "xin24m",	13, 11),
292 	GATE(SCLK_LCDC_PWM0, "sclk_lcdc_pwm0", "xin24m",	13, 10),
296 	GATE(SCLK_OTGPHY2, "sclk_otgphy2", "xin24m",		13, 6),
297 	GATE(SCLK_OTGPHY1, "sclk_otgphy1", "xin24m",		13, 5),
298 	GATE(SCLK_OTGPHY0, "sclk_otgphy0", "xin24m",		13, 4),
527 PLIST(pll_src_p) = {"xin24m", "xin24m", "xin32k"};
538 PLIST(mmc_p) = {"cpll", "gpll", "xin24m", "xin24m"};
543 PLIST(uart0_p) = {"uart0_src", "uart0_frac", "xin24m"};
544 PLIST(uart1_p) = {"uart1_src", "uart1_frac", "xin24m"};
545 PLIST(uart2_p) = {"uart2_src", "uart2_frac", "xin24m"};
546 PLIST(uart3_p) = {"uart3_src", "uart3_frac", "xin24m"};
547 PLIST(uart4_p) = {"uart4_src", "uart4_frac", "xin24m"};
548 PLIST(vip_out_p) = {"vip_src", "xin24m"};
551 PLIST(edp_24m_p) = {"ext_edp_24m", "xin24m"};
561 	LINK("xin24m"),
578 	FFACT(0, "xin12m", "xin24m", 1, 2),
733 	CDIV(0, "sclk_saradc_s", "xin24m", 0,