/linux/drivers/usb/host/ |
H A D | Makefile | 6 # tell define_trace.h where to find the xhci trace header 14 xhci-hcd-y := xhci.o xhci-mem.o xhci-ext-caps.o 15 xhci-hcd-y += xhci-ring.o xhci-hub.o xhci-dbg.o 16 xhci-hcd-y += xhci-trace.o 19 xhci-hcd-y += xhci-dbgcap.o xhci-dbgtty.o 22 xhci-mtk-hcd-y := xhci-mtk.o xhci-mtk-sch.o 24 xhci-plat-hcd-y := xhci-plat.o 26 xhci-plat-hcd-y += xhci-mvebu.o 29 xhci-hcd-y += xhci-debugfs.o 32 xhci-rcar-hcd-y += xhci-rcar.o [all …]
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H A D | xhci-debugfs.c | 3 * xhci-debugfs.c - xHCI debugfs interface 13 #include "xhci.h" 14 #include "xhci-debugfs.h" 86 static struct xhci_regset *xhci_debugfs_alloc_regset(struct xhci_hcd *xhci) in xhci_debugfs_alloc_regset() argument 99 list_add_tail(®set->list, &xhci->regset_list); in xhci_debugfs_alloc_regset() 114 static void xhci_debugfs_regset(struct xhci_hcd *xhci, u32 base, in xhci_debugfs_regset() argument 122 struct usb_hcd *hcd = xhci_to_hcd(xhci); in xhci_debugfs_regset() 124 rgs = xhci_debugfs_alloc_regset(xhci); in xhci_debugfs_regset() 141 static void xhci_debugfs_extcap_regset(struct xhci_hcd *xhci, int cap_id, in xhci_debugfs_extcap_regset() argument 148 void __iomem *base = &xhci->cap_regs->hc_capbase; in xhci_debugfs_extcap_regset() [all …]
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H A D | xhci-histb.c | 3 * xHCI host controller driver for HiSilicon STB SoCs 19 #include "xhci.h" 69 * refer to xHCI spec in xhci_histb_config() 193 struct xhci_hcd *xhci; in xhci_histb_probe() local 252 xhci = hcd_to_xhci(hcd); in xhci_histb_probe() 256 xhci->main_hcd = hcd; in xhci_histb_probe() 257 xhci->shared_hcd = usb_create_shared_hcd(driver, dev, dev_name(dev), in xhci_histb_probe() 259 if (!xhci->shared_hcd) { in xhci_histb_probe() 265 xhci->quirks |= XHCI_HW_LPM_DISABLE; in xhci_histb_probe() 268 xhci->quirks |= XHCI_LPM_SUPPORT; in xhci_histb_probe() [all …]
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H A D | xhci-mtk.c | 3 * MediaTek xHCI Host Controller Driver 24 #include "xhci.h" 25 #include "xhci-mtk.h" 61 /* xHCI CSR */ 145 if (!of_device_is_compatible(dev->of_node, "mediatek,mt8195-xhci")) in xhci_mtk_set_frame_interval() 451 static void xhci_mtk_quirks(struct device *dev, struct xhci_hcd *xhci) in xhci_mtk_quirks() argument 453 struct usb_hcd *hcd = xhci_to_hcd(xhci); in xhci_mtk_quirks() 456 xhci->quirks |= XHCI_MTK_HOST; in xhci_mtk_quirks() 461 xhci->quirks |= XHCI_SPURIOUS_SUCCESS; in xhci_mtk_quirks() 463 xhci->quirks |= XHCI_LPM_SUPPORT; in xhci_mtk_quirks() [all …]
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H A D | xhci-debugfs.h | 3 * xhci-debugfs.h - xHCI debugfs interface 107 void xhci_debugfs_init(struct xhci_hcd *xhci); 108 void xhci_debugfs_exit(struct xhci_hcd *xhci); 111 void xhci_debugfs_create_slot(struct xhci_hcd *xhci, int slot_id); 112 void xhci_debugfs_remove_slot(struct xhci_hcd *xhci, int slot_id); 113 void xhci_debugfs_create_endpoint(struct xhci_hcd *xhci, 116 void xhci_debugfs_remove_endpoint(struct xhci_hcd *xhci, 119 void xhci_debugfs_create_stream_files(struct xhci_hcd *xhci, 123 static inline void xhci_debugfs_init(struct xhci_hcd *xhci) { } in xhci_debugfs_init() argument 124 static inline void xhci_debugfs_exit(struct xhci_hcd *xhci) { } in xhci_debugfs_exit() argument [all …]
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H A D | xhci-ext-caps.c | 3 * XHCI extended capability handling 11 #include "xhci.h" 28 static int xhci_create_intel_xhci_sw_pdev(struct xhci_hcd *xhci, u32 cap_offset) in xhci_create_intel_xhci_sw_pdev() argument 30 struct usb_hcd *hcd = xhci_to_hcd(xhci); in xhci_create_intel_xhci_sw_pdev() 39 xhci_err(xhci, "couldn't allocate %s platform device\n", in xhci_create_intel_xhci_sw_pdev() 84 int xhci_ext_cap_init(struct xhci_hcd *xhci) in xhci_ext_cap_init() argument 86 void __iomem *base = &xhci->cap_regs->hc_capbase; in xhci_ext_cap_init() 97 if (xhci->quirks & XHCI_INTEL_USB_ROLE_SW) { in xhci_ext_cap_init() 98 ret = xhci_create_intel_xhci_sw_pdev(xhci, in xhci_ext_cap_init()
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H A D | xhci-dbg.c | 3 * xHCI host controller driver 11 #include "xhci.h" 13 char *xhci_get_slot_state(struct xhci_hcd *xhci, in xhci_get_slot_state() argument 16 struct xhci_slot_ctx *slot_ctx = xhci_get_slot_ctx(xhci, ctx); in xhci_get_slot_state() 22 void xhci_dbg_trace(struct xhci_hcd *xhci, void (*trace)(struct va_format *), in xhci_dbg_trace() argument 31 xhci_dbg(xhci, "%pV\n", &vaf); in xhci_dbg_trace()
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H A D | xhci-rzv2m.c | 3 * xHCI host controller driver for RZ/V2M 9 #include "xhci.h" 10 #include "xhci-plat.h" 11 #include "xhci-rzv2m.h"
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H A D | xhci-mtk-sch.c | 13 #include "xhci.h" 14 #include "xhci-mtk.h" 130 struct xhci_hcd *xhci = hcd_to_xhci(mtk->hcd); in get_bw_info() local 134 virt_dev = xhci->devs[udev->slot_id]; in get_bw_info() 147 bw_index = virt_dev->rhub_port->hw_portnum + xhci->usb3_rhub.num_ports; in get_bw_info() 332 * xHCI spec section6.2.3.4 in setup_sch_info() 887 struct xhci_hcd *xhci = hcd_to_xhci(mtk->hcd); in xhci_mtk_sch_init() local 892 num_usb_bus = xhci->usb3_rhub.num_ports * 2 + xhci->usb2_rhub.num_ports; in xhci_mtk_sch_init() 915 struct xhci_hcd *xhci = hcd_to_xhci(hcd); in add_ep_quirk() local 921 virt_dev = xhci->devs[udev->slot_id]; in add_ep_quirk() [all …]
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H A D | xhci-tegra.c | 3 * NVIDIA Tegra xHCI host controller driver 34 #include "xhci.h" 993 dev_err(tegra->dev, "XHCI Controller not ready. Falcon state: 0x%x\n", in tegra_xusb_wait_for_falcon() 1292 struct xhci_hcd *xhci = hcd_to_xhci(tegra->hcd); in tegra_xhci_set_port_power() local 1293 struct usb_hcd *hcd = main ? xhci->main_hcd : xhci->shared_hcd; in tegra_xhci_set_port_power() 1345 struct xhci_hcd *xhci = hcd_to_xhci(tegra->hcd); in tegra_xhci_id_work() local 1372 xhci->shared_hcd, GetPortStatus, in tegra_xhci_id_work() 1541 struct xhci_hcd *xhci; in tegra_xusb_probe() local 1819 xhci = hcd_to_xhci(tegra->hcd); in tegra_xusb_probe() 1821 xhci->shared_hcd = usb_create_shared_hcd(&tegra_xhci_hc_driver, in tegra_xusb_probe() [all …]
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/linux/Documentation/devicetree/bindings/usb/ |
H A D | renesas,usb-xhci.yaml | 4 $id: http://devicetree.org/schemas/usb/renesas,usb-xhci.yaml# 7 title: Renesas USB xHCI controllers 18 - renesas,xhci-r8a7742 # RZ/G1H 19 - renesas,xhci-r8a7743 # RZ/G1M 20 - renesas,xhci-r8a7744 # RZ/G1N 21 - renesas,xhci-r8a7790 # R-Car H2 22 - renesas,xhci-r8a7791 # R-Car M2-W 23 - renesas,xhci-r8a7793 # R-Car M2-N 24 - const: renesas,rcar-gen2-xhci # R-Car Gen2 and RZ/G1 27 - renesas,xhci-r8a774a1 # RZ/G2M [all …]
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H A D | generic-xhci.yaml | 4 $id: http://devicetree.org/schemas/usb/generic-xhci.yaml# 7 title: USB xHCI Controller 15 - description: Generic xHCI device 16 const: generic-xhci 20 - marvell,armada3700-xhci 21 - marvell,armada-375-xhci 22 - marvell,armada-380-xhci 23 - marvell,armada-8k-xhci 24 - const: generic-xhci 28 - brcm,bcm2711-xhci [all …]
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H A D | mediatek,mtk-xhci.yaml | 5 $id: http://devicetree.org/schemas/usb/mediatek,mtk-xhci.yaml# 8 title: MediaTek USB3 xHCI 14 - $ref: usb-xhci.yaml 18 case 1: only supports xHCI driver; 19 case 2: supports dual-role mode, and the host is based on xHCI driver. 26 - mediatek,mt2701-xhci 27 - mediatek,mt2712-xhci 28 - mediatek,mt7622-xhci 29 - mediatek,mt7623-xhci 30 - mediatek,mt7629-xhci [all …]
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H A D | nvidia,tegra234-xusb.yaml | 7 title: NVIDIA Tegra234 xHCI controller 14 The Tegra xHCI controller supports both USB2 and USB3 interfaces exposed by 15 the Tegra XUSB pad controller. The xHCI controller controls up to eight 24 - description: xHCI host registers 36 - description: xHCI host interrupt 79 the USB pads used by the XHCI controller 112 - $ref: usb-xhci.yaml
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H A D | mediatek,mtu3.yaml | 18 based on xHCI. 174 layer between xHCI and SPM, the field should always be 3 cells long. 208 $ref: /schemas/usb/mediatek,mtk-xhci.yaml# 210 The xhci should be added as subnode to mtu3 as shown in the following 257 xhci: usb@11270000 { 258 compatible = "mediatek,mt8173-xhci", "mediatek,mtk-xhci"; 290 compatible = "mediatek,mt2712-xhci", "mediatek,mtk-xhci"; 327 compatible = "mediatek,mt8183-xhci", "mediatek,mtk-xhci";
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H A D | cdns,usb3.yaml | 19 - description: XHCI Host controller registers 25 - const: xhci 31 - description: XHCI host controller interrupt 35 cleared by xhci core, this interrupt is optional 103 reg-names = "otg", "xhci", "dev";
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H A D | nvidia,tegra186-xusb.yaml | 7 title: NVIDIA Tegra186 xHCI controller 13 description: The Tegra xHCI controller supports both USB2 and USB3 interfaces 22 - description: base and length of the xHCI host registers 32 - description: xHCI host interrupt 75 the USB pads used by the XHCI controller 126 - $ref: usb-xhci.yaml
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H A D | nvidia,tegra194-xusb.yaml | 7 title: NVIDIA Tegra194 xHCI controller 13 description: The Tegra xHCI controller supports both USB2 and USB3 interfaces 22 - description: base and length of the xHCI host registers 32 - description: xHCI host interrupt 75 the USB pads used by the XHCI controller 127 - $ref: usb-xhci.yaml
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/linux/drivers/usb/dwc3/ |
H A D | host.c | 16 #include "../host/xhci-port.h" 17 #include "../host/xhci-ext-caps.h" 18 #include "../host/xhci-caps.h" 19 #include "../host/xhci-plat.h" 38 /* xhci regs is not mapped yet, do it temperary here */ in dwc3_power_off_all_roothub_ports() 59 dev_err(dwc->dev, "xhci base reg invalid\n"); in dwc3_power_off_all_roothub_ports() 130 struct platform_device *xhci; in dwc3_host_init() local 136 * mode to avoid VBUS glitch happen when xhci get reset later. in dwc3_host_init() 144 xhci = platform_device_alloc("xhci-hcd", PLATFORM_DEVID_AUTO); in dwc3_host_init() 145 if (!xhci) { in dwc3_host_init() [all …]
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/linux/Documentation/devicetree/bindings/phy/ |
H A D | realtek,usb2phy.yaml | 15 The USB 2.0 PHY driver is designed to support the XHCI controller. The SoCs 16 support multiple XHCI controllers. One PHY device node maps to one XHCI 20 The USB architecture includes three XHCI controllers. 21 Each XHCI maps to one USB 2.0 PHY and map one USB 3.0 PHY on some 23 XHCI controller#0 -- usb2phy -- phy#0 25 XHCI controller#1 -- usb2phy -- phy#0 26 XHCI controller#2 -- usb2phy -- phy#0 30 The USB architecture includes two XHCI controllers. 33 XHCI controller#0 -- usb2phy -- phy#0 34 XHCI controller#1 -- usb2phy -- phy#0 [all …]
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H A D | realtek,usb3phy.yaml | 15 The USB 3.0 PHY driver is designed to support the XHCI controller. The SoCs 16 support multiple XHCI controllers. One PHY device node maps to one XHCI 20 The USB architecture includes three XHCI controllers. 21 Each XHCI maps to one USB 2.0 PHY and map one USB 3.0 PHY on some 23 XHCI controller#0 -- usb2phy -- phy#0 25 XHCI controller#1 -- usb2phy -- phy#0 26 XHCI controller#2 -- usb2phy -- phy#0 30 The USB architecture includes three XHCI controllers. 31 Each XHCI maps to one USB 2.0 PHY and map one USB 3.0 PHY on controllers#2. 32 XHCI controller#0 -- usb2phy -- phy#0 [all …]
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H A D | brcm,brcmstb-usb-phy.yaml | 9 description: Broadcom's PHY that handles EHCI/OHCI and/or XHCI 27 - description: XHCI EC register 28 - description: XHCI GBL register 87 brcm,has-xhci: 88 description: Indicates the PHY has an XHCI PHY. 108 - brcm,has-xhci 166 brcm,has-xhci; 192 brcm,has-xhci;
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/linux/Documentation/ABI/testing/ |
H A D | sysfs-bus-pci-drivers-xhci_hcd | 5 xHCI compatible USB host controllers (i.e. super-speed 12 The DbC debug device shares a root port with xHCI host. 15 to xHCI. 21 port will roll back to the xHCI. 32 presented in the USB device descriptor by this xhci debug 45 presented in the USB device descriptor by this xhci debug 57 presented in the USB device descriptor by this xhci debug 70 presented in the USB Interface descriptor by the xhci debug
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/linux/drivers/usb/cdns3/ |
H A D | Kconfig | 47 Host controller is compliant with XHCI so it will use 48 standard XHCI driver. 117 very similar to XHCI controller. Therefore some algorithms 130 Host controller is compliant with XHCI so it uses 131 standard XHCI driver.
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/linux/Documentation/devicetree/bindings/sound/ |
H A D | qcom,q6usb.yaml | 15 XHCI host controller properly for enabling the offloaded audio stream. 18 the XHCI host controller. 36 Desired XHCI interrupter number to use. Depending on the audio DSP 37 on the platform, it will operate on a specific XHCI interrupter.
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