1*d6ef6887SStanley Chang# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) 2*d6ef6887SStanley Chang# Copyright 2023 Realtek Semiconductor Corporation 3*d6ef6887SStanley Chang%YAML 1.2 4*d6ef6887SStanley Chang--- 5*d6ef6887SStanley Chang$id: http://devicetree.org/schemas/phy/realtek,usb3phy.yaml# 6*d6ef6887SStanley Chang$schema: http://devicetree.org/meta-schemas/core.yaml# 7*d6ef6887SStanley Chang 8*d6ef6887SStanley Changtitle: Realtek DHC SoCs USB 3.0 PHY 9*d6ef6887SStanley Chang 10*d6ef6887SStanley Changmaintainers: 11*d6ef6887SStanley Chang - Stanley Chang <stanley_chang@realtek.com> 12*d6ef6887SStanley Chang 13*d6ef6887SStanley Changdescription: | 14*d6ef6887SStanley Chang Realtek USB 3.0 PHY support the digital home center (DHC) RTD series SoCs. 15*d6ef6887SStanley Chang The USB 3.0 PHY driver is designed to support the XHCI controller. The SoCs 16*d6ef6887SStanley Chang support multiple XHCI controllers. One PHY device node maps to one XHCI 17*d6ef6887SStanley Chang controller. 18*d6ef6887SStanley Chang 19*d6ef6887SStanley Chang RTD1295/RTD1619 SoCs USB 20*d6ef6887SStanley Chang The USB architecture includes three XHCI controllers. 21*d6ef6887SStanley Chang Each XHCI maps to one USB 2.0 PHY and map one USB 3.0 PHY on some 22*d6ef6887SStanley Chang controllers. 23*d6ef6887SStanley Chang XHCI controller#0 -- usb2phy -- phy#0 24*d6ef6887SStanley Chang |- usb3phy -- phy#0 25*d6ef6887SStanley Chang XHCI controller#1 -- usb2phy -- phy#0 26*d6ef6887SStanley Chang XHCI controller#2 -- usb2phy -- phy#0 27*d6ef6887SStanley Chang |- usb3phy -- phy#0 28*d6ef6887SStanley Chang 29*d6ef6887SStanley Chang RTD1319/RTD1619b SoCs USB 30*d6ef6887SStanley Chang The USB architecture includes three XHCI controllers. 31*d6ef6887SStanley Chang Each XHCI maps to one USB 2.0 PHY and map one USB 3.0 PHY on controllers#2. 32*d6ef6887SStanley Chang XHCI controller#0 -- usb2phy -- phy#0 33*d6ef6887SStanley Chang XHCI controller#1 -- usb2phy -- phy#0 34*d6ef6887SStanley Chang XHCI controller#2 -- usb2phy -- phy#0 35*d6ef6887SStanley Chang |- usb3phy -- phy#0 36*d6ef6887SStanley Chang 37*d6ef6887SStanley Chang RTD1319d SoCs USB 38*d6ef6887SStanley Chang The USB architecture includes three XHCI controllers. 39*d6ef6887SStanley Chang Each xhci maps to one USB 2.0 PHY and map one USB 3.0 PHY on controllers#0. 40*d6ef6887SStanley Chang XHCI controller#0 -- usb2phy -- phy#0 41*d6ef6887SStanley Chang |- usb3phy -- phy#0 42*d6ef6887SStanley Chang XHCI controller#1 -- usb2phy -- phy#0 43*d6ef6887SStanley Chang XHCI controller#2 -- usb2phy -- phy#0 44*d6ef6887SStanley Chang 45*d6ef6887SStanley Changproperties: 46*d6ef6887SStanley Chang compatible: 47*d6ef6887SStanley Chang enum: 48*d6ef6887SStanley Chang - realtek,rtd1295-usb3phy 49*d6ef6887SStanley Chang - realtek,rtd1319-usb3phy 50*d6ef6887SStanley Chang - realtek,rtd1319d-usb3phy 51*d6ef6887SStanley Chang - realtek,rtd1619-usb3phy 52*d6ef6887SStanley Chang - realtek,rtd1619b-usb3phy 53*d6ef6887SStanley Chang 54*d6ef6887SStanley Chang reg: 55*d6ef6887SStanley Chang maxItems: 1 56*d6ef6887SStanley Chang 57*d6ef6887SStanley Chang "#phy-cells": 58*d6ef6887SStanley Chang const: 0 59*d6ef6887SStanley Chang 60*d6ef6887SStanley Chang nvmem-cells: 61*d6ef6887SStanley Chang maxItems: 1 62*d6ef6887SStanley Chang description: A phandle to the tx lfps swing trim data provided by 63*d6ef6887SStanley Chang a nvmem device, if unspecified, default values shall be used. 64*d6ef6887SStanley Chang 65*d6ef6887SStanley Chang nvmem-cell-names: 66*d6ef6887SStanley Chang items: 67*d6ef6887SStanley Chang - const: usb_u3_tx_lfps_swing_trim 68*d6ef6887SStanley Chang 69*d6ef6887SStanley Chang realtek,amplitude-control-coarse-tuning: 70*d6ef6887SStanley Chang description: 71*d6ef6887SStanley Chang This adjusts the signal amplitude for normal operation and beacon LFPS. 72*d6ef6887SStanley Chang This value is a parameter for coarse tuning. 73*d6ef6887SStanley Chang For different boards, if the default value is inappropriate, this 74*d6ef6887SStanley Chang property can be assigned to adjust. 75*d6ef6887SStanley Chang $ref: /schemas/types.yaml#/definitions/uint32 76*d6ef6887SStanley Chang default: 255 77*d6ef6887SStanley Chang minimum: 0 78*d6ef6887SStanley Chang maximum: 255 79*d6ef6887SStanley Chang 80*d6ef6887SStanley Chang realtek,amplitude-control-fine-tuning: 81*d6ef6887SStanley Chang description: 82*d6ef6887SStanley Chang This adjusts the signal amplitude for normal operation and beacon LFPS. 83*d6ef6887SStanley Chang This value is used for fine-tuning parameters. 84*d6ef6887SStanley Chang $ref: /schemas/types.yaml#/definitions/uint32 85*d6ef6887SStanley Chang default: 65535 86*d6ef6887SStanley Chang minimum: 0 87*d6ef6887SStanley Chang maximum: 65535 88*d6ef6887SStanley Chang 89*d6ef6887SStanley Changrequired: 90*d6ef6887SStanley Chang - compatible 91*d6ef6887SStanley Chang - reg 92*d6ef6887SStanley Chang - "#phy-cells" 93*d6ef6887SStanley Chang 94*d6ef6887SStanley ChangadditionalProperties: false 95*d6ef6887SStanley Chang 96*d6ef6887SStanley Changexamples: 97*d6ef6887SStanley Chang - | 98*d6ef6887SStanley Chang usb-phy@13e10 { 99*d6ef6887SStanley Chang compatible = "realtek,rtd1319d-usb3phy"; 100*d6ef6887SStanley Chang reg = <0x13e10 0x4>; 101*d6ef6887SStanley Chang #phy-cells = <0>; 102*d6ef6887SStanley Chang 103*d6ef6887SStanley Chang nvmem-cells = <&otp_usb_u3_tx_lfps_swing_trim>; 104*d6ef6887SStanley Chang nvmem-cell-names = "usb_u3_tx_lfps_swing_trim"; 105*d6ef6887SStanley Chang 106*d6ef6887SStanley Chang realtek,amplitude-control-coarse-tuning = <0x77>; 107*d6ef6887SStanley Chang }; 108