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/linux/arch/hexagon/kernel/
H A Dvm_init_segtable.S40 #define X __HVM_PDE_S_INVALID macro
47 .word X,X,X,X
48 .word X,X,X,X
49 .word X,X,X,X
50 .word X,X,X,X
51 .word X,X,X,X,X,X,X,X,X,X,X,X,X,X,X,X
52 .word X,X,X,X,X,X,X,X,X,X,X,X,X,X,X,X,X,X,X,X,X,X,X,X,X,X,X,X,X,X,X,X
53 .word X,X,X,X,X,X,X,X,X,X,X,X,X,X,X,X,X,X,X,X,X,X,X,X,X,X,X,X,X,X,X,X
54 .word X,X,X,X,X,X,X,X,X,X,X,X,X,X,X,X,X,X,X,X,X,X,X,X,X,X,X,X,X,X,X,X
55 .word X,X,X,X,X,X,X,X,X,X,X,X,X,X,X,X,X,X,X,X,X,X,X,X,X,X,X,X,X,X,X,X
[all …]
/linux/fs/bcachefs/
H A Derrcode.h6 x(ERANGE, ERANGE_option_too_small) \
7 x(ERANGE, ERANGE_option_too_big) \
8 x(EINVAL, injected) \
9 x(BCH_ERR_injected, injected_fs_start) \
10 x(EINVAL, mount_option) \
11 x(BCH_ERR_mount_option, option_name) \
12 x(BCH_ERR_mount_option, option_value) \
13 x(BCH_ERR_mount_option, option_not_bool) \
14 x(ENOMEM, ENOMEM_stripe_buf) \
15 x(ENOMEM, ENOMEM_replicas_table) \
[all …]
H A Dsb-errors_format.h13 x(clean_but_journal_not_empty, 0, 0) \
14 x(dirty_but_no_journal_entries, 1, 0) \
15 x(dirty_but_no_journal_entries_post_drop_nonflushes, 2, 0) \
16 x(sb_clean_journal_seq_mismatch, 3, 0) \
17 x(sb_clean_btree_root_mismatch, 4, 0) \
18 x(sb_clean_missing, 5, 0) \
19 x(jset_unsupported_version, 6, 0) \
20 x(jset_unknown_csum, 7, 0) \
21 x(jset_last_seq_newer_than_seq, 8, 0) \
22 x(jset_past_bucket_end, 9, 0) \
[all …]
/linux/drivers/gpu/drm/radeon/
H A Drs600d.h33 #define S_000040_SCRATCH_INT_MASK(x) (((x) & 0x1) << 18) argument
34 #define G_000040_SCRATCH_INT_MASK(x) (((x) >> 18) & 0x1) argument
36 #define S_000040_GUI_IDLE_MASK(x) (((x) & 0x1) << 19) argument
37 #define G_000040_GUI_IDLE_MASK(x) (((x) >> 19) & 0x1) argument
39 #define S_000040_DMA_VIPH1_INT_EN(x) (((x) & 0x1) << 13) argument
40 #define G_000040_DMA_VIPH1_INT_EN(x) (((x) >> 13) & 0x1) argument
42 #define S_000040_DMA_VIPH2_INT_EN(x) (((x) & 0x1) << 14) argument
43 #define G_000040_DMA_VIPH2_INT_EN(x) (((x) >> 14) & 0x1) argument
45 #define S_000040_DMA_VIPH3_INT_EN(x) (((x) & 0x1) << 15) argument
46 #define G_000040_DMA_VIPH3_INT_EN(x) (((x) >> 15) & 0x1) argument
[all …]
H A Dr100d.h69 #define S_0000F0_SOFT_RESET_CP(x) (((x) & 0x1) << 0) argument
70 #define G_0000F0_SOFT_RESET_CP(x) (((x) >> 0) & 0x1) argument
72 #define S_0000F0_SOFT_RESET_HI(x) (((x) & 0x1) << 1) argument
73 #define G_0000F0_SOFT_RESET_HI(x) (((x) >> 1) & 0x1) argument
75 #define S_0000F0_SOFT_RESET_SE(x) (((x) & 0x1) << 2) argument
76 #define G_0000F0_SOFT_RESET_SE(x) (((x) >> 2) & 0x1) argument
78 #define S_0000F0_SOFT_RESET_RE(x) (((x) & 0x1) << 3) argument
79 #define G_0000F0_SOFT_RESET_RE(x) (((x) >> 3) & 0x1) argument
81 #define S_0000F0_SOFT_RESET_PP(x) (((x) & 0x1) << 4) argument
82 #define G_0000F0_SOFT_RESET_PP(x) (((x) >> 4) & 0x1) argument
[all …]
H A Drs690d.h34 #define G_00005F_K8_ADDR_EXT(x) (((x) >> 0) & 0xFF) argument
36 #define S_000078_MC_IND_ADDR(x) (((x) & 0x1FF) << 0) argument
37 #define G_000078_MC_IND_ADDR(x) (((x) >> 0) & 0x1FF) argument
39 #define S_000078_MC_IND_WR_EN(x) (((x) & 0x1) << 9) argument
40 #define G_000078_MC_IND_WR_EN(x) (((x) >> 9) & 0x1) argument
43 #define S_00007C_MC_DATA(x) (((x) & 0xFFFFFFFF) << 0) argument
44 #define G_00007C_MC_DATA(x) (((x) >> 0) & 0xFFFFFFFF) argument
47 #define S_0000F8_CONFIG_MEMSIZE(x) (((x) & 0xFFFFFFFF) << 0) argument
48 #define G_0000F8_CONFIG_MEMSIZE(x) (((x) >> 0) & 0xFFFFFFFF) argument
51 #define S_000134_HDP_FB_START(x) (((x) & 0xFFFF) << 0) argument
[all …]
H A Drv515d.h210 #define S_0000F0_SOFT_RESET_CP(x) (((x) & 0x1) << 0) argument
211 #define G_0000F0_SOFT_RESET_CP(x) (((x) >> 0) & 0x1) argument
213 #define S_0000F0_SOFT_RESET_HI(x) (((x) & 0x1) << 1) argument
214 #define G_0000F0_SOFT_RESET_HI(x) (((x) >> 1) & 0x1) argument
216 #define S_0000F0_SOFT_RESET_VAP(x) (((x) & 0x1) << 2) argument
217 #define G_0000F0_SOFT_RESET_VAP(x) (((x) >> 2) & 0x1) argument
219 #define S_0000F0_SOFT_RESET_RE(x) (((x) & 0x1) << 3) argument
220 #define G_0000F0_SOFT_RESET_RE(x) (((x) >> 3) & 0x1) argument
222 #define S_0000F0_SOFT_RESET_PP(x) (((x) & 0x1) << 4) argument
223 #define G_0000F0_SOFT_RESET_PP(x) (((x) >> 4) & 0x1) argument
[all …]
H A Dr300d.h70 #define S_000148_MC_FB_START(x) (((x) & 0xFFFF) << 0) argument
71 #define G_000148_MC_FB_START(x) (((x) >> 0) & 0xFFFF) argument
73 #define S_000148_MC_FB_TOP(x) (((x) & 0xFFFF) << 16) argument
74 #define G_000148_MC_FB_TOP(x) (((x) >> 16) & 0xFFFF) argument
77 #define S_00014C_MC_AGP_START(x) (((x) & 0xFFFF) << 0) argument
78 #define G_00014C_MC_AGP_START(x) (((x) >> 0) & 0xFFFF) argument
80 #define S_00014C_MC_AGP_TOP(x) (((x) & 0xFFFF) << 16) argument
81 #define G_00014C_MC_AGP_TOP(x) (((x) >> 16) & 0xFFFF) argument
84 #define S_00015C_AGP_BASE_ADDR_2(x) (((x) & 0xF) << 0) argument
85 #define G_00015C_AGP_BASE_ADDR_2(x) (((x) >> 0) & 0xF) argument
[all …]
H A Dr420d.h32 #define S_0001F8_MC_IND_ADDR(x) (((x) & 0x7F) << 0) argument
33 #define G_0001F8_MC_IND_ADDR(x) (((x) >> 0) & 0x7F) argument
35 #define S_0001F8_MC_IND_WR_EN(x) (((x) & 0x1) << 8) argument
36 #define G_0001F8_MC_IND_WR_EN(x) (((x) >> 8) & 0x1) argument
39 #define S_0001FC_MC_IND_DATA(x) (((x) & 0xFFFFFFFF) << 0) argument
40 #define G_0001FC_MC_IND_DATA(x) (((x) >> 0) & 0xFFFFFFFF) argument
43 #define S_0007C0_MRU_BUSY(x) (((x) & 0x1) << 0) argument
44 #define G_0007C0_MRU_BUSY(x) (((x) >> 0) & 0x1) argument
46 #define S_0007C0_MWU_BUSY(x) (((x) & 0x1) << 1) argument
47 #define G_0007C0_MWU_BUSY(x) (((x) >> 1) & 0x1) argument
[all …]
H A Dr600d.h60 #define BACKEND_DISABLE(x) ((x) << 16) argument
63 #define S_028808_SPECIAL_OP(x) (((x) & 0x7) << 4) argument
64 #define G_028808_SPECIAL_OP(x) (((x) >> 4) & 0x7) argument
83 #define S_028080_SLICE_START(x) (((x) & 0x7FF) << 0) argument
84 #define G_028080_SLICE_START(x) (((x) >> 0) & 0x7FF) argument
86 #define S_028080_SLICE_MAX(x) (((x) & 0x7FF) << 13) argument
87 #define G_028080_SLICE_MAX(x) (((x) >> 13) & 0x7FF) argument
97 #define S_028100_CMASK_BLOCK_MAX(x) (((x) & 0xFFF) << 0) argument
98 #define G_028100_CMASK_BLOCK_MAX(x) (((x) >> 0) & 0xFFF) argument
100 #define S_028100_FMASK_TILE_MAX(x) (((x) & 0xFFFFF) << 12) argument
[all …]
H A Dr520d.h33 #define S_0000F8_CONFIG_MEMSIZE(x) (((x) & 0xFFFFFFFF) << 0) argument
34 #define G_0000F8_CONFIG_MEMSIZE(x) (((x) >> 0) & 0xFFFFFFFF) argument
37 #define S_000134_HDP_FB_START(x) (((x) & 0xFFFF) << 0) argument
38 #define G_000134_HDP_FB_START(x) (((x) >> 0) & 0xFFFF) argument
41 #define S_0007C0_MRU_BUSY(x) (((x) & 0x1) << 0) argument
42 #define G_0007C0_MRU_BUSY(x) (((x) >> 0) & 0x1) argument
44 #define S_0007C0_MWU_BUSY(x) (((x) & 0x1) << 1) argument
45 #define G_0007C0_MWU_BUSY(x) (((x) >> 1) & 0x1) argument
47 #define S_0007C0_RSIU_BUSY(x) (((x) & 0x1) << 2) argument
48 #define G_0007C0_RSIU_BUSY(x) (((x) >> 2) & 0x1) argument
[all …]
/linux/drivers/gpu/drm/imagination/
H A Dpvr_rogue_fwif_sf.h65 #define ROGUE_FW_SF_GID(x) (((u32)(x) >> 12) & 0xfU) argument
67 #define ROGUE_FW_SF_PARAMNUM(x) (((u32)(x) >> 16) & 0xfU) argument
80 "Kick 3D: FWCtx 0x%08.8x @ %d, RTD 0x%08x. Partial render:%d, CSW resume:%d, prio:%d" },
82 "3D finished, HWRTData0State=%x, HWRTData1State=%x" },
84 "Kick 3D TQ: FWCtx 0x%08.8x @ %d, CSW resume:%d, prio: %d" },
88 "Kick Compute: FWCtx 0x%08.8x @ %d, prio: %d" },
92 … "Kick TA: FWCtx 0x%08.8x @ %d, RTD 0x%08x. First kick:%d, Last kick:%d, CSW resume:%d, prio:%d" },
100 "Out of memory! Context 0x%08x, HWRTData 0x%x" },
102 "Kick TLA: FWCtx 0x%08.8x @ %d, prio:%d" },
106 "cCCB Woff update = %d, DM = %d, FWCtx = 0x%08.8x" },
[all …]
/linux/drivers/media/platform/verisilicon/
H A Drockchip_vpu2_regs.h14 #define VEPU_REG_VP8_QUT_DC_Y2(x) (((x) & 0x3fff) << 16) argument
15 #define VEPU_REG_VP8_QUT_DC_Y1(x) (((x) & 0x3fff) << 0) argument
17 #define VEPU_REG_VP8_QUT_AC_Y1(x) (((x) & 0x3fff) << 16) argument
18 #define VEPU_REG_VP8_QUT_DC_CHR(x) (((x) & 0x3fff) << 0) argument
20 #define VEPU_REG_VP8_QUT_AC_CHR(x) (((x) & 0x3fff) << 16) argument
21 #define VEPU_REG_VP8_QUT_AC_Y2(x) (((x) & 0x3fff) << 0) argument
23 #define VEPU_REG_VP8_QUT_ZB_DC_CHR(x) (((x) & 0x1ff) << 18) argument
24 #define VEPU_REG_VP8_QUT_ZB_DC_Y2(x) (((x) & 0x1ff) << 9) argument
25 #define VEPU_REG_VP8_QUT_ZB_DC_Y1(x) (((x) & 0x1ff) << 0) argument
27 #define VEPU_REG_VP8_QUT_ZB_AC_CHR(x) (((x) & 0x1ff) << 18) argument
[all …]
H A Dhantro_g1_regs.h28 #define G1_REG_CONFIG_DEC_AXI_RD_ID(x) (((x) & 0xff) << 24) argument
37 #define G1_REG_CONFIG_DEC_LATENCY(x) (((x) & 0x3f) << 11) argument
41 #define G1_REG_CONFIG_PRIORITY_MODE(x) (((x) & 0x7) << 5) argument
45 #define G1_REG_CONFIG_DEC_MAX_BURST(x) (((x) & 0x1f) << 0) argument
47 #define G1_REG_DEC_CTRL0_DEC_MODE(x) (((x) & 0xf) << 28) argument
70 #define G1_REG_DEC_CTRL0_DEC_AXI_WR_ID(x) (((x) & 0xff) << 0) argument
74 #define G1_REG_DEC_CTRL1_PIC_MB_WIDTH(x) (((x) & 0x1ff) << 23) argument
75 #define G1_REG_DEC_CTRL1_MB_WIDTH_OFF(x) (((x) & 0xf) << 19) argument
76 #define G1_REG_DEC_CTRL1_PIC_MB_HEIGHT_P(x) (((x) & 0xff) << 11) argument
77 #define G1_REG_DEC_CTRL1_MB_HEIGHT_OFF(x) (((x) & 0xf) << 7) argument
[all …]
/linux/drivers/net/ethernet/chelsio/cxgb/
H A Dregs.h36 #define V_CMDQ0_ENABLE(x) ((x) << S_CMDQ0_ENABLE) argument
40 #define V_CMDQ1_ENABLE(x) ((x) << S_CMDQ1_ENABLE) argument
44 #define V_FL0_ENABLE(x) ((x) << S_FL0_ENABLE) argument
48 #define V_FL1_ENABLE(x) ((x) << S_FL1_ENABLE) argument
52 #define V_CPL_ENABLE(x) ((x) << S_CPL_ENABLE) argument
56 #define V_RESPONSE_QUEUE_ENABLE(x) ((x) << S_RESPONSE_QUEUE_ENABLE) argument
61 #define V_CMDQ_PRIORITY(x) ((x) << S_CMDQ_PRIORITY) argument
62 #define G_CMDQ_PRIORITY(x) (((x) >> S_CMDQ_PRIORITY) & M_CMDQ_PRIORITY) argument
65 #define V_DISABLE_CMDQ0_GTS(x) ((x) << S_DISABLE_CMDQ0_GTS) argument
69 #define V_DISABLE_CMDQ1_GTS(x) ((x) << S_DISABLE_CMDQ1_GTS) argument
[all …]
/linux/lib/crypto/
H A Dchacha.c18 u32 *x = state->x; in chacha_permute()
25 x[0] += x[4]; x[12] = rol32(x[12] ^ x[0], 16); in chacha_permute()
26 x[1] += x[5]; x[1 in chacha_permute()
16 chacha_permute(u32 * x,int nrounds) chacha_permute() argument
78 u32 x[16]; chacha_block_generic() local
105 u32 x[16]; hchacha_block_generic() local
[all...]
/linux/drivers/net/ethernet/chelsio/cxgb3/
H A Dregs.h5 #define V_CONGMODE(x) ((x) << S_CONGMODE) argument
9 #define V_TNLFLMODE(x) ((x) << S_TNLFLMODE) argument
13 #define V_FATLPERREN(x) ((x) << S_FATLPERREN) argument
17 #define V_DROPPKT(x) ((x) << S_DROPPKT) argument
21 #define V_EGRGENCTRL(x) ((x) << S_EGRGENCTRL) argument
26 #define V_USERSPACESIZE(x) ((x) << S_USERSPACESIZE) argument
30 #define V_HOSTPAGESIZE(x) ((x) << S_HOSTPAGESIZE) argument
33 #define V_FLMODE(x) ((x) << S_FLMODE) argument
38 #define V_PKTSHIFT(x) ((x) << S_PKTSHIFT) argument
41 #define V_ONEINTMULTQ(x) ((x) << S_ONEINTMULTQ) argument
[all …]
H A Dsge_defs.h11 #define V_EC_CREDITS(x) ((x) << S_EC_CREDITS) argument
12 #define G_EC_CREDITS(x) (((x) >> S_EC_CREDITS) & M_EC_CREDITS) argument
15 #define V_EC_GTS(x) ((x) << S_EC_GTS) argument
20 #define V_EC_INDEX(x) ((x) << S_EC_INDEX) argument
21 #define G_EC_INDEX(x) (((x) >> S_EC_INDEX) & M_EC_INDEX) argument
25 #define V_EC_SIZE(x) ((x) << S_EC_SIZE) argument
26 #define G_EC_SIZE(x) (((x) >> S_EC_SIZE) & M_EC_SIZE) argument
30 #define V_EC_BASE_LO(x) ((x) << S_EC_BASE_LO) argument
31 #define G_EC_BASE_LO(x) (((x) >> S_EC_BASE_LO) & M_EC_BASE_LO) argument
35 #define V_EC_BASE_HI(x) ((x) << S_EC_BASE_HI) argument
[all …]
/linux/drivers/net/ethernet/microchip/lan966x/
H A Dlan966x_regs.h38 #define AFI_PORT_FRM_OUT_FRM_OUT_CNT_SET(x)\ argument
39 FIELD_PREP(AFI_PORT_FRM_OUT_FRM_OUT_CNT, x)
40 #define AFI_PORT_FRM_OUT_FRM_OUT_CNT_GET(x)\ argument
41 FIELD_GET(AFI_PORT_FRM_OUT_FRM_OUT_CNT, x)
47 #define AFI_PORT_CFG_FC_SKIP_TTI_INJ_SET(x)\ argument
48 FIELD_PREP(AFI_PORT_CFG_FC_SKIP_TTI_INJ, x)
49 #define AFI_PORT_CFG_FC_SKIP_TTI_INJ_GET(x)\ argument
50 FIELD_GET(AFI_PORT_CFG_FC_SKIP_TTI_INJ, x)
53 #define AFI_PORT_CFG_FRM_OUT_MAX_SET(x)\ argument
54 FIELD_PREP(AFI_PORT_CFG_FRM_OUT_MAX, x)
[all …]
/linux/drivers/net/ethernet/chelsio/cxgb4/
H A Dt4_regs.h77 #define QID_V(x) ((x) << QID_S) argument
80 #define DBPRIO_V(x) ((x) << DBPRIO_S) argument
84 #define PIDX_V(x) ((x) << PIDX_S) argument
89 #define DBTYPE_V(x) ((x) << DBTYPE_S) argument
94 #define PIDX_T5_V(x) ((x) << PIDX_T5_S) argument
95 #define PIDX_T5_G(x) (((x) >> PIDX_T5_S) & PIDX_T5_M) argument
100 #define INGRESSQID_V(x) ((x) << INGRESSQID_S) argument
103 #define TIMERREG_V(x) ((x) << TIMERREG_S) argument
106 #define SEINTARM_V(x) ((x) << SEINTARM_S) argument
110 #define CIDXINC_V(x) ((x) << CIDXINC_S) argument
[all …]
H A Dt4fw_api.h123 #define FW_WR_OP_V(x) ((x) << FW_WR_OP_S) argument
124 #define FW_WR_OP_G(x) (((x) >> FW_WR_OP_S) & FW_WR_OP_M) argument
128 #define FW_WR_ATOMIC_V(x) ((x) << FW_WR_ATOMIC_S) argument
134 #define FW_WR_FLUSH_V(x) ((x) << FW_WR_FLUSH_S) argument
138 #define FW_WR_COMPL_V(x) ((x) << FW_WR_COMPL_S) argument
144 #define FW_WR_IMMDLEN_V(x) ((x) << FW_WR_IMMDLEN_S) argument
148 #define FW_WR_EQUIQ_V(x) ((x) << FW_WR_EQUIQ_S) argument
153 #define FW_WR_EQUEQ_V(x) ((x) << FW_WR_EQUEQ_S) argument
158 #define FW_WR_FLOWID_V(x) ((x) << FW_WR_FLOWID_S) argument
162 #define FW_WR_LEN16_V(x) ((x) << FW_WR_LEN16_S) argument
[all …]
H A Dt4_msg.h196 #define CPL_OPCODE_V(x) ((x) << CPL_OPCODE_S) argument
197 #define CPL_OPCODE_G(x) (((x) >> CPL_OPCODE_S) & 0xFF) argument
198 #define TID_G(x) ((x) & 0xFFFFFF) argument
211 #define TID_TID_V(x) ((x) << TID_TID_S) argument
212 #define TID_TID_G(x) (((x) >> TID_TID_S) & TID_TID_M) argument
216 #define TID_QID_V(x) ((x) << TID_QID_S) argument
217 #define TID_QID_G(x) (((x) >> TID_QID_S) & TID_QID_M) argument
248 #define WR_OP_V(x) ((__u64)(x) << WR_OP_S) argument
254 #define TX_CHAN_V(x) ((x) << TX_CHAN_S) argument
257 #define ULP_MODE_V(x) ((x) << ULP_MODE_S) argument
[all …]
/linux/tools/memory-model/
H A Dlinux-kernel.def9 READ_ONCE(X) __load{ONCE}(X)
10 WRITE_ONCE(X,V) { __store{ONCE}(X,V); }
13 smp_store_release(X,V) { __store{RELEASE}(*X,V); }
14 smp_load_acquire(X) __load{ACQUIRE}(*X)
15 rcu_assign_pointer(X,V) { __store{RELEASE}(X,
[all...]
/linux/arch/mips/include/asm/sibyte/
H A Dbcm1480_mc.h31 #define V_BCM1480_MC_INTLV0(x) _SB_MAKEVALUE(x, S_BCM1480_MC_INTLV0) argument
32 #define G_BCM1480_MC_INTLV0(x) _SB_GETVALUE(x, S_BCM1480_MC_INTLV0, M_BCM1480_MC_INTLV0) argument
37 #define V_BCM1480_MC_INTLV1(x) _SB_MAKEVALUE(x, S_BCM1480_MC_INTLV1) argument
38 #define G_BCM1480_MC_INTLV1(x) _SB_GETVALUE(x, S_BCM1480_MC_INTLV1, M_BCM1480_MC_INTLV1) argument
43 #define V_BCM1480_MC_INTLV2(x) _SB_MAKEVALUE(x, S_BCM1480_MC_INTLV2) argument
44 #define G_BCM1480_MC_INTLV2(x) _SB_GETVALUE(x, S_BCM1480_MC_INTLV2, M_BCM1480_MC_INTLV2) argument
49 #define V_BCM1480_MC_CS_MODE(x) _SB_MAKEVALUE(x, S_BCM1480_MC_CS_MODE) argument
50 #define G_BCM1480_MC_CS_MODE(x) _SB_GETVALUE(x, S_BCM1480_MC_CS_MODE, M_BCM1480_MC_CS_MODE) argument
72 #define V_BCM1480_MC_CS0_START(x) _SB_MAKEVALUE(x, S_BCM1480_MC_CS0_START) argument
73 #define G_BCM1480_MC_CS0_START(x) _SB_GETVALUE(x, S_BCM1480_MC_CS0_START, M_BCM1480_MC_CS0_STAR… argument
[all …]
/linux/drivers/phy/microchip/
H A Dlan966x_serdes_regs.h21 #define HSIO_SD_CFG_PHY_RESET_SET(x)\ argument
22 FIELD_PREP(HSIO_SD_CFG_PHY_RESET, x)
23 #define HSIO_SD_CFG_PHY_RESET_GET(x)\ argument
24 FIELD_GET(HSIO_SD_CFG_PHY_RESET, x)
27 #define HSIO_SD_CFG_TX_RESET_SET(x)\ argument
28 FIELD_PREP(HSIO_SD_CFG_TX_RESET, x)
29 #define HSIO_SD_CFG_TX_RESET_GET(x)\ argument
30 FIELD_GET(HSIO_SD_CFG_TX_RESET, x)
33 #define HSIO_SD_CFG_TX_RATE_SET(x)\ argument
34 FIELD_PREP(HSIO_SD_CFG_TX_RATE, x)
[all …]

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