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/linux/drivers/video/fbdev/
H A Dc2p_core.h2 * Fast C2P (Chunky-to-Planar) Conversion
4 * Copyright (C) 2003-2008 Geert Uytterhoeven
7 * - This code was inspired by Scout's C2P tutorial
8 * - It assumes to run on a big endian system
23 unsigned int shift, u32 mask) in _transp() argument
25 u32 t = (d[i1] ^ (d[i2] >> shift)) & mask; in _transp()
57 * Transpose operations on 8 32-bit words
62 u32 mask = get_mask(n); in transp8() local
66 /* First n x 1 block */ in transp8()
67 _transp(d, 0, 1, n, mask); in transp8()
[all …]
H A Dpxa3xx-regs.h1 /* SPDX-License-Identifier: GPL-2.0 */
36 #define LCCR3_BPP(x) ((((x) & 0x7) << 24) | (((x) & 0x8) ? (1 << 29) : 0)) argument
65 #define LCCR0_LDM (1 << 3) /* LCD Disable Done Mask */
66 #define LCCR0_SFM (1 << 4) /* Start of frame mask */
67 #define LCCR0_IUM (1 << 5) /* Input FIFO underrun mask */
68 #define LCCR0_EFM (1 << 6) /* End of Frame mask */
73 #define LCCR0_4PixMono (LCCR0_DPD*0) /* 4-Pixel/clock Monochrome display */
74 #define LCCR0_8PixMono (LCCR0_DPD*1) /* 8-Pixel/clock Monochrome display */
76 #define LCCR0_QDM (1 << 11) /* LCD Quick Disable mask */
79 #define LCCR0_BM (1 << 20) /* Branch mask */
[all …]
/linux/arch/powerpc/platforms/powermac/
H A Dpfunc_core.c1 // SPDX-License-Identifier: GPL-2.0-only
84 while(bytes--) {
85 printk("%02x ", *((u8 *)blob));
99 if ((cmd->cmdend - cmd->cmdptr) < 4) { in pmf_next32()
100 cmd->error = 1; in pmf_next32()
103 value = *((u32 *)cmd->cmdptr); in pmf_next32()
104 cmd->cmdptr += 4; in pmf_next32()
111 if ((cmd->cmdend - cmd->cmdptr) < count) { in pmf_next_blob()
112 cmd->error = 1; in pmf_next_blob()
115 value = cmd->cmdptr; in pmf_next_blob()
[all …]
/linux/include/linux/
H A Dpxa2xx_ssp.h1 /* SPDX-License-Identifier: GPL-2.0-only */
5 * This driver supports the following PXA CPU/SSP ports:-
49 #define SSCR0_DSS GENMASK(3, 0) /* Data Size Select (mask) */
50 #define SSCR0_DataSize(x) ((x) - 1) /* Data Size Select [4..16] */ argument
51 #define SSCR0_FRF GENMASK(5, 4) /* FRame Format (mask) */
57 #define SSCR0_SCR(x) ((x) << 8) /* Serial Clock Rate (mask) */ argument
62 #define SSCR0_RIM BIT(22) /* Receive FIFO overrun interrupt mask */
63 #define SSCR0_TUM BIT(23) /* Transmit FIFO underrun interrupt mask */
64 #define SSCR0_FRDC GENMASK(26, 24) /* Frame rate divider control (mask) */
65 #define SSCR0_SlotsPerFrm(x) (((x) - 1) << 24) /* Time slots per frame [1..8] */ argument
[all …]
/linux/drivers/net/mdio/
H A Dmdio-mux-mmioreg.c1 // SPDX-License-Identifier: GPL-2.0
3 * Simple memory-mapped device MDIO MUX driver
11 #include <linux/mdio-mux.h>
22 unsigned int mask; member
28 * This function is called by the mdio-mux layer when it thinks the mdio bus
32 * s->mask).
37 * The first time this function is called, current_child == -1.
48 void __iomem *p = ioremap(s->phys, s->iosize); in mdio_mux_mmioreg_switch_fn()
50 return -ENOMEM; in mdio_mux_mmioreg_switch_fn()
52 switch (s->iosize) { in mdio_mux_mmioreg_switch_fn()
[all …]
/linux/drivers/video/fbdev/core/
H A Dfb_draw.h1 /* SPDX-License-Identifier: GPL-2.0 */
11 * This is equivalent to (a & mask) | (b & ~mask)
15 comp(unsigned long a, unsigned long b, unsigned long mask) in comp() argument
17 return ((a ^ b) & mask) ^ b; in comp()
104 u32 mask; in fb_shifted_pixels_mask_u32() local
107 mask = FB_SHIFT_HIGH(p, ~(u32)0, index); in fb_shifted_pixels_mask_u32()
109 mask = 0xff << FB_LEFT_POS(p, 8); in fb_shifted_pixels_mask_u32()
110 mask = FB_SHIFT_LOW(p, mask, index & (bswapmask)) & mask; in fb_shifted_pixels_mask_u32()
111 mask = FB_SHIFT_HIGH(p, mask, index & ~(bswapmask)); in fb_shifted_pixels_mask_u32()
113 /* Shift argument is limited to 0 - 31 on x86 based CPU's */ in fb_shifted_pixels_mask_u32()
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/linux/drivers/gpu/drm/tegra/
H A Dfirewall.c1 // SPDX-License-Identifier: GPL-2.0-only
2 /* Copyright (c) 2010-2020 NVIDIA Corporation */
19 if (fw->pos == fw->end) in fw_next()
20 return -EINVAL; in fw_next()
22 *word = fw->data[fw->pos++]; in fw_next()
31 for (i = 0; i < fw->submit->num_used_mappings; i++) { in fw_check_addr_valid()
32 struct tegra_drm_mapping *m = fw->submit->used_mappings[i].mapping; in fw_check_addr_valid()
34 if (offset >= m->iova && offset <= m->iova_end) in fw_check_addr_valid()
51 if (!fw->client->ops->is_addr_reg) in fw_check_reg()
54 is_addr = fw->client->ops->is_addr_reg(fw->client->base.dev, fw->class, in fw_check_reg()
[all …]
/linux/drivers/rtc/
H A Drtc-sunxi.c1 // SPDX-License-Identifier: GPL-2.0-or-later
47 #define SUNXI_GET(x, mask, shift) (((x) & ((mask) << (shift))) \ argument
50 #define SUNXI_SET(x, mask, shift) (((x) & (mask)) << (shift)) argument
55 #define SUNXI_DATE_GET_DAY_VALUE(x) SUNXI_GET(x, SUNXI_MASK_DH, 0) argument
56 #define SUNXI_DATE_GET_MON_VALUE(x) SUNXI_GET(x, SUNXI_MASK_M, 8) argument
57 #define SUNXI_DATE_GET_YEAR_VALUE(x, mask) SUNXI_GET(x, mask, 16) argument
62 #define SUNXI_TIME_GET_SEC_VALUE(x) SUNXI_GET(x, SUNXI_MASK_SM, 0) argument
63 #define SUNXI_TIME_GET_MIN_VALUE(x) SUNXI_GET(x, SUNXI_MASK_SM, 8) argument
64 #define SUNXI_TIME_GET_HOUR_VALUE(x) SUNXI_GET(x, SUNXI_MASK_DH, 16) argument
69 #define SUNXI_ALRM_GET_SEC_VALUE(x) SUNXI_GET(x, SUNXI_MASK_SM, 0) argument
[all …]
/linux/arch/xtensa/include/asm/
H A Dbitops.h2 * include/asm-xtensa/bitops.h
10 * Copyright (C) 2001 - 2007 Tensilica Inc.
24 #include <asm-generic/bitops/non-atomic.h>
28 static inline unsigned long __cntlz (unsigned long x) in __cntlz() argument
31 asm ("nsau %0, %1" : "=r" (lz) : "r" (x)); in __cntlz()
40 static inline int ffz(unsigned long x) in ffz() argument
42 return 31 - __cntlz(~x & -~x); in ffz()
49 static inline unsigned long __ffs(unsigned long x) in __ffs() argument
51 return 31 - __cntlz(x & -x); in __ffs()
60 static inline int ffs(unsigned long x) in ffs() argument
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/linux/arch/alpha/lib/
H A Ddivide.S1 /* SPDX-License-Identifier: GPL-2.0 */
14 * __divqu: 64-bit unsigned long divide
15 * __remqu: 64-bit unsigned long remainder
16 * __divqs/__remqs: signed 64-bit
17 * __divlu/__remlu: unsigned 32-bit
18 * __divls/__remls: signed 32-bit
27 * This is a rather simple bit-at-a-time algorithm: it's very good
28 * at dividing random 64-bit numbers, but the more usual case where
37 * $0 - current bit
38 * $1 - shifted divisor
[all …]
H A Dev6-divide.S1 /* SPDX-License-Identifier: GPL-2.0 */
3 * arch/alpha/lib/ev6-divide.S
5 * 21264 version contributed by Rick Gorton <rick.gorton@alpha-processor.com>
14 * __divqu: 64-bit unsigned long divide
15 * __remqu: 64-bit unsigned long remainder
16 * __divqs/__remqs: signed 64-bit
17 * __divlu/__remlu: unsigned 32-bit
18 * __divls/__remls: signed 32-bit
27 * This is a rather simple bit-at-a-time algorithm: it's very good
28 * at dividing random 64-bit numbers, but the more usual case where
[all …]
/linux/drivers/gpu/drm/exynos/
H A Dregs-rotator.h1 /* SPDX-License-Identifier: GPL-2.0-only */
2 /* drivers/gpu/drm/exynos/regs-rotator.h
34 #define ROT_STATUS_IRQ_PENDING(x) (1 << (x)) argument
35 #define ROT_STATUS_IRQ(x) (((x) >> 8) & 0x3) argument
46 #define ROT_SET_BUF_SIZE_H(x) ((x) << 16) argument
47 #define ROT_SET_BUF_SIZE_W(x) ((x) << 0) argument
48 #define ROT_GET_BUF_SIZE_H(x) ((x) >> 16) argument
49 #define ROT_GET_BUF_SIZE_W(x) ((x) & 0xffff) argument
54 #define ROT_CROP_POS_Y(x) ((x) << 16) argument
55 #define ROT_CROP_POS_X(x) ((x) << 0) argument
[all …]
/linux/drivers/gpu/drm/nouveau/nvkm/subdev/bios/
H A Dinit.c42 nvkm_printk(init->subdev, lvl, info, "0x%08x[%c]: "fmt, \
43 init->offset, init_exec(init) ? \
44 '0' + (init->nested - 1) : ' ', ##args); \
47 if (init->subdev->debug >= NV_DBG_TRACE) \
61 return (init->execute == 1) || ((init->execute & 5) == 5); in init_exec()
67 if (exec) init->execute &= 0xfd; in init_exec_set()
68 else init->execute |= 0x02; in init_exec_set()
74 init->execute ^= 0x02; in init_exec_inv()
80 if (exec) init->execute |= 0x04; in init_exec_force()
81 else init->execute &= 0xfb; in init_exec_force()
[all …]
/linux/arch/powerpc/include/asm/
H A Dbitops.h1 /* SPDX-License-Identifier: GPL-2.0-or-later */
13 * big-endian system because, unlike little endian, the number of each
22 * There are a few little-endian macros used mostly for filesystem
24 * byte-oriented:
27 * The main difference is that bit 3-5 (64b) or 3-4 (32b) in the bit
28 * number field needs to be reversed compared to the big-endian bit
42 #include <asm/asm-compat.h>
46 #define PPC_BITLSHIFT(be) (BITS_PER_LONG - 1 - (be))
48 #define PPC_BITMASK(bs, be) ((PPC_BIT(bs) - PPC_BIT(be)) | PPC_BIT(bs))
54 #define PPC_BITLSHIFT32(be) (32 - 1 - (be))
[all …]
/linux/drivers/iommu/
H A Domap-iopgtable.h1 /* SPDX-License-Identifier: GPL-2.0-only */
5 * Copyright (C) 2008-2010 Nokia Corporation
16 * "L2 table" address mask and size definitions.
20 #define IOPGD_MASK (~(IOPGD_SIZE - 1))
23 * "section" address mask and size definitions.
27 #define IOSECTION_MASK (~(IOSECTION_SIZE - 1))
30 * "supersection" address mask and size definitions.
34 #define IOSUPER_MASK (~(IOSUPER_SIZE - 1))
36 #define PTRS_PER_IOPGD (1UL << (32 - IOPGD_SHIFT))
40 * "small page" address mask and size definitions.
[all …]
/linux/arch/arm/mach-pxa/
H A Dmfp-pxa2xx.c1 // SPDX-License-Identifier: GPL-2.0-only
3 * linux/arch/arm/mach-pxa/mfp-pxa2xx.c
13 #include <linux/gpio-pxa.h>
21 #include "pxa2xx-regs.h"
22 #include "mfp-pxa2xx.h"
23 #include "mfp-pxa27x.h"
27 #define PGSR(x) __REG2(0x40F00020, (x) << 2) argument
28 #define __GAFR(u, x) __REG2((u) ? 0x40E00058 : 0x40E00054, (x) << 3) argument
29 #define GAFR_L(x) __GAFR(0, x) argument
30 #define GAFR_U(x) __GAFR(1, x) argument
[all …]
/linux/drivers/net/wireless/broadcom/b43/
H A Ddebugfs.c1 // SPDX-License-Identifier: GPL-2.0-or-later
8 Copyright (c) 2005-2007 Michael Buesch <m@bues.ch>
43 p = dev->dfsentry; in fops_to_dfs_file()
44 p += dfops->file_struct_offset; in fops_to_dfs_file()
50 #define fappend(fmt, x...) \
52 if (bufsize - coun
51 fappend(fmt,x...) global() argument
112 unsigned int routing, addr, mask, set; shm16write__write_file() local
188 unsigned int routing, addr, mask, set; shm32write__write_file() local
260 unsigned int addr, mask, set; mmio16write__write_file() local
324 unsigned int addr, mask, set; mmio32write__write_file() local
[all...]
/linux/drivers/hwmon/
H A Dltc2992.c1 // SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 * LTC2992 - Dual Wide Range Power Monitor
62 #define LTC2992_POWER(x) (LTC2992_POWER1 + ((x) * 0x32)) argument
63 #define LTC2992_POWER_MAX(x) (LTC2992_POWER1_MAX + ((x) * 0x32)) argument
64 #define LTC2992_POWER_MIN(x) (LTC2992_POWER1_MIN + ((x) * 0x32)) argument
65 #define LTC2992_POWER_MAX_THRESH(x) (LTC2992_POWER1_MAX_THRESH + ((x) * 0x32)) argument
66 #define LTC2992_POWER_MIN_THRESH(x) (LTC2992_POWER1_MIN_THRESH + ((x) * 0x32)) argument
67 #define LTC2992_DSENSE(x) (LTC2992_DSENSE1 + ((x) * 0x32)) argument
68 #define LTC2992_DSENSE_MAX(x) (LTC2992_DSENSE1_MAX + ((x) * 0x32)) argument
69 #define LTC2992_DSENSE_MIN(x) (LTC2992_DSENSE1_MIN + ((x) * 0x32)) argument
[all …]
/linux/drivers/gpu/drm/i915/
H A Di915_cmd_parser.c86 * implemented via a per-engine length decoding vfunc.
91 * in the per-engine command tables.
107 * a length mask if not set
129 u32 mask; member
134 * not include a length field) or has a length field mask. The flag
136 * a length mask. All command entries in a command table must include
141 u32 mask; member
149 * A non-zero step value implies that the command may access multiple
155 u32 mask; member
164 * the CMD_DESC_BITMASK bit set. Only entries where mask is non-zero
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/linux/drivers/regulator/
H A Dlp3972.c1 // SPDX-License-Identifier: GPL-2.0-only
64 /* LDO output enable mask */
143 #define LP3972_LDO_OUTPUT_ENABLE_MASK(x) (ldo_output_enable_mask[x]) argument
144 #define LP3972_LDO_OUTPUT_ENABLE_REG(x) (ldo_output_enable_addr[x]) argument
147 LP3972_LDO1 -> 0, LP3972_LDO2 -> 4
148 LP3972_LDO3 -> 0, LP3972_LDO4 -> 4
149 LP3972_LDO5 -> 0
151 #define LP3972_LDO_VOL_CONTR_SHIFT(x) (((x) & 1) << 2) argument
152 #define LP3972_LDO_VOL_CONTR_REG(x) (ldo_vol_ctl_addr[x]) argument
153 #define LP3972_LDO_VOL_CHANGE_SHIFT(x) ((x) ? 4 : 6) argument
[all …]
H A Dlp3971.c1 // SPDX-License-Identifier: GPL-2.0-only
27 static int lp3971_set_bits(struct lp3971 *lp3971, u8 reg, u16 mask, u16 val);
40 LP3971_BUCK1 -> 0
41 LP3971_BUCK2 -> 4
42 LP3971_BUCK3 -> 6
44 #define BUCK_VOL_CHANGE_SHIFT(x) (((!!x) << 2) | (x & ~0x01)) argument
59 #define LP3971_BUCK_TARGET_VOL1_REG(x) (buck_base_addr[x]) argument
60 #define LP3971_BUCK_TARGET_VOL2_REG(x) (buck_base_addr[x]+1) argument
71 #define LP3971_BUCK_RAMP_REG(x) (buck_base_addr[x]+2) argument
77 LP3971_LDO1 -> LP3971_LDO_VOL_CONTR_BASE + 0
[all …]
/linux/arch/arm/mach-s3c/
H A Dpm-gpio.c1 // SPDX-License-Identifier: GPL-2.0+
16 #include "gpio-samsung.h"
18 #include "gpio-core.h"
29 chip->pm_save[0] = __raw_readl(chip->base + OFFS_CON); in samsung_gpio_pm_1bit_save()
30 chip->pm_save[1] = __raw_readl(chip->base + OFFS_DAT); in samsung_gpio_pm_1bit_save()
35 void __iomem *base = chip->base; in samsung_gpio_pm_1bit_resume()
38 u32 gps_gpcon = chip->pm_save[0]; in samsung_gpio_pm_1bit_resume()
39 u32 gps_gpdat = chip->pm_save[1]; in samsung_gpio_pm_1bit_resume()
43 * GPACON[x] = 0 => Output, 1 => SFN */ in samsung_gpio_pm_1bit_resume()
55 S3C_PMDBG("%s: CON %08x => %08x, DAT %08x => %08x\n", in samsung_gpio_pm_1bit_resume()
[all …]
/linux/drivers/net/ethernet/intel/i40e/
H A Di40e_diag.c1 // SPDX-License-Identifier: GPL-2.0
2 /* Copyright(c) 2013 - 2018 Intel Corporation. */
11 * @mask: bits to be touched
14 u32 reg, u32 mask) in i40e_diag_reg_pattern_test() argument
25 wr32(hw, reg, (pat & mask)); in i40e_diag_reg_pattern_test()
27 if ((val & mask) != (pat & mask)) { in i40e_diag_reg_pattern_test()
29 "%s: reg pattern test failed - reg 0x%08x pat 0x%08x val 0x%08x\n", in i40e_diag_reg_pattern_test()
31 return -EIO; in i40e_diag_reg_pattern_test()
39 "%s: reg restore test failed - reg 0x%08x orig_val 0x%08x val 0x%08x\n", in i40e_diag_reg_pattern_test()
41 return -EIO; in i40e_diag_reg_pattern_test()
[all …]
/linux/drivers/s390/cio/
H A Dvfio_ccw_trace.h1 /* SPDX-License-Identifier: GPL-2.0 */
22 int mask,
24 TP_ARGS(schid, mask, event),
30 __field(int, mask)
35 __entry->cssid = schid.cssid;
36 __entry->ssid = schid.ssid;
37 __entry->sch_no = schid.sch_no;
38 __entry->mask = mask;
39 __entry->event = event;
42 TP_printk("schid=%x.%x.%04x mask=0x%x event=%d",
[all …]
/linux/drivers/gpu/drm/hisilicon/kirin/
H A Dkirin_ade_reg.h1 /* SPDX-License-Identifier: GPL-2.0-only */
4 * Copyright (c) 2014-2016 HiSilicon Limited.
13 #define MASK(x) (BIT_ULL(x) - 1) argument
17 #define FRM_END_START_MASK MASK(2)
26 #define ADE_SOFT_RST_SEL(x) (0x0078 + (x) * 0x4) argument
27 #define ADE_RELOAD_DIS(x) (0x00AC + (x) * 0x4) argument
34 #define RD_CH_CTRL(x) (0x1004 + (x) * 0x80) argument
35 #define RD_CH_ADDR(x) (0x1008 + (x) * 0x80) argument
36 #define RD_CH_SIZE(x) (0x100C + (x) * 0x80) argument
37 #define RD_CH_STRIDE(x) (0x1010 + (x) * 0x80) argument
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