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/linux/drivers/dma/ti/
H A Dedma.c1 // SPDX-License-Identifier: GPL-2.0-only
9 #include <linux/dma-mapping.h>
29 #include "../virt-dma.h"
71 #define EDMA_DMAQNUM 0x0240 /* 8 registers (4 on OMAP-L1xx) */
82 #define EDMA_DRAE 0x0340 /* 4 x 64 bits*/
84 #define EDMA_QUEEVTENTRY 0x0400 /* 2 x 16 registers */
101 #define GET_NUM_DMACH(x) (x & 0x7) /* bits 0-2 */ argument
102 #define GET_NUM_QDMACH(x) ((x & 0x70) >> 4) /* bits 4-6 */ argument
103 #define GET_NUM_PAENTRY(x) ((x & 0x7000) >> 12) /* bits 12-14 */ argument
104 #define GET_NUM_EVQUE(x) ((x & 0x70000) >> 16) /* bits 16-18 */ argument
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/linux/drivers/mtd/nand/raw/
H A Dlpc32xx_slc.c1 // SPDX-License-Identifier: GPL-2.0-or-later
24 #include <linux/dma-mapping.h>
30 #define LPC32XX_MODNAME "lpc32xx-nand"
36 #define SLC_DATA(x) (x + 0x000) argument
37 #define SLC_ADDR(x) (x + 0x004) argument
38 #define SLC_CMD(x) (x + 0x008) argument
39 #define SLC_STOP(x) (x + 0x00C) argument
40 #define SLC_CTRL(x) (x + 0x010) argument
41 #define SLC_CFG(x) (x + 0x014) argument
42 #define SLC_STAT(x) (x + 0x018) argument
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H A Dtegra_nand.c1 // SPDX-License-Identifier: GPL-2.0
4 * Copyright (C) 2014-2015 Lucas Stach <dev@lynxeye.de>
10 #include <linux/dma-mapping.h>
34 #define COMMAND_TRANS_SIZE(size) ((((size) - 1) & 0xf) << 20)
39 #define COMMAND_CE(x) BIT(8 + ((x) & 0x7)) argument
40 #define COMMAND_CLE_SIZE(size) ((((size) - 1) & 0x3) << 4)
41 #define COMMAND_ALE_SIZE(size) ((((size) - 1) & 0xf) << 0)
53 #define IER_ERR_TRIG_VAL(x) (((x) & 0xf) << 16) argument
80 #define CONFIG_TAG_BYTE_SIZE(x) ((x) & 0xff) argument
83 #define TIMING_TRP_RESP(x) (((x) & 0xf) << 28) argument
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H A Dfsl_elbc_nand.c1 // SPDX-License-Identifier: GPL-2.0-or-later
4 * Copyright © 2006-2007, 2010 Freescale Semiconductor
9 * Roy Zang <tie-fei.zang@freescale.com>
66 /* These map to the positions used by the FCM hardware ECC generator */
74 if (section >= chip->ecc.steps) in fsl_elbc_ooblayout_ecc()
75 return -ERANGE; in fsl_elbc_ooblayout_ecc()
77 oobregion->offset = (16 * section) + 6; in fsl_elbc_ooblayout_ecc()
78 if (priv->fmr & FMR_ECCM) in fsl_elbc_ooblayout_ecc()
79 oobregion->offset += 2; in fsl_elbc_ooblayout_ecc()
81 oobregion->length = chip->ecc.bytes; in fsl_elbc_ooblayout_ecc()
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H A Darasan-nand-controller.c1 // SPDX-License-Identifier: GPL-2.0
5 * Copyright (C) 2014 - 2020 Xilinx, Inc.
17 #include <linux/dma-mapping.h>
30 #define PKT_SIZE(x) FIELD_PREP(GENMASK(10, 0), (x)) argument
31 #define PKT_STEPS(x) FIELD_PREP(GENMASK(23, 12), (x)) argument
36 #define ADDR2_STRENGTH(x) FIELD_PREP(GENMASK(27, 25), (x)) argument
37 #define ADDR2_CS(x) FIELD_PREP(GENMASK(31, 30), (x)) argument
40 #define CMD_1(x) FIELD_PREP(GENMASK(7, 0), (x)) argument
41 #define CMD_2(x) FIELD_PREP(GENMASK(15, 8), (x)) argument
42 #define CMD_PAGE_SIZE(x) FIELD_PREP(GENMASK(25, 23), (x)) argument
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H A Dmarvell_nand.c1 // SPDX-License-Identifier: GPL-2.0
6 * Author: Miquel RAYNAL <miquel.raynal@free-electrons.com>
13 * The main visible difference is that NFCv1 only has Hamming ECC
14 * capabilities, while NFCv2 also embeds a BCH ECC engine. Also, DMA
17 * The ECC layouts are depicted in details in Marvell AN-379, but here
21 * or 4) and each chunk will have its own ECC "digest" of 6B at the
28 * +-------------------------------------------------------------+
29 * | Data 1 | ... | Data N | ECC 1 | ... | ECCN | Free OOB bytes |
30 * +-------------------------------------------------------------+
33 * ECC) sections and potentially an extra one to deal with
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H A Dmtk_nand.c1 // SPDX-License-Identifier: GPL-2.0 OR MIT
6 * Jorge Ramirez-Ortiz <jorge.ramirez-ortiz@linaro.org>
10 #include <linux/dma-mapping.h>
19 #include <linux/mtd/nand-ecc-mtk.h>
77 #define NFI_FDML(x) (0xA0 + (x) * sizeof(u32) * 2) argument
78 #define NFI_FDMM(x) (0xA4 + (x) * sizeof(u32) * 2) argument
89 #define MTK_NAME "mtk-nand"
90 #define KB(x) ((x) * 1024UL) argument
91 #define MB(x) (KB(x) * 1024UL) argument
146 struct mtk_ecc *ecc; member
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H A Dcafe_nand.c1 // SPDX-License-Identifier: GPL-2.0-only
23 #include <linux/dma-mapping.h>
101 #define cafe_readl(cafe, addr) readl((cafe)->mmio + CAFE_##addr)
102 #define cafe_writel(cafe, datum, addr) writel(datum, (cafe)->mmio + CAFE_##addr)
112 cafe_dev_dbg(&cafe->pdev->dev, "NAND device is%s ready, IRQ %x (%x) (%x,%x)\n", in cafe_device_ready()
124 if (cafe->usedma) in cafe_write_buf()
125 memcpy(cafe->dmabuf + cafe->datalen, buf, len); in cafe_write_buf()
127 memcpy_toio(cafe->mmio + CAFE_NAND_WRITE_DATA + cafe->datalen, buf, len); in cafe_write_buf()
129 cafe->datalen += len; in cafe_write_buf()
131 cafe_dev_dbg(&cafe->pdev->dev, "Copy 0x%x bytes to write buffer. datalen 0x%x\n", in cafe_write_buf()
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H A Dlpc32xx_mlc.c1 // SPDX-License-Identifier: GPL-2.0-or-later
11 * - Read: Auto Decode
12 * - Write: Auto Encode
13 * - Tested Page Sizes: 2048, 4096
32 #include <linux/dma-mapping.h>
41 #define MLC_BUFF(x) (x + 0x00000) argument
42 #define MLC_DATA(x) (x + 0x08000) argument
43 #define MLC_CMD(x) (x + 0x10000) argument
44 #define MLC_ADDR(x) (x + 0x10004) argument
45 #define MLC_ECC_ENC_REG(x) (x + 0x10008) argument
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H A Dvf610_nfc.c1 // SPDX-License-Identifier: GPL-2.0+
3 * Copyright 2009-2015 Freescale Semiconductor, Inc. and others
15 * - Untested on MPC5125 and M54418.
16 * - DMA and pipelining not used.
17 * - 2K pages or less.
18 * - HW ECC: Only 2K page with 64+ OOB.
19 * - HW ECC: Only 24 and 32-bit error correction implemented.
67 #define COMMAND_NADDR_BYTES(x) GENMASK(13, 13 - (x) + 1) argument
76 /* NFC ECC mode define */
136 * ECC status - seems to consume 8 bytes (double word). The documented
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H A Dmxc_nand.c1 // SPDX-License-Identifier: GPL-2.0+
3 * Copyright 2004-2007 Freescale Semiconductor, Inc. All Rights Reserved.
28 #define NFC_V1_V2_BUF_SIZE (host->regs + 0x00)
29 #define NFC_V1_V2_BUF_ADDR (host->regs + 0x04)
30 #define NFC_V1_V2_FLASH_ADDR (host->regs + 0x06)
31 #define NFC_V1_V2_FLASH_CMD (host->regs + 0x08)
32 #define NFC_V1_V2_CONFIG (host->regs + 0x0a)
33 #define NFC_V1_V2_ECC_STATUS_RESULT (host->regs + 0x0c)
34 #define NFC_V1_V2_RSLTMAIN_AREA (host->regs + 0x0e)
35 #define NFC_V21_RSLTSPARE_AREA (host->regs + 0x10)
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H A Ddiskonchip.c1 // SPDX-License-Identifier: GPL-2.0-only
14 * converted to the generic Reed-Solomon library by Thomas Gleixner <tglx@linutronix.de>
16 * Interface to generic NAND code for M-Systems DiskOnChip devices
79 /* This is the ecc value computed by the HW ecc generator upon writing an empty
85 #define DoC_is_MillenniumPlus(doc) ((doc)->ChipID == DOC_ChipID_DocMilPlus16 || (doc)->ChipID == DO…
86 #define DoC_is_Millennium(doc) ((doc)->ChipID == DOC_ChipID_DocMil)
87 #define DoC_is_2000(doc) ((doc)->ChipID == DOC_ChipID_Doc2k)
115 /* Sector size for HW ECC */
129 * Reed-Solomon library code.
133 * of the generic Reed-Solomon library. tglx
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H A Dfsl_ifc_nand.c1 // SPDX-License-Identifier: GPL-2.0-or-later
5 * Copyright 2011-2012 Freescale Semiconductor, Inc
51 unsigned int eccread; /* Non zero for a full-page ECC read */
67 .offs = 2, /* 0 on 8-bit small page */
77 .offs = 2, /* 0 on 8-bit small page */
90 return -ERANGE; in fsl_ifc_ooblayout_ecc()
92 oobregion->offset = 8; in fsl_ifc_ooblayout_ecc()
93 oobregion->length = chip->ecc.total; in fsl_ifc_ooblayout_ecc()
104 return -ERANGE; in fsl_ifc_ooblayout_free()
106 if (mtd->writesize == 512 && in fsl_ifc_ooblayout_free()
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/linux/drivers/mtd/nand/raw/gpmi-nand/
H A Dgpmi-nand.h1 /* SPDX-License-Identifier: GPL-2.0+ */
5 * Copyright (C) 2010-2011 Freescale Semiconductor, Inc.
13 #include <linux/dma-mapping.h>
26 * struct bch_geometry - BCH geometry description.
28 * @ecc_strength: A number that describes the strength of the ECC
33 * @ecc0_chunk_size: The size, in bytes, of a first ECC chunk.
34 * @eccn_chunk_size: The size, in bytes, of a single ECC chunk after
36 * @ecc_chunk_count: The number of ECC chunks in the page,
40 * the ECC status appears.
41 * @block_mark_byte_offset: The byte offset in the ECC-based page view at
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/linux/drivers/edac/
H A Dzynqmp_edac.c1 // SPDX-License-Identifier: GPL-2.0
3 * Xilinx ZynqMP OCM ECC Driver
28 /* ECC control register */
47 /* ECC control register bit field definitions */
70 #define EDAC_DEVICE "ZynqMP-OCM"
73 * struct ecc_error_info - ECC error log information
75 * @fault_lo: Generated fault data (lower 32-bit)
76 * @fault_hi: Generated fault data (upper 32-bit)
85 * struct ecc_status - ECC status information to report
99 * struct edac_priv - OCM private instance data
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H A Di82975x_edac.c2 * Intel 82975X Memory Controller kernel module
34 /* Intel 82975X register addresses - device 0 function 0 - DRAM Controller */
37 * 31:7 128 byte cache-line address
44 * 7:0 DRAM ECC Syndrome
50 * More - See Page 65 of Intel DocSheet.
58 * 9 non-DRAM lock error (ndlock)
61 * 1 ECC UE (multibit DRAM error)
62 * 0 ECC CE (singlebit DRAM error)
76 * 9 non-DRAM lock error (ndlock)
79 * 1 ECC UE (multibit DRAM error)
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H A DKconfig16 EDAC is a subsystem along with hardware-specific drivers designed to
17 report hardware errors. These are low-level errors that are reported
22 The mailing list for the EDAC project is linux-edac@vger.kernel.org.
39 You do so by inserting edac_module with "edac_debug_level=x." Valid
40 levels are 0-4 (from low to high) and by default it is set to 2.
44 tristate "Decode MCEs in human-readable form (only on AMD for now)"
49 occurring on your machine in human-readable form.
60 Not all machines support hardware-driven error report. Some of those
61 provide a BIOS-driven error report mechanism via ACPI, using the
65 When this option is enabled, it will disable the hardware-driven
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H A Dsynopsys_edac.c1 // SPDX-License-Identifier: GPL-2.0-only
3 * Synopsys DDR ECC Driver
6 * Copyright (C) 2012 - 2014 Xilinx, Inc.
33 /* Synopsys DDR memory controller registers that are relevant to ECC */
37 /* ECC control register */
39 /* ECC log register */
41 /* ECC address register */
43 /* ECC data[31:0] register */
64 /* ECC control register bit field definitions */
68 /* ECC correctable/uncorrectable error log register definitions */
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H A Daltera_edac.c1 // SPDX-License-Identifier: GPL-2.0
3 * Copyright (C) 2017-2018, Intel Corporation. All rights reserved
4 * Copyright Altera Corporation (C) 2014-2016. All rights reserved.
5 * Copyright 2011-2012 Calxeda, Inc.
12 #include <linux/firmware/intel/stratix10-smc.h>
17 #include <linux/mfd/altera-sysmgr.h>
84 struct altr_sdram_mc_data *drvdata = mci->pvt_info; in altr_sdram_mc_err_handler()
85 const struct altr_sdram_prv_data *priv = drvdata->data; in altr_sdram_mc_err_handler()
88 regmap_read(drvdata->mc_vbase, priv->ecc_stat_offset, &status); in altr_sdram_mc_err_handler()
90 if (status & priv->ecc_stat_ue_mask) { in altr_sdram_mc_err_handler()
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/linux/fs/ocfs2/
H A Dblockcheck.c1 // SPDX-License-Identifier: GPL-2.0-only
5 * Checksum and ECC codes for the OCFS2 userspace library.
39 * power-of-two bits for parity, the data bit number and the code bit
42 * Recall that bit numbers in hamming code are 1-based. This function
43 * takes the 0-based data bit from the caller.
59 * Data bits are 0-based, but we're talking code bits, which in calc_code_bit()
60 * are 1-based. in calc_code_bit()
105 * 1-based array, but C uses 0-based. So 'i' is for C, and 'b' is in ocfs2_hamming_encode()
235 debugfs_remove_recursive(stats->b_debug_dir); in ocfs2_blockcheck_debug_remove()
236 stats->b_debug_dir = NULL; in ocfs2_blockcheck_debug_remove()
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/linux/drivers/scsi/csiostor/
H A Dcsio_hw_t5.c4 * Copyright (c) 2008-2013 Chelsio Communications, Inc. All rights reserved.
15 * - Redistributions of source code must retain the above
19 * - Redistributions in binary form must reproduce the above
42 * Truncation intentional: we only read the bottom 32-bits of the in csio_t5_set_mem_win()
43 * 64-bit BAR0/BAR1 ... We use the hardware backdoor mechanism to in csio_t5_set_mem_win()
46 * accesses to our Configuration Space and we need to set up the PCI-E in csio_t5_set_mem_win()
48 * coming across the PCI-E link. in csio_t5_set_mem_win()
60 WINDOW_V(ilog2(MEMWIN_APERTURE) - 10), in csio_t5_set_mem_win()
76 -1, 1 }, in csio_t5_pcie_intr_handler()
77 { MSTTIMEOUTPERR_F, "Master Timeout FIFO parity error", -1, 1 }, in csio_t5_pcie_intr_handler()
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/linux/lib/
H A Dbch.c15 * Franklin St, Fifth Floor, Boston, MA 02110-1301 USA.
24 * Bose-Chaudhuri-Hocquenghem (BCH) codes.
30 * Call bch_encode to compute and store ecc parity bytes to a given buffer.
39 * better (up to 2x) encoding performance. Using this option makes sense when
50 * b. Error locator polynomial computation using Berlekamp-Massey algorithm
56 * (BTA) down to a certain degree (4), after which ad hoc low-degree polynomial
63 * - WEWoRC 2009, Graz, Austria, LNCS, Springer, July 2009, to appear.
81 #define GF_N(_p) ((1 << (CONFIG_BCH_CONST_M))-1)
85 #define GF_M(_p) ((_p)->m)
86 #define GF_T(_p) ((_p)->t)
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/linux/drivers/mtd/nand/raw/ingenic/
H A Djz4740_ecc.c1 // SPDX-License-Identifier: GPL-2.0
3 * JZ4740 ECC controller driver
7 * based on jz4740-nand.c
26 #define JZ_REG_NAND_ERR(x) (0x1C + ((x) << 2)) argument
45 static void jz4740_ecc_reset(struct ingenic_ecc *ecc, bool calc_ecc) in jz4740_ecc_reset() argument
50 writel(0, ecc->base + JZ_REG_NAND_IRQ_STAT); in jz4740_ecc_reset()
52 /* Initialize and enable ECC hardware */ in jz4740_ecc_reset()
53 reg = readl(ecc->base + JZ_REG_NAND_ECC_CTRL); in jz4740_ecc_reset()
57 if (calc_ecc) /* calculate ECC from data */ in jz4740_ecc_reset()
59 else /* correct data from ECC */ in jz4740_ecc_reset()
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/linux/arch/mips/dec/
H A Decc-berr.c1 // SPDX-License-Identifier: GPL-2.0-or-later
3 * Bus error event handling code for systems equipped with ECC
20 #include <asm/cpu-type.h>
26 #include <asm/dec/ecc.h>
52 static const char eccstr[] = "ECC error"; in dec_ecc_be_backend()
65 /* For non-ECC ack ASAP, so that any subsequent errors get caught. */ in dec_ecc_be_backend()
80 /* An ECC error on a CPU or DMA transaction. */ in dec_ecc_be_backend()
90 /* For ECC errors on reads adjust for MT pipelining. */ in dec_ecc_be_backend()
92 address = (address & ~0xfffLL) | ((address - 5) & 0xfffLL); in dec_ecc_be_backend()
156 if (syn && syn == (syn & -syn)) { in dec_ecc_be_backend()
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/linux/drivers/net/can/spi/mcp251xfd/
H A Dmcp251xfd-core.c1 // SPDX-License-Identifier: GPL-2.0
3 // mcp251xfd - Microchip MCP251xFD Family CAN controller driver
6 // Marc Kleine-Budde <kernel@pengutronix.de>
79 * [-64,63] for TDCO, indicating a relative TDCO.
115 return __mcp251xfd_get_model_str(priv->devtype_data.model); in mcp251xfd_get_model_str()
160 if (!priv->reg_vdd) in mcp251xfd_vdd_enable()
163 return regulator_enable(priv->reg_vdd); in mcp251xfd_vdd_enable()
168 if (!priv->reg_vdd) in mcp251xfd_vdd_disable()
171 return regulator_disable(priv->reg_vdd); in mcp251xfd_vdd_disable()
177 if (!priv->reg_xceiver) in mcp251xfd_transceiver_enable()
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