| /freebsd/sys/contrib/device-tree/Bindings/memory-controllers/ |
| H A D | arm,pl172.txt | 5 - compatible: Must be "arm,primecell" and exactly one from
8 - reg: Must contains offset/length value for controller.
10 - #address-cells: Must be 2. The partition number has to be encoded in the
11 first address cell and it may accept values 0..N-1
12 (N - total number of partitions). The second cell is the
15 - #size-cells: Must be set to 1.
17 - ranges: Must contain one or more chip select memory regions.
19 - clocks: Must contain references to controller clocks.
21 - clock-names: Must contain "mpmcclk" and "apb_pclk".
23 - clock-ranges: Empty property indicating that child nodes can inherit
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| H A D | ti,gpmc-child.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/memory-controllers/ti,gpmc-child.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Tony Lindgren <tony@atomide.com>
11 - Roger Quadros <rogerq@kernel.org>
24 gpmc,sync-clk-ps:
28 # Chip-select signal timings corresponding to GPMC_CONFIG2:
29 gpmc,cs-on-ns:
33 gpmc,cs-rd-off-ns:
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| H A D | omap-gpmc.txt | 7 - compatible: Should be set to one of the following:
9 ti,omap2420-gpmc (omap2420)
10 ti,omap2430-gpmc (omap2430)
11 ti,omap3430-gpmc (omap3430 & omap3630)
12 ti,omap4430-gpmc (omap4430 & omap4460 & omap543x)
13 ti,am3352-gpmc (am335x devices)
15 - reg: A resource specifier for the register space
17 - ti,hwmods: Should be set to "ti,gpmc" until the DT transition is
19 - #address-cells: Must be set to 2 to allow memory address translation
20 - #size-cells: Must be set to 1 to allow CS address passing
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| H A D | st,stm32-fmc2-ebi-props.yaml | 1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/memory-controllers/st,stm32-fmc2-ebi-props.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Christophe Kerello <christophe.kerello@foss.st.com>
11 - Marek Vasut <marex@denx.de>
14 st,fmc2-ebi-cs-transaction-type:
25 8: Synchronous read synchronous write PSRAM.
26 9: Synchronous read asynchronous write PSRAM.
27 10: Synchronous read synchronous write NOR.
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| H A D | ti-aemif.txt | 4 provide a glue-less interface to a variety of asynchronous memory devices like
6 can be accessed at any given time via four chip selects with 64M byte access
11 Davinci DM646x - http://www.ti.com/lit/ug/sprueq7c/sprueq7c.pdf
12 OMAP-L138 (DA850) - http://www.ti.com/lit/ug/spruh77a/spruh77a.pdf
13 Kestone - http://www.ti.com/lit/ug/sprugz3a/sprugz3a.pdf
17 - compatible: "ti,davinci-aemif"
18 "ti,keystone-aemif"
19 "ti,da850-aemif"
21 - reg: contains offset/length value for AEMIF control registers
24 - #address-cells: Must be 2. The partition number has to be encoded in the
[all …]
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| /freebsd/sys/dev/bhnd/cores/pci/ |
| H A D | bhnd_pci.c | 1 /*-
2 * SPDX-License-Identifier: BSD-2-Clause
79 BHND_PCI_DEV(PCI, "Host-PCI bridge", BHND_DF_HOSTB),
80 BHND_PCI_DEV(PCI, "PCI-BHND bridge", BHND_DF_SOC),
81 BHND_PCI_DEV(PCIE, "PCIe-G1 Host-PCI bridge", BHND_DF_HOSTB),
82 BHND_PCI_DEV(PCIE, "PCIe-G1 PCI-BHND bridge", BHND_DF_SOC),
94 #define BHND_PCIE_MDIO_CTL_DELAY 10 /**< usec delay required between
96 #define BHND_PCIE_MDIO_RETRY_DELAY 2000 /**< usec delay before retrying
102 bhnd_bus_read_4((_sc)->mem_res, (_reg))
104 bhnd_bus_write_4((_sc)->mem_res, (_reg), (_val))
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| /freebsd/sys/contrib/alpine-hal/ |
| H A D | al_hal_plat_services.h | 1 /*-
10 found at http://www.gnu.org/licenses/gpl-2.0.html
42 * - Registers read/write
43 * - Assertions
44 * - Memory barriers
45 * - Endianness conversions
95 /* *INDENT-OFF* */
99 /* *INDENT-ON* */
135 * Make sure write data will be visible in order by other cpus masters.
190 * Relaxed register read/write functions don't involve cpu instructions that
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| /freebsd/share/misc/ |
| H A D | scsi_modes | 35 # 'i' is a byte-sized integral types, followed by a field width of
38 # 'b' is a bit-sized integral type
39 # 't' is a bitfield type- followed by a bit field width
42 # 'z' values are null-padded strings
81 {Extended Self-Test Completion Time} i2
95 0x02 "Disconnect-Reconnect" {
111 0x16 "Extended Device-Type Specific";
154 0x18 "Protocol-Specific Logical Unit";
156 0x19 "Protocol-Specific Port";
158 # DIRECT ACCESS DEVICES
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| /freebsd/sys/contrib/device-tree/src/arm/nxp/lpc/ |
| H A D | lpc4350-hitex-eval.dts | 9 * Released under the terms of 3-clause BSD License
13 /dts-v1/;
18 #include "dt-bindings/input/input.h"
19 #include "dt-bindings/gpio/gpio.h"
23 compatible = "hitex,lpc4350-eval-board", "nxp,lpc4350";
33 stdout-path = &uart0;
42 compatible = "gpio-keys-polled";
43 poll-interval = <100>;
97 compatible = "gpio-leds";
102 linux,default-trigger = "heartbeat";
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| /freebsd/sys/contrib/device-tree/Bindings/memory-controllers/ddr/ |
| H A D | jedec,lpddr2-timings.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/memory-controllers/ddr/jedec,lpddr2-timings.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: LPDDR2 SDRAM AC timing parameters for a given speed-bin
10 - Krzysztof Kozlowski <krzk@kernel.org>
14 const: jedec,lpddr2-timings
16 max-freq:
19 Maximum DDR clock frequency for the speed-bin, in Hz.
21 min-freq:
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| H A D | jedec,lpddr3.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/memory-controllers/ddr/jedec,lpddr3.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: LPDDR3 SDRAM compliant to JEDEC JESD209-3
10 - Krzysztof Kozlowski <krzk@kernel.org>
13 - $ref: jedec,lpddr-props.yaml#
18 - items:
19 - enum:
20 - samsung,K3QF2F20DB
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| /freebsd/usr.sbin/ctladm/ |
| H A D | ctladm.8 | 3 .\" Copyright (c) 2015-2021 Alexander Motin <mav@FreeBSD.org>
36 .\" $Id: //depot/users/kenm/FreeBSD-test2/usr.sbin/ctladm/ctladm.8#3 $
72 .Aq Fl f Ar file|-
77 .Ic write
82 .Aq Fl f Ar file|-
123 .Ic delay
197 .Aq Fl a | Fl c Ar connection-id | Fl i Ar name | Fl p Ar portal
200 .Aq Fl a | Fl c Ar connection-id | Fl i Ar name | Fl p Ar portal
207 .Aq Fl a | Fl c Ar controller-id | Fl h Ar name
213 utility is designed to provide a way to access and control the CAM Target
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| /freebsd/sys/dev/ath/ |
| H A D | ah_osdep.h | 1 /*-
2 * SPDX-License-Identifier: BSD-2-Clause
4 * Copyright (c) 2002-2008 Sam Leffler, Errno Consulting
34 * Atheros Hardware Access Layer (HAL) OS Dependent Definitions.
65 * Delay n microseconds.
67 #define OS_DELAY(_n) DELAY(_n)
79 * The hardware registers are native little-endian byte order.
80 * Big-endian hosts are handled by enabling hardware byte-swap
82 * domain registers are not byte swapped! Thus, on big-endian
83 * platforms we have to explicitly byte-swap those registers.
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| /freebsd/stand/efi/include/ |
| H A D | efipciio.h | 3 and DMA interfaces that a driver uses to access its PCI controller.
5 Copyright (c) 2006 - 2010, Intel Corporation. All rights reserved.<BR>
9 http://opensource.org/licenses/bsd-license.php
56 #define EFI_PCI_IO_ATTRIBUTE_ISA_MOTHERBOARD_IO 0x0001 ///< I/O cycles 0x0000-0x00FF (10 bit dec…
57 #define EFI_PCI_IO_ATTRIBUTE_ISA_IO 0x0002 ///< I/O cycles 0x0100-0x03FF or greater …
59 #define EFI_PCI_IO_ATTRIBUTE_VGA_MEMORY 0x0008 ///< MEM cycles 0xA0000-0xBFFFF (24 bit d…
60 #define EFI_PCI_IO_ATTRIBUTE_VGA_IO 0x0010 ///< I/O cycles 0x3B0-0x3BB and 0x3C0-0x3…
61 #define EFI_PCI_IO_ATTRIBUTE_IDE_PRIMARY_IO 0x0020 ///< I/O cycles 0x1F0-0x1F7, 0x3F6, 0x3F7…
62 #define EFI_PCI_IO_ATTRIBUTE_IDE_SECONDARY_IO 0x0040 ///< I/O cycles 0x170-0x177, 0x376, 0x377…
69 #define EFI_PCI_IO_ATTRIBUTE_EMBEDDED_DEVICE 0x2000 ///< Clear for an add-in PCI Device
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| /freebsd/sys/contrib/device-tree/Bindings/mtd/ |
| H A D | gpmc-nor.txt | 8 Documentation/devicetree/bindings/memory-controllers/omap-gpmc.txt
11 - bank-width: Width of NOR flash in bytes. GPMC supports 8-bit and
12 16-bit devices and so must be either 1 or 2 bytes.
13 - compatible: Documentation/devicetree/bindings/mtd/mtd-physmap.yaml
14 - gpmc,cs-on-ns: Chip-select assertion time
15 - gpmc,cs-rd-off-ns: Chip-select de-assertion time for reads
16 - gpmc,cs-wr-off-ns: Chip-select de-assertion time for writes
17 - gpmc,oe-on-ns: Output-enable assertion time
18 - gpmc,oe-off-ns: Output-enable de-assertion time
19 - gpmc,we-on-ns Write-enable assertion time
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| H A D | fsmc-nand.txt | 5 - compatible : "st,spear600-fsmc-nand", "stericsson,fsmc-nand"
6 - reg : Address range of the mtd chip
7 - reg-names: Should contain the reg names "fsmc_regs", "nand_data", "nand_addr" and "nand_cmd"
10 - bank-width : Width (in bytes) of the device. If not present, the width
12 - nand-skip-bbtscan: Indicates the BBT scanning should be skipped
13 - timings: array of 6 bytes for NAND timings. The meanings of these bytes
15 byte 0 TCLR : CLE to RE delay in number of AHB clock cycles, only 4 bits
18 byte 1 TAR : ALE to RE delay, 4 bits are valid. Same format as TCLR.
20 kept in Hi-Z (tristate) after the start of a write access.
21 Only valid for write transactions. Zero means zero cycles,
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| /freebsd/share/doc/smm/06.nfs/ |
| H A D | 2.t | 38 This section borrows heavily from work done on Spritely-NFS [Srinivasan89],
54 file whenever that file is write shared\**.
56 \** Write sharing occurs when at least one client is modifying a file while
60 There are three types of leases: read caching, write caching and non-caching.
65 A write caching lease allows for client caching of writes,
69 \** Cached write data is not yet pushed (written) to the server.
71 when a write cache lease has almost expired, it will attempt to
75 frequent RPCs Getattr, Setattr, Lookup, Readlink, Read, Write and Readdir
80 are not write cached.
88 a write caching lease and any other client,
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| /freebsd/sys/contrib/device-tree/Bindings/net/ |
| H A D | gpmc-eth.txt | 4 General-Purpose Memory Controller can be used to connect Pseudo-SRAM devices
12 Documentation/devicetree/bindings/memory-controllers/omap-gpmc.txt
18 Child nodes need to specify the GPMC bus address width using the "bank-width"
20 specify the I/O registers address width. Even when the GPMC has a maximum 16-bit
21 address width, it supports devices with 32-bit word registers.
23 OMAP2+ board, "bank-width = <2>;" and "reg-io-width = <4>;".
26 - bank-width: Address width of the device in bytes. GPMC supports 8-bit
27 and 16-bit devices and so must be either 1 or 2 bytes.
28 - compatible: Compatible string property for the ethernet child device.
29 - gpmc,cs-on-ns: Chip-select assertion time
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| /freebsd/sys/arm/arm/ |
| H A D | machdep_intr.c | 1 /*-
2 * Copyright (c) 2015-2016 Svatopluk Kraus
3 * Copyright (c) 2015-2016 Michal Meloun
42 * This is intended to be called from the post-filter and post-thread routines
44 * use bus_space_barrier() if it needs to ensure a write has reached the
52 * is, if the cpu writes to device A then device B, the write to device B could
53 * complete before the write to device A.
56 * writes to a device status-acknowledge register to clear the interrupt before
57 * returning. That write is posted to the L2 controller which "immediately"
63 * all this delay is happening, execution proceeds on the CPU, unwinding its way
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| /freebsd/sys/dev/atkbdc/ |
| H A D | atkbdc.c | 1 /*-
2 * SPDX-License-Identifier: BSD-3-Clause
4 * Copyright (c) 1996-1999
5 * Kazutaka YOKOTA (yokota@zodiac.mech.utsunomiya-u.ac.jp)
66 #define availq(q) ((q)->head != (q)->tail)
68 #define emptyq(q) ((q)->tail = (q)->head = (q)->qcount = 0)
70 #define emptyq(q) ((q)->tail = (q)->head = 0)
73 #define read_data(k) (bus_space_read_1((k)->iot, (k)->ioh0, 0))
74 #define read_status(k) (bus_space_read_1((k)->iot, (k)->ioh1, 0))
76 (bus_space_write_1((k)->iot, (k)->ioh0, 0, (d)))
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| /freebsd/sys/contrib/device-tree/src/arm/ti/omap/ |
| H A D | omap3-gta04a5one.dts | 1 // SPDX-License-Identifier: GPL-2.0-only
3 * Copyright (C) 2014-18 H. Nikolaus Schaller <hns@goldelico.com>
6 #include "omap3-gta04a5.dts"
13 gpmc_pins: gpmc-pins {
14 pinctrl-single,pins = <
45 pinctrl-names = "default";
46 pinctrl-0 = <&gpmc_pins>;
48 /delete-node/ nand@0,0;
52 #address-cells = <1>;
53 #size-cells = <1>;
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| /freebsd/share/man/man4/ |
| H A D | ioat.4 | 34 .Bd -ragged -offset indent
40 .Bd -literal -offset indent
69 .Fn ioat_set_interrupt_coalesce "bus_dmaengine_t dmaengine" "uint16_t delay"
150 Blockfill operations can be used to write a 64-bit pattern to memory.
163 The hardware can delay and coalesce interrupts on a given channel for a
167 Software can control this on a per-channel basis with the
177 All operations are safe to use in a non-blocking context with the
211 chunks of memory and only write out the result once.
242 argument to either routine is non-NULL, the CRC32C engine is initialized with
251 object for exclusive access to enqueue operations on that channel.
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| /freebsd/sys/arm/mv/armada38x/ |
| H A D | armada38x_rtc.c | 1 /*-
69 #define MV_RTC_LOCK(sc) mtx_lock_spin(&(sc)->mutex)
70 #define MV_RTC_UNLOCK(sc) mtx_unlock_spin(&(sc)->mutex)
98 { -1, 0 }
143 {"marvell,armada-380-rtc", RTC_A38X},
144 {"marvell,armada-8k-rtc", RTC_A8K},
159 DELAY(500000); in mv_rtc_reset()
163 DELAY(62); in mv_rtc_reset()
167 DELAY(62); in mv_rtc_reset()
175 /* Setup nominal register access timing */ in mv_rtc_reset()
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| /freebsd/contrib/ntp/html/ |
| H A D | debug.html | 1 <!DOCTYPE HTML PUBLIC "-//W3C//DTD HTML 4.01 Transitional//EN">
4 <meta http-equiv="content-type" content="text/html;charset=iso-8859-1">
14 <!-- #BeginDate format:En2m -->16-Jul-2014 08:38<!-- #EndDate -->
21 …- standard NTP query program</a>, either on the local server or from a remote machine. In special …
22 …-d</tt> command-line option. Without the option the daemon detaches from the controlling terminal …
45 …licit calendar dates, times are in milliseconds and frequencies are in parts-per-million (PPM).</p>
52 …<li>The <tt>reach</tt> peer variable is an 8-bit shift register displayed in octal format. When a …
54 …delay, offset and jitter statistics for each of the last eight measurement rounds. These statistic…
55 …<li>The synchronization distance, defined as one-half the delay plus the dispersion, represents th…
60 <h4>Access Controls</h4>
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| /freebsd/sys/dev/sound/pci/ |
| H A D | csa.c | 1 /*-
2 * SPDX-License-Identifier: BSD-2-Clause
9 * Copyright (c) 1996-1998 Crystal Semiconductor Corp.
192 subcard = card->cards; in csa_findsubcard()
211 device_set_desc(dev, card->name); in csa_probe()
229 scp->dev = dev; in csa_attach()
234 resp = &scp->res; in csa_attach()
235 scp->card = csa_findsubcard(dev); in csa_attach()
236 scp->binfo.card = scp->card; in csa_attach()
237 printf("csa: card is %s\n", scp->card->name); in csa_attach()
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