Lines Matching +full:write +full:- +full:access +full:- +full:delay
5 - compatible : "st,spear600-fsmc-nand", "stericsson,fsmc-nand"
6 - reg : Address range of the mtd chip
7 - reg-names: Should contain the reg names "fsmc_regs", "nand_data", "nand_addr" and "nand_cmd"
10 - bank-width : Width (in bytes) of the device. If not present, the width
12 - nand-skip-bbtscan: Indicates the BBT scanning should be skipped
13 - timings: array of 6 bytes for NAND timings. The meanings of these bytes
15 byte 0 TCLR : CLE to RE delay in number of AHB clock cycles, only 4 bits
18 byte 1 TAR : ALE to RE delay, 4 bits are valid. Same format as TCLR.
20 kept in Hi-Z (tristate) after the start of a write access.
21 Only valid for write transactions. Zero means zero cycles,
32 - bank: default NAND bank to use (0-3 are valid, 0 is the default).
33 - nand-ecc-mode : see nand-controller.yaml
34 - nand-ecc-strength : see nand-controller.yaml
35 - nand-ecc-step-size : see nand-controller.yaml
37 Can support 1-bit HW ECC (default) or if stronger correction is required,
38 software-based BCH.
43 compatible = "st,spear600-fsmc-nand";
44 #address-cells = <1>;
45 #size-cells = <1>;
50 reg-names = "fsmc_regs", "nand_data", "nand_addr", "nand_cmd";
52 bank-width = <1>;
53 nand-skip-bbtscan;