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/linux/Documentation/devicetree/bindings/remoteproc/
H A Dti,omap-remoteproc.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/remoteproc/ti,omap-remoteproc.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Suman Anna <s-anna@ti.com>
13 The OMAP family of SoCs usually have one or more slave processor sub-systems
14 that are used to offload some of the processor-intensive tasks, or to manage
17 The processor cores in the sub-system are usually behind an IOMMU, and may
18 contain additional sub-modules like Internal RAM and/or ROMs, L1 and/or L2
21 The OMAP SoCs usually have a DSP processor sub-system and/or an IPU processor
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/linux/arch/arm/boot/dts/ti/omap/
H A Ddra7-ipu-dsp-common.dtsi1 // SPDX-License-Identifier: GPL-2.0
8 mbox_ipu1_ipc3x: mbox-ipu1-ipc3x {
11 mbox_dsp1_ipc3x: mbox-dsp1-ipc3x {
18 mbox_ipu2_ipc3x: mbox-ipu2-ipc3x {
25 ti,timers = <&timer3>;
26 ti,watchdog-timers = <&timer4>, <&timer9>;
31 ti,timers = <&timer11>;
32 ti,watchdog-timers = <&timer7>, <&timer8>;
37 ti,timers = <&timer5>;
38 ti,watchdog-timers = <&timer10>;
H A Domap5-uevm.dts1 // SPDX-License-Identifier: GPL-2.0-only
3 * Copyright (C) 2013 Texas Instruments Incorporated - https://www.ti.com/
5 /dts-v1/;
7 #include "omap5-board-common.dtsi"
11 compatible = "ti,omap5-uevm", "ti,omap5";
18 reserved-memory {
19 #address-cells = <2>;
20 #size-cells = <2>;
23 dsp_memory_region: dsp-memory@95000000 {
24 compatible = "shared-dma-pool";
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H A Ddra74-ipu-dsp-common.dtsi1 // SPDX-License-Identifier: GPL-2.0
6 #include "dra7-ipu-dsp-common.dtsi"
9 mbox_dsp2_ipc3x: mbox-dsp2-ipc3x {
16 ti,timers = <&timer6>;
17 ti,watchdog-timers = <&timer13>;
/linux/drivers/watchdog/
H A Di6300esb.c1 // SPDX-License-Identifier: GPL-2.0-or-later
3 * i6300esb: Watchdog timer driver for Intel 6300ESB chipset
8 * based on i810-tco.c which is in turn based on softdog.c
12 * 6300ESB chip : document number 300641-004
21 * Change driver to use the watchdog subsystem
35 #include <linux/watchdog.h>
49 #define ESB_TIMER1_REG(w) ((w)->base + 0x00)/* Timer1 value after each reset */
50 #define ESB_TIMER2_REG(w) ((w)->base + 0x04)/* Timer2 value after each reset */
51 #define ESB_GINTSR_REG(w) ((w)->base + 0x08)/* General Interrupt Status Reg */
52 #define ESB_RELOAD_REG(w) ((w)->base + 0x0c)/* Reload register */
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H A Dcpwd.c1 // SPDX-License-Identifier: GPL-2.0-only
2 /* cpwd.c - driver implementation for hardware watchdog
3 * timers found on Sun Microsystems CP1400 and CP1500 boards.
5 * This device supports both the generic Linux watchdog
6 * interface and Solaris-compatible ioctls as best it is
38 #include <asm/watchdog.h>
42 #define WD_OBPNAME "watchdog"
43 #define WD_BADMODEL "SUNW,501-5336"
60 #define WD_STAT_INIT 0x01 /* Watchdog timer is initialized */
61 #define WD_STAT_BSTOP 0x02 /* Watchdog timer is brokenstopped */
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H A Dgeodewdt.c1 // SPDX-License-Identifier: GPL-2.0-or-later
2 /* Watchdog timer for machines with the CS5535/CS5536 companion chip
4 * Copyright (C) 2006-2007, Advanced Micro Devices, Inc.
14 #include <linux/watchdog.h>
36 "Watchdog timeout in seconds. 1<= timeout <=131, default="
42 "Watchdog cannot be stopped once started (default="
71 return -EINVAL; in geodewdt_set_heartbeat()
85 return -EBUSY; in geodewdt_open()
100 pr_crit("Unexpected close - watchdog is not stopping\n"); in geodewdt_release()
123 return -EFAULT; in geodewdt_write()
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H A Dpseries-wdt.c1 // SPDX-License-Identifier: GPL-2.0-or-later
15 #include <linux/watchdog.h>
17 #define DRV_NAME "pseries-wdt"
24 * Bits 48-55: "operation"
31 * Bits 56-63: "timeoutAction" (for "Start Watchdog" only)
65 * - For the "Query Watchdog Capabilities" operation, a 64-bit
80 MODULE_PARM_DESC(action, "Action taken when watchdog expires (default="
85 MODULE_PARM_DESC(nowayout, "Watchdog cannot be stopped once started (default="
91 MODULE_PARM_DESC(timeout, "Initial watchdog timeout in seconds (default="
97 unsigned long num; /* Watchdog numbers are 1-based */
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H A Dmax63xx_wdt.c1 // SPDX-License-Identifier: GPL-2.0-only
3 * drivers/char/watchdog/max63xx_wdt.c
5 * Driver for max63{69,70,71,72,73,74} watchdog timers
9 * This driver assumes the watchdog pins are memory mapped (as it is
20 #include <linux/watchdog.h>
36 * to ping the watchdog.
103 while (table->twd) { in max63xx_select_timeout()
104 if (value <= table->twd) { in max63xx_select_timeout()
105 if (nodelay && table->tdelay == 0) in max63xx_select_timeout()
122 wdt->ping(wdt); in max63xx_wdt_ping()
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H A Dmachzwd.c1 // SPDX-License-Identifier: GPL-2.0-or-later
3 * MachZ ZF-Logic Watchdog Timer driver for Linux
6 * any of this software. This material is provided "AS-IS" in
13 * We have two timers (wd#1, wd#2) driven by a 32 KHz clock with the
15 * wd#1 - 2 seconds;
16 * wd#2 - 7.2 ms;
21 * 14-Dec-2001 Matt Domsch <Matt_Domsch@dell.com>
33 #include <linux/watchdog.h>
87 MODULE_DESCRIPTION("MachZ ZF-Logic Watchdog driver");
93 "Watchdog cannot be stopped once started (default="
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H A Dshwdt.c1 // SPDX-License-Identifier: GPL-2.0-or-later
3 * drivers/watchdog/shwdt.c
5 * Watchdog driver for integrated watchdog in the SuperH processors.
7 * Copyright (C) 2001 - 2012 Paul Mundt <lethal@linux-sh.org>
9 * 14-Dec-2001 Matt Domsch <Matt_Domsch@dell.com>
12 * 19-Apr-2002 Rob Radez <rob@osinvestor.com>
25 #include <linux/watchdog.h>
33 #include <asm/watchdog.h>
35 #define DRV_NAME "sh-wdt"
39 * values, consult the asm-sh/watchdog.h. Overload this at module load
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/linux/Documentation/arch/mips/
H A Dingenic-tcu.rst1 .. SPDX-License-Identifier: GPL-2.0
7 The Timer/Counter Unit (TCU) in Ingenic JZ47xx SoCs is a multi-function
9 counters, timers, or PWM.
11 - JZ4725B, JZ4750, JZ4755 only have six TCU channels. The other SoCs all
14 - JZ4725B introduced a separate channel, called Operating System Timer
15 (OST). It is a 32-bit programmable timer. On JZ4760B and above, it is
16 64-bit.
18 - Each one of the TCU channels has its own clock, which can be reparented to three
21 - The watchdog and OST hardware blocks also feature a TCSR register with the same
23 - The TCU registers used to gate/ungate can also gate/ungate the watchdog and
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/linux/drivers/acpi/arm64/
H A Dgtdt.c1 // SPDX-License-Identifier: GPL-2.0-only
23 * struct acpi_gtdt_descriptor - Store the key info of GTDT for all functions
45 gh->length != 0 && in platform_timer_valid()
46 platform_timer + gh->length <= acpi_gtdt_desc.gtdt_end); in platform_timer_valid()
53 return platform_timer + gh->length; in next_platform_timer()
64 return gh->type == ACPI_GTDT_TYPE_TIMER_BLOCK; in is_timer_block()
72 if (gh->type != ACPI_GTDT_TYPE_WATCHDOG) in is_non_secure_watchdog()
75 return !(wd->timer_flags & ACPI_GTDT_WATCHDOG_SECURE); in is_non_secure_watchdog()
92 * acpi_gtdt_map_ppi() - Map the PPIs of per-cpu arch_timer.
96 * So we only handle the non-secure timer PPIs,
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/linux/arch/sparc/include/uapi/asm/
H A Dwatchdog.h1 /* SPDX-License-Identifier: GPL-2.0 WITH Linux-syscall-note */
4 * watchdog - Driver interface for the hardware watchdog timers
14 #include <linux/watchdog.h>
16 /* Solaris compatibility ioctls--
17 * Ref. <linux/watchdog.h> for standard linux watchdog ioctls
/linux/Documentation/devicetree/bindings/watchdog/
H A Dralink,rt2880-wdt.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/watchdog/ralink,rt2880-wdt.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Ralink Watchdog Timers
10 - Sergio Paracuellos <sergio.paracuellos@gmail.com>
13 - $ref: watchdog.yaml#
17 const: ralink,rt2880-wdt
32 - compatible
33 - reg
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H A Dmediatek,mt7621-wdt.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/watchdog/mediatek,mt7621-wdt.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Ralink Watchdog Timers
10 - Sergio Paracuellos <sergio.paracuellos@gmail.com>
13 - $ref: watchdog.yaml#
17 const: mediatek,mt7621-wdt
29 - compatible
30 - reg
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H A Dmaxim,max63xx.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/watchdog/maxim,max63xx.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Maxim 63xx Watchdog Timers
10 - Marc Zyngier <maz@kernel.org>
11 - Linus Walleij <linus.walleij@linaro.org>
14 - $ref: watchdog.yaml#
15 - $ref: /schemas/memory-controllers/mc-peripheral-props.yaml#
20 - maxim,max6369
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H A Dmarvell,cn10624-wdt.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/watchdog/marvell,cn10624-wdt.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Marvell Global Timer (GTI) system watchdog
10 - Bharat Bhushan <bbhushan2@marvell.com>
13 - $ref: watchdog.yaml#
18 - enum:
19 - marvell,cn9670-wdt
20 - marvell,cn10624-wdt
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H A Datmel,at91sam9-wdt.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
4 ---
5 $id: http://devicetree.org/schemas/watchdog/atmel,at91sam9-wdt.yaml#
6 $schema: http://devicetree.org/meta-schemas/core.yaml#
8 title: Atmel Watchdog Timers
11 - Eugen Hristev <eugen.hristev@microchip.com>
15 const: atmel,at91sam9260-wdt
26 atmel,max-heartbeat-sec:
32 atmel,min-heartbeat-sec:
35 must be smaller than the max-heartbeat-sec value. It is used to
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/linux/Documentation/devicetree/bindings/mfd/
H A Dbrcm,twd.yaml1 # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Broadcom's Timer-Watchdog (aka TWD)
10 - Rafał Miłecki <rafal@milecki.pl>
13 Broadcom has a Timer-Watchdog block used in multiple SoCs (e.g., BCM4908,
15 registers layout). This block consists of: timers, watchdog and optionally a
21 - enum:
22 - brcm,bcm4908-twd
23 - brcm,bcm7038-twd
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/linux/Documentation/watchdog/
H A Dwdt.rst2 WDT Watchdog Timer Interfaces For The Linux Operating System
9 - ICS WDT501-P
10 - ICS WDT501-P (no fan tachometer)
11 - ICS WDT500-P
13 All the interfaces provide /dev/watchdog, which when open must be written
15 time another timeout. In the case of the software watchdog the ability to
17 boards physically pull the machine down off their own onboard timers and
26 The ICS ISA-bus wdt card cannot be safely probed for. Instead you need to
34 heartbeat Watchdog heartbeat in seconds (default 60)
35 nowayout Watchdog cannot be stopped once started (kernel
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/linux/Documentation/devicetree/bindings/interrupt-controller/
H A Dmti,gic.yaml1 # SPDX-License-Identifier: GPL-2.0-only
3 ---
4 $id: http://devicetree.org/schemas/interrupt-controller/mti,gic.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Paul Burton <paulburton@kernel.org>
11 - Thomas Bogendoerfer <tsbogend@alpha.franken.de>
15 It also supports local (per-processor) interrupts and software-generated
16 interrupts which can be used as IPIs. The GIC also includes a free-running
17 global timer, per-CPU count/compare timers, and a watchdog.
23 "#interrupt-cells":
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/linux/arch/x86/platform/intel-mid/
H A Dintel-mid.c1 // SPDX-License-Identifier: GPL-2.0-only
27 #include <asm/intel-mid.h>
54 x86_init.timers.setup_percpu_clockev = setup_boot_APIC_clock; in intel_mid_time_init()
81 * watchdog or lock debug. Reading io port 0x61 results in 0xff which
98 x86_init.timers.timer_init = intel_mid_time_init; in x86_intel_mid_early_setup()
99 x86_init.timers.setup_percpu_clockev = x86_init_noop; in x86_intel_mid_early_setup()
/linux/arch/powerpc/kernel/
H A Dwatchdog.c1 // SPDX-License-Identifier: GPL-2.0
3 * Watchdog support on powerpc systems.
7 * This uses code from arch/sparc/kernel/nmi.c and kernel/watchdog.c
10 #define pr_fmt(fmt) "watchdog: " fmt
35 * The powerpc watchdog ensures that each CPU is able to service timers.
36 * The watchdog sets up a simple timer on each CPU to run once per timer
37 * period, and updates a per-cpu timestamp and a "pending" cpumask. This is
41 * The local soft-NMI, and the SMP checker.
43 * The soft-NMI checker can detect lockups on the local CPU. When interrupts
44 * are disabled with local_irq_disable(), platforms that use soft-masking
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/linux/Documentation/devicetree/bindings/power/reset/
H A Dkeystone-reset.txt6 The Keystone SoCs can contain up to 4 watchdog timers to reset
7 SoC. Each watchdog timer event input is connected to the Reset Mux
14 - compatible: ti,keystone-reset
16 - ti,syscon-pll: phandle/offset pair. The phandle to syscon used to
20 - ti,syscon-dev: phandle/offset pair. The phandle to syscon used to
26 - ti,soft-reset: Boolean option indicating soft reset.
29 - ti,wdt-list: WDT list that can cause SoC reset. It's not related
40 pllctrl: pll-controller@2310000 {
41 compatible = "ti,keystone-pllctrl", "syscon";
45 devctrl: device-state-control@2620000 {
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