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/freebsd/crypto/openssl/crypto/perlasm/
H A Driscv.pm420 # vadd.vv vd, vs2, vs1, vm
423 my $vs2 = read_vreg shift;
426 return ".word ".($template | ($vm << 25) | ($vs2 << 20) | ($vs1 << 15) | ($vd << 7));
430 # vadd.vx vd, vs2, rs1, vm
433 my $vs2 = read_vreg shift;
436 return ".word ".($template | ($vm << 25) | ($vs2 << 20) | ($rs1 << 15) | ($vd << 7));
440 # vsub.vv vd, vs2, vs1, vm
443 my $vs2 = read_vreg shift;
446 return ".word ".($template | ($vm << 25) | ($vs2 << 20) | ($vs1 << 15) | ($vd << 7));
450 # vsub.vx vd, vs2, rs1, vm
[all …]
/freebsd/contrib/llvm-project/llvm/lib/Target/RISCV/
H A DRISCVInstrInfoV.td336 // indexed load vd, (rs1), vs2, vm
340 (ins GPRMemZeroOffset:$rs1, VR:$vs2, VMaskOp:$vm), opcodestr,
341 "$vd, $rs1, $vs2$vm">;
362 // indexed segment load vd, (rs1), vs2, vm
367 (ins GPRMemZeroOffset:$rs1, VR:$vs2, VMaskOp:$vm), opcodestr,
368 "$vd, $rs1, $vs2$vm">;
400 // indexed store vd, vs3, (rs1), vs2, vm
403 (ins VR:$vs3, GPRMemZeroOffset:$rs1, VR:$vs2, VMaskOp:$vm),
404 opcodestr, "$vs3, $rs1, $vs2$vm">;
418 // segment store vd, vs3, (rs1), vs2, vm
[all …]
H A DRISCVInstrFormatsV.td110 bits<5> vs2;
117 let Inst{24-20} = vs2;
130 bits<5> vs2;
137 let Inst{24-20} = vs2;
147 class RVInstV2<bits<6> funct6, bits<5> vs2, RISCVVFormat opv, dag outs, dag ins,
156 let Inst{24-20} = vs2;
169 bits<5> vs2;
176 let Inst{24-20} = vs2;
189 bits<5> vs2;
195 let Inst{24-20} = vs2;
[all …]
H A DRISCVInstrInfoZvk.td35 bits<5> vs2;
43 let Inst{24-20} = vs2;
56 (ins VR:$vs2, uimm6:$imm, VMaskOp:$vm),
57 opcodestr # ".vi", "$vd, $vs2, $imm$vm">,
61 // op vd, vs2, vs1
67 // op vd, vs2, vs1
70 (ins VR:$vd, VR:$vs2, VR:$vs1),
71 opcodestr, "$vd, $vs2, $vs1"> {
77 // op vd, vs2, imm
84 // op vd, vs2, imm where vd is also a source regardless of tail policy
[all …]
H A DRISCVInstrInfoXTHead.td58 // op vd, vs1, vs2, vm (reverse the order of vs1 and vs2)
62 (ins VR:$vd, VR:$vs1, VR:$vs2, VMaskOp:$vm),
63 opcodestr, "$vd, $vs1, $vs2$vm"> {
68 // op vd, rs1, vs2, vm (reverse the order of rs1 and vs2)
72 (ins VR:$vd, GPR:$rs1, VR:$vs2, VMaskOp:$vm),
73 opcodestr, "$vd, $rs1, $vs2$vm"> {
H A DRISCVScheduleV.td477 // The LMUL range of read resource(VS2) for reduction operantion is between
479 // LMUL from VS2.
/freebsd/sys/net/
H A Dvnet.c514 struct vnet_sysinit *vs, *vs2; in vnet_register_sysinit() local
522 TAILQ_FOREACH(vs2, &vnet_constructors, link) { in vnet_register_sysinit()
523 if (vs2->subsystem > vs->subsystem) in vnet_register_sysinit()
525 if (vs2->subsystem == vs->subsystem && vs2->order > vs->order) in vnet_register_sysinit()
528 if (vs2 != NULL) in vnet_register_sysinit()
529 TAILQ_INSERT_BEFORE(vs2, vs, link); in vnet_register_sysinit()
563 struct vnet_sysinit *vs, *vs2; in vnet_register_sysuninit() local
569 TAILQ_FOREACH(vs2, &vnet_destructors, link) { in vnet_register_sysuninit()
570 if (vs2->subsystem > vs->subsystem) in vnet_register_sysuninit()
572 if (vs2->subsystem == vs->subsystem && vs2->order > vs->order) in vnet_register_sysuninit()
[all …]
/freebsd/crypto/openssl/crypto/modes/asm/
H A Dghash-riscv64-zvkg.pl114 my ($VD,$VS2) = ("v1","v2");
122 @{[vle32_v $VS2, $Htable]}
124 @{[vgmul_vv $VD, $VS2]}
/freebsd/contrib/llvm-project/clang/lib/Sema/
H A DSemaRISCV.cpp747 // bit_27_26, bit_11_7, vs2, simm5 in CheckBuiltinFunctionCall()
759 // bit_27_26, vs2, simm5 in CheckBuiltinFunctionCall()
768 // bit_27_26, vd, vs2, simm5 in CheckBuiltinFunctionCall()
779 // bit_27_26, bit_11_7, vs2, xs1/vs1 in CheckBuiltinFunctionCall()
789 // bit_27_26, vd, vs2, xs1 in CheckBuiltinFunctionCall()
794 // bit_27_26, vs2, xs1/vs1 in CheckBuiltinFunctionCall()
803 // bit_27_26, vd, vs2, xs1/vs1 in CheckBuiltinFunctionCall()
806 // bit_26, bit_11_7, vs2, fs1 in CheckBuiltinFunctionCall()
815 // bit_26, vd, vs2, fs1 in CheckBuiltinFunctionCall()
818 // bit_26, vs2, fs1 in CheckBuiltinFunctionCall()
/freebsd/sys/contrib/device-tree/src/arm64/mediatek/
H A Dmt8183-kukui.dtsi417 vsys-vs2-supply = <&reg_vsys>;
419 vs2-ldo1-supply = <&mt6358_vdram1_reg>;
420 vs2-ldo2-supply = <&mt6358_vs2_reg>;
421 vs2-ldo3-supply = <&mt6358_vs2_reg>;
422 vs2-ldo4-supply = <&mt6358_vs2_reg>;
H A Dmt8186-corsola.dtsi1297 vsys-vs2-supply = <&pp4200_z2>;
1299 vs2-ldo1-supply = <&mt6366_vdram1_reg>;
1300 vs2-ldo2-supply = <&mt6366_vs2_reg>;
1301 vs2-ldo3-supply = <&mt6366_vs2_reg>;
1373 mt6366_vs2_reg: vs2 {
H A Dmt6359.dtsi60 regulator-name = "vs2";
H A Dmt6358.dtsi85 regulator-name = "vs2";
/freebsd/sys/contrib/device-tree/src/arm/qcom/
H A Dqcom-pm8941.dtsi224 interrupt-names = "ocp-5vs1", "ocp-5vs2";
243 pm8941_5vs2: 5vs2 {
/freebsd/sys/contrib/openzfs/module/zfs/
H A Dspa_stats.c434 vdev_get_stats(spa->spa_root_vdev, &ts->vs2); in spa_txg_history_fini_io()
439 ts->vs2.vs_bytes[ZIO_TYPE_READ] - ts->vs1.vs_bytes[ZIO_TYPE_READ], in spa_txg_history_fini_io()
440 ts->vs2.vs_bytes[ZIO_TYPE_WRITE] - ts->vs1.vs_bytes[ZIO_TYPE_WRITE], in spa_txg_history_fini_io()
441 ts->vs2.vs_ops[ZIO_TYPE_READ] - ts->vs1.vs_ops[ZIO_TYPE_READ], in spa_txg_history_fini_io()
442 ts->vs2.vs_ops[ZIO_TYPE_WRITE] - ts->vs1.vs_ops[ZIO_TYPE_WRITE], in spa_txg_history_fini_io()
/freebsd/sys/dev/ntb/test/
H A Dntb_tool.c457 bool vs1, vs2, vs3; in parse_mw_buf() local
460 vs1 = vs2 = vs3 = false; in parse_mw_buf()
472 vs2 = true; in parse_mw_buf()
481 } else if (!vs2 && !strcmp(op2, "nbytes")) { in parse_mw_buf()
483 vs2 = true; in parse_mw_buf()
491 } else if (!vs2 && !strcmp(op3, "nbytes")) { in parse_mw_buf()
/freebsd/contrib/llvm-project/lldb/source/Plugins/Process/Utility/
H A DRegisterInfos_ppc64le.h211 DEFINE_VSX(vs2, LLDB_INVALID_REGNUM), \
396 uint32_t vs2[4]; member
/freebsd/sys/contrib/device-tree/Bindings/regulator/
H A Dqcom,smd-rpm-regulator.yaml55 lvs3, 5vs1, 5vs2
H A Dqcom,spmi-regulator.yaml281 - const: ocp-5vs2
H A Dqcom,smd-rpm-regulator.txt255 lvs3, 5vs1, 5vs2
H A Dqcom,spmi-regulator.txt212 5vs1, 5vs2
H A Dmt6358-regulator.txt82 regulator-name = "vs2";
H A Dmt6359-regulator.yaml146 regulator-name = "vs2";
/freebsd/contrib/llvm-project/llvm/lib/Target/PowerPC/
H A DPPCInstrMMA.td1064 (INSERT_SUBREG (IMPLICIT_DEF), $vs2, sub_vsx1),
1083 def : Pat<(v512i1 (PPCAccBuild v4i32:$vs1, v4i32:$vs0, v4i32:$vs3, v4i32:$vs2)),
1086 v16i8:$vs3, v16i8:$vs2)),
1100 def : Pat<(v512i1 (PPCAccBuild v4i32:$vs1, v4i32:$vs0, v4i32:$vs3, v4i32:$vs2)),
1103 v16i8:$vs3, v16i8:$vs2)),
H A DPPCScheduleP7.td

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