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/linux/Documentation/devicetree/bindings/rtc/
H A Dnvidia,vrs-10.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/rtc/nvidia,vrs-10.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Shubhi Garg <shgarg@nvidia.com>
13 NVIDIA VRS-10 (Voltage Regulator Specification) is a Power Management IC
15 The device includes a real-time clock (RTC) with 32kHz clock output and
16 backup battery support, alarm functionality for system wake-up from
18 and an interrupt controller for managing VRS events.
22 const: nvidia,vrs-10
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/linux/arch/powerpc/kernel/
H A Dvecemu.c1 // SPDX-License-Identifier: GPL-2.0
36 * Computes an estimate of 2^x. The `s' argument is the 32-bit
37 * single-precision floating-point representation of x.
45 exp = ((s >> 23) & 0xff) - 127; in eexp2()
50 /* 2^-big = 0, 2^+big = +Inf */ in eexp2()
53 if (exp < -23) in eexp2()
61 pwr >>= -exp; in eexp2()
63 pwr = -pwr; in eexp2()
69 if (exp < -23) in eexp2()
85 exp = -exp; in eexp2()
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H A Dtm.S1 /* SPDX-License-Identifier: GPL-2.0 */
10 #include <asm/asm-offsets.h>
12 #include <asm/ppc-opcode.h>
16 #include <asm/feature-fixups.h>
46 #define TM_FRAME_L0 TM_FRAME_SIZE-16
47 #define TM_FRAME_L1 TM_FRAME_SIZE-8
89 /* Passed an 8-bit failure cause as first argument. */
99 * - Performs a full reclaim. This destroys outstanding
102 * thread->regs is unchanged.
118 stdu r1, -TM_FRAME_SIZE(r1)
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/linux/tools/testing/selftests/powerpc/include/
H A Dinstructions.h1 /* SPDX-License-Identifier: GPL-2.0 */
10 (0x7c00060c | (RA) << (31-15) | (RB) << (31-20) | (L) << (31-10))
34 (0x7c00070c | (RA) << (31-15) | (RB) << (31-20) | (L) << (31-10) | (RC) << (31-31))
130 /* Prefixed Floating-Point Load/Store Instructions */
141 #define PSTXSD(vrs, a, r, d) PREFIX_8LS(0xb8000000, vrs, a, r, d) argument
142 #define PSTXSSP(vrs, a, r, d) PREFIX_8LS(0xbc000000, vrs, a, r, d) argument
/linux/arch/arm64/boot/dts/nvidia/
H A Dtegra234-p3701.dtsi1 // SPDX-License-Identifier: GPL-2.0
42 dma-controller@2930000 {
46 interrupt-controller@2a40000 {
59 vcc-supply = <&vdd_1v8_hs>;
60 address-width = <8>;
63 read-only;
71 compatible = "jedec,spi-nor";
73 spi-max-frequency = <102000000>;
74 spi-tx-bus-width = <4>;
75 spi-rx-bus-width = <4>;
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H A Dtegra234-p3767.dtsi1 // SPDX-License-Identifier: GPL-2.0
29 dma-controller@2930000 {
33 interrupt-controller@2a40000 {
46 vcc-supply = <&vdd_1v8_hs>;
47 address-width = <8>;
50 read-only;
58 compatible = "jedec,spi-nor";
60 spi-max-frequency = <102000000>;
61 spi-tx-bus-width = <4>;
62 spi-rx-bus-width = <4>;
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/linux/lib/crypto/powerpc/
H A Dchacha-p10le-8x.S1 /* SPDX-License-Identifier: GPL-2.0-or-later */
5 # Copyright 2023- IBM Corp. All rights reserved
40 #include <asm/asm-offsets.h>
41 #include <asm/asm-compat.h>
51 .macro SAVE_VRS VRS OFFSET FRAME
53 stvx \VRS, 16, \FRAME
65 .macro RESTORE_VRS VRS OFFSET FRAME
67 lvx \VRS, 16, \FRAME
78 stdu 1,-752(1)
215 vadduwm 10, 10, 14
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H A Dpoly1305-p10le_64.S1 /* SPDX-License-Identifier: GPL-2.0-or-later */
5 # Copyright 2023- IBM Corp. All rights reserved
10 # Poly1305 - this version mainly using vector/VSX/Scalar
11 # - 26 bits limbs
12 # - Handle multiple 64 byte blcok.
17 # p = 2^130 - 5
25 # 07/22/21 - this revison based on the above sum of products. Setup r^4, r^3, r^2, r and s3, s2, …
56 #include <asm/asm-offsets.h>
57 #include <asm/asm-compat.h>
68 .macro SAVE_VRS VRS OFFSET FRAME
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/linux/Documentation/arch/loongarch/
H A Dintroduction.rst1 .. SPDX-License-Identifier: GPL-2.0
7 LoongArch is a new RISC ISA, which is a bit like MIPS or RISC-V. There are
8 currently 3 variants: a reduced 32-bit version (LA32R), a standard 32-bit
9 version (LA32S) and a 64-bit version (LA64). There are 4 privilege levels
18 registers (FPRs), vector registers (VRs) and control status registers (CSRs)
22 ----
24 LoongArch has 32 GPRs ( ``$r0`` ~ ``$r31`` ); each one is 32-bit wide in LA32
25 and 64-bit wide in LA64. ``$r0`` is hard-wired to zero, and the other registers
26 are not architecturally special. (Except ``$r1``, which is hard-wired as the
30 the LoongArch ELF psABI spec, in :ref:`References <loongarch-references>`:
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/linux/drivers/regulator/
H A Dstm32-vrefbuf.c1 // SPDX-License-Identifier: GPL-2.0-only
28 #define STM32_VREFBUF_AUTO_SUSPEND_DELAY_MS 10
37 /* Matches resp. VRS = 000b, 001b, 010b, 011b */
47 ret = pm_runtime_resume_and_get(priv->dev); in stm32_vrefbuf_enable()
51 val = readl_relaxed(priv->base + STM32_VREFBUF_CSR); in stm32_vrefbuf_enable()
53 writel_relaxed(val, priv->base + STM32_VREFBUF_CSR); in stm32_vrefbuf_enable()
58 * ~650us sleep should be enough for caps up to 1.5uF. Use 10ms as in stm32_vrefbuf_enable()
61 ret = readl_poll_timeout(priv->base + STM32_VREFBUF_CSR, val, in stm32_vrefbuf_enable()
64 dev_err(&rdev->dev, "stm32 vrefbuf timed out!\n"); in stm32_vrefbuf_enable()
65 val = readl_relaxed(priv->base + STM32_VREFBUF_CSR); in stm32_vrefbuf_enable()
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/linux/arch/s390/include/asm/
H A Dfpu-insn-asm.h1 /* SPDX-License-Identifier: GPL-2.0 */
16 #error only <asm/fpu-insn.h> can be included directly
23 /* GR_NUM - Retrieve general-purpose register number
61 \opd = 10
83 /* VX_NUM - Retrieve vector register number
125 \opd = 10
195 /* RXB - Compute most significant bit used vector registers
200 * are stored in instruction bits 8-11.
203 * are stored in instruction bits 12-15.
206 * are stored in instruction bits 16-19.
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/linux/Documentation/translations/zh_CN/arch/loongarch/
H A Dintroduction.rst1 .. SPDX-License-Identifier: GPL-2.0
3 .. include:: ../../disclaimer-zh_CN.rst
12 LoongArch是一种新的RISC ISA，在一定程度上类似于MIPS和RISC-V。LoongArch指令集
21 LoongArch的寄存器包括通用寄存器（GPRs）、浮点寄存器（FPRs）、向量寄存器（VRs）
25 ----------
32 :ref:`参考文献 <loongarch-references-zh_CN>`:
41 ``$r4``-``$r11`` ``$a0``-``$a7`` 参数寄存器 否
42 ``$r4``-``$r5`` ``$v0``-``$v1`` 返回值 否
43 ``$r12``-``$r20`` ``$t0``-``$t8`` 临时寄存器 否
46 ``$r23``-``$r31`` ``$s0``-``$s8`` 静态寄存器 是
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/linux/drivers/rtc/
H A Drtc-nvidia-vrs10.c1 // SPDX-License-Identifier: GPL-2.0-only
5 * SPDX-FileCopyrightText: Copyright (c) 2025 NVIDIA CORPORATION & AFFILIATES.
96 ret = i2c_smbus_read_byte_data(info->client, reg); in nvvrs_update_bits()
104 return i2c_smbus_write_byte_data(info->client, reg, val); in nvvrs_update_bits()
147 struct i2c_client *client = info->client; in nvvrs_rtc_disable_alarm()
184 * Multi-byte transfers are not supported with PEC enabled in nvvrs_rtc_read_time()
187 ret = i2c_smbus_read_byte_data(info->client, NVVRS_REG_RTC_T3); in nvvrs_rtc_read_time()
194 ret = i2c_smbus_read_byte_data(info->client, NVVRS_REG_RTC_T2); in nvvrs_rtc_read_time()
201 ret = i2c_smbus_read_byte_data(info->client, NVVRS_REG_RTC_T1); in nvvrs_rtc_read_time()
208 ret = i2c_smbus_read_byte_data(info->client, NVVRS_REG_RTC_T0); in nvvrs_rtc_read_time()
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/linux/fs/udf/
H A Dsuper.c1 // SPDX-License-Identifier: GPL-2.0-only
6 * Super block routines for the OSTA-UDF(tm) filesystem.
9 * OSTA-UDF(tm) = Optical Storage Technology Association
20 * (C) 1998-2004 Ben Fennema
27 * 10/01/98 dgb updated to allow (some) possibility of compiling w/2.0.34
28 * 10/16/98 attempting some multi-session support
29 * 10/17/98 added freespace count for "df"
51 #include <linux/crc-itu-t.h>
77 * Descriptor redirections. The chosen numbers are arbitrary - just that we
78 * hopefully don't limit any real use of rewritten inode on write-once media
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/linux/drivers/gpu/drm/amd/pm/swsmu/inc/pmfw_if/
H A Dsmu13_driver_if_v13_0_7.h59 #define FEATURE_VDDIO_MEM_SCALING_BIT 10
197 #define THROTTLER_TEMP_LIQUID0_BIT 10
222 #define FW_DSTATE_HSR_NON_STROBE_BIT 10
504 uint8_t SnapToDiscrete; // 0 - Fine grained DPM, 1 - Discrete DPM
507 LinearInt_t ConversionToAvfsClk; // Transfer function to AVFS Clock (GHz->GHz)
691 #define PP_OD_FEATURE_TEMPERATURE_BIT 10
970 uint8_t UseInputTelemetry; //applicable to SVI3 only and only to be set if VRs support
1016 …uint16_t Vmin_Hot_T0[PMFW_VOLT_PLANE_COUNT]; //In mV(Q2) Initial (pre-aging) Vse…
1017 …uint16_t Vmin_Cold_T0[PMFW_VOLT_PLANE_COUNT]; //In mV(Q2) Initial (pre-aging) Vse…
1018 …uint16_t Vmin_Hot_Eol[PMFW_VOLT_PLANE_COUNT]; //In mV(Q2) End-of-life Vset to be …
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H A Dsmu14_driver_if_v14_0.h56 #define FEATURE_DS_GFXCLK_BIT 10
205 #define THROTTLER_TEMP_LIQUID1_BIT 10
229 #define FW_DSTATE_HSR_NON_STROBE_BIT 10
517 uint8_t SnapToDiscrete; // 0 - Fine grained DPM, 1 - Discrete DPM
520 LinearInt_t ConversionToAvfsClk; // Transfer function to AVFS Clock (GHz->GHz)
595 MEM_VENDOR_PLACEHOLDER1, // 10
703 #define PP_OD_FEATURE_FCLK_BIT 10
1062 uint8_t SocketPowerLimitSpare[10];
1067 uint8_t UseInputTelemetry; //applicable to SVI3 only and only to be set if VRs support
1106 …uint16_t Vmin_Hot_T0[PMFW_VOLT_PLANE_COUNT]; //In mV(Q2) Initial (pre-aging) Vse…
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H A Dsmu13_driver_if_v13_0_0.h58 #define FEATURE_VDDIO_MEM_SCALING_BIT 10
196 #define THROTTLER_TEMP_LIQUID0_BIT 10
221 #define FW_DSTATE_HSR_NON_STROBE_BIT 10
503 uint8_t SnapToDiscrete; // 0 - Fine grained DPM, 1 - Discrete DPM
506 LinearInt_t ConversionToAvfsClk; // Transfer function to AVFS Clock (GHz->GHz)
677 #define PP_OD_FEATURE_TEMPERATURE_BIT 10
961 uint8_t UseInputTelemetry; //applicable to SVI3 only and only to be set if VRs support
1007 …uint16_t Vmin_Hot_T0[PMFW_VOLT_PLANE_COUNT]; //In mV(Q2) Initial (pre-aging) Vse…
1008 …uint16_t Vmin_Cold_T0[PMFW_VOLT_PLANE_COUNT]; //In mV(Q2) Initial (pre-aging) Vse…
1009 …uint16_t Vmin_Hot_Eol[PMFW_VOLT_PLANE_COUNT]; //In mV(Q2) End-of-life Vset to be …
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/linux/drivers/hwmon/
H A Dintel-m10-bmc-hwmon.c1 // SPDX-License-Identifier: GPL-2.0
3 * Intel MAX 10 BMC HWMON Driver
5 * Copyright (C) 2018-2020 Intel Corporation. All rights reserved.
10 #include <linux/mfd/intel-m10-bmc.h>
243 { 0x1a8, 0x0, 0x0, 0x0, 0x0, 1000, "QSFP28-1 Temperature" },
244 { 0x1ac, 0x0, 0x0, 0x0, 0x0, 1000, "QSFP28-2 Temperature" },
245 { 0x1b0, 0x0, 0x0, 0x0, 0x0, 1000, "QSFP28-3 Temperature" },
246 { 0x1b4, 0x0, 0x0, 0x0, 0x0, 1000, "QSFP28-4 Temperature" },
344 { 0x444, 0x448, 0x44c, 0x0, 0x0, 500, "FPGA E-TILE Temperature #1" },
345 { 0x450, 0x454, 0x458, 0x0, 0x0, 500, "FPGA E-TILE Temperature #2" },
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/linux/arch/powerpc/platforms/powernv/
H A Dopal.c1 // SPDX-License-Identifier: GPL-2.0-or-later
33 #include <asm/imc-pmu.h>
80 /* Do the actual re-init, This will clobber all FPRs, VRs, etc... in opal_configure_cores()
106 if (cur_cpu_spec->cpu_restore) in opal_configure_cores()
107 cur_cpu_spec->cpu_restore(); in opal_configure_cores()
119 basep = of_get_flat_dt_prop(node, "opal-base-address", &basesz); in early_init_dt_scan_opal()
120 entryp = of_get_flat_dt_prop(node, "opal-entry-address", &entrysz); in early_init_dt_scan_opal()
121 sizep = of_get_flat_dt_prop(node, "opal-runtime-size", &runtimesz); in early_init_dt_scan_opal()
137 if (of_flat_dt_is_compatible(node, "ibm,opal-v3")) { in early_init_dt_scan_opal()
156 prop = of_get_flat_dt_prop(node, "mcheck-recoverable-ranges", &psize); in early_init_dt_scan_recoverable_ranges()
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/linux/drivers/video/fbdev/sis/
H A Dinit.c10 * Copyright (C) 2001-2005 by Thomas Winischhofer, Vienna, Austria
27 * * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307, USA
55 * Formerly based on non-functional code-fragements for 300 series by SiS, Inc.
81 SiS_Pr->SiS_SModeIDTable = SiS_SModeIDTable; in InitCommonPointer()
82 SiS_Pr->SiS_StResInfo = SiS_StResInfo; in InitCommonPointer()
83 SiS_Pr->SiS_ModeResInfo = SiS_ModeResInfo; in InitCommonPointer()
84 SiS_Pr->SiS_StandTable = SiS_StandTable; in InitCommonPointer()
86 SiS_Pr->SiS_NTSCTiming = SiS_NTSCTiming; in InitCommonPointer()
87 SiS_Pr->SiS_PALTiming = SiS_PALTiming; in InitCommonPointer()
88 SiS_Pr->SiS_HiTVSt1Timing = SiS_HiTVSt1Timing; in InitCommonPointer()
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/linux/arch/s390/kvm/
H A Dkvm-s390.c1 // SPDX-License-Identifier: GPL-2.0
13 #define pr_fmt(fmt) "kvm-s390: " fmt
16 #include <linux/entry-virt.h>
38 #include <asm/access-regs.h>
39 #include <asm/asm-offsets.h>
54 #include "kvm-s390.h"
60 #include "trace-s390.h"
212 static u8 halt_poll_max_steal = 10;
228 * the feature is opt-in anyway
243 * defines in FACILITIES_KVM and the non-hypervisor managed bits.
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H A Dinterrupt.c1 // SPDX-License-Identifier: GPL-2.0
10 #define pr_fmt(fmt) "kvm-s390: " fmt
23 #include <asm/access-regs.h>
24 #include <asm/asm-offsets.h>
33 #include "kvm-s390.h"
35 #include "trace-s390.h"
47 struct esca_block *sca = vcpu->kvm->arch.sca; in sca_ext_call_pending()
48 union esca_sigp_ctrl sigp_ctrl = sca->cpu[vcpu->vcpu_id].sigp_ctrl; in sca_ext_call_pending()
63 struct esca_block *sca = vcpu->kvm->arch.sca; in sca_inject_ext_call()
64 union esca_sigp_ctrl *sigp_ctrl = &sca->cpu[vcpu->vcpu_id].sigp_ctrl; in sca_inject_ext_call()
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/linux/drivers/hid/
H A DKconfig1 # SPDX-License-Identifier: GPL-2.0-only
22 most commonly used to refer to the USB-HID specification, but other
27 removed from the HID bus by the transport-layer drivers, such as
58 to work on raw hid events when they want to, and avoid using transport-specific
64 tristate "User-space I/O driver support for HID subsystem"
67 Say Y here if you want to provide HID I/O Drivers from user-space.
68 This allows to write I/O drivers in user-space and feed the data from
71 user-space device.
73 This driver cannot be used to parse HID-reports in user-space and write
74 special HID-drivers. You should use hidraw for that.
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/linux/drivers/net/ethernet/intel/e1000/
H A De1000_hw.h1 /* SPDX-License-Identifier: GPL-2.0 */
2 /* Copyright(c) 1999 - 2006 Intel Corporation. */
122 e1000_igp_cable_length_10 = 10,
258 #define E1000_ERR_MASTER_REQUESTS_PENDING 10
297 #define E1000_MNG_DHCP_COMMAND_TIMEOUT 10 /* Time in ms to process MNG command */
422 /* MAC decode size is 128K - This is the size of BAR0 */
432 #define SPEED_10 10
443 (MINIMUM_ETHERNET_FRAME_SIZE - ETHERNET_FCS_SIZE)
486 * E1000_RAR_ENTRIES - 1 multicast addresses.
503 /* Receive Descriptor - Extended */
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/linux/fs/nfs/
H A Dnfs4xdr.c4 * Client-side XDR for NFSv4.
313 #define IMPL_NAME_LIMIT (sizeof(utsname()->sysname) + sizeof(utsname()->release) + \
314 sizeof(utsname()->version) + sizeof(utsname()->machine) + 8)
424 #define encode_layoutget_maxsz (op_encode_hdr_maxsz + 10 + \
1014 while (len > 0 && bitmap[len-1] == 0) in xdr_encode_bitmap4()
1015 len--; in xdr_encode_bitmap4()
1028 while (len > 0 && (bitmap[len-1] == 0 || mask[len-1] == 0)) in mask_bitmap4()
1029 len--; in mask_bitmap4()
1030 for (i = len; i-- > 0;) { in mask_bitmap4()
1041 encode_uint32(xdr, seqid->sequence->counter); in encode_nfs4_seqid()
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