1*4c03653fSShubhi Garg# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) 2*4c03653fSShubhi Garg%YAML 1.2 3*4c03653fSShubhi Garg--- 4*4c03653fSShubhi Garg$id: http://devicetree.org/schemas/rtc/nvidia,vrs-10.yaml# 5*4c03653fSShubhi Garg$schema: http://devicetree.org/meta-schemas/core.yaml# 6*4c03653fSShubhi Garg 7*4c03653fSShubhi Gargtitle: NVIDIA Voltage Regulator Specification Real Time Clock 8*4c03653fSShubhi Garg 9*4c03653fSShubhi Gargmaintainers: 10*4c03653fSShubhi Garg - Shubhi Garg <shgarg@nvidia.com> 11*4c03653fSShubhi Garg 12*4c03653fSShubhi Gargdescription: 13*4c03653fSShubhi Garg NVIDIA VRS-10 (Voltage Regulator Specification) is a Power Management IC 14*4c03653fSShubhi Garg (PMIC) that implements a power sequencing solution with I2C interface. 15*4c03653fSShubhi Garg The device includes a real-time clock (RTC) with 32kHz clock output and 16*4c03653fSShubhi Garg backup battery support, alarm functionality for system wake-up from 17*4c03653fSShubhi Garg suspend and shutdown states, OTP memory for power sequencing configuration, 18*4c03653fSShubhi Garg and an interrupt controller for managing VRS events. 19*4c03653fSShubhi Garg 20*4c03653fSShubhi Gargproperties: 21*4c03653fSShubhi Garg compatible: 22*4c03653fSShubhi Garg const: nvidia,vrs-10 23*4c03653fSShubhi Garg 24*4c03653fSShubhi Garg reg: 25*4c03653fSShubhi Garg maxItems: 1 26*4c03653fSShubhi Garg 27*4c03653fSShubhi Garg interrupts: 28*4c03653fSShubhi Garg maxItems: 1 29*4c03653fSShubhi Garg 30*4c03653fSShubhi Garg interrupt-controller: true 31*4c03653fSShubhi Garg 32*4c03653fSShubhi Garg '#interrupt-cells': 33*4c03653fSShubhi Garg const: 2 34*4c03653fSShubhi Garg 35*4c03653fSShubhi Gargrequired: 36*4c03653fSShubhi Garg - compatible 37*4c03653fSShubhi Garg - reg 38*4c03653fSShubhi Garg - interrupts 39*4c03653fSShubhi Garg - interrupt-controller 40*4c03653fSShubhi Garg - '#interrupt-cells' 41*4c03653fSShubhi Garg 42*4c03653fSShubhi GargadditionalProperties: false 43*4c03653fSShubhi Garg 44*4c03653fSShubhi Gargexamples: 45*4c03653fSShubhi Garg - | 46*4c03653fSShubhi Garg #include <dt-bindings/interrupt-controller/irq.h> 47*4c03653fSShubhi Garg i2c { 48*4c03653fSShubhi Garg #address-cells = <1>; 49*4c03653fSShubhi Garg #size-cells = <0>; 50*4c03653fSShubhi Garg 51*4c03653fSShubhi Garg pmic@3c { 52*4c03653fSShubhi Garg compatible = "nvidia,vrs-10"; 53*4c03653fSShubhi Garg reg = <0x3c>; 54*4c03653fSShubhi Garg interrupt-parent = <&pmc>; 55*4c03653fSShubhi Garg interrupts = <24 IRQ_TYPE_LEVEL_LOW>; 56*4c03653fSShubhi Garg interrupt-controller; 57*4c03653fSShubhi Garg #interrupt-cells = <2>; 58*4c03653fSShubhi Garg }; 59*4c03653fSShubhi Garg }; 60