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/freebsd/sys/contrib/device-tree/Bindings/regulator/
H A Dlm363x-regulator.txt11 - enable-gpios: Two GPIO specifiers for Vpos and Vneg control pins.
12 The first entry is Vpos, the second is Vneg enable pin.
20 - vneg
25 - vneg
66 vneg {
82 /* GPIO1_16 for Vpos, GPIO1_28 is for Vneg */
99 vneg {
/freebsd/sys/contrib/device-tree/Bindings/mfd/
H A Dti-lmu.txt98 vneg {
141 vneg {
250 vneg {
H A Dmediatek,mt6370.yaml270 regulator-name = "mt6370-dsv-vneg";
/freebsd/contrib/llvm-project/compiler-rt/lib/builtins/arm/
H A Dnegdf2vfp.S21 vneg.f64 d0, d0
H A Dnegsf2vfp.S21 vneg.f32 s0, s0
/freebsd/sys/contrib/device-tree/Bindings/leds/
H A Dleds-lm36274.txt63 vneg {
/freebsd/sys/contrib/device-tree/Bindings/iio/dac/
H A Dadi,ltc2672.yaml142 v-neg-supply = <&vneg>;
H A Dadi,ltc2664.yaml163 v-neg-supply = <&vneg>;
/freebsd/contrib/llvm-project/llvm/lib/Target/ARM/
H A DARMScheduleM4.td130 def : M4UnitL1I<(instregex "VMOVS", "FCONSTS", "VCMP", "VNEG", "VABS")>;
H A DARMScheduleSwift.td558 (instregex "VADDv", "VSUBv", "VNEG(s|f|v)", "VADDL", "VSUBL",
603 def : InstRW<[SwiftWriteP0TwoCycle], (instregex "VABS(S|D)$", "VNEG(S|D)$")>;
H A DARMScheduleA57.td790 def : InstRW<[A57Write_3cyc_1V], (instregex "VNEG")>;
993 "VNEG(s8d|s16d|s32d|s8q|s16q|s32q|d|q)",
1187 def : InstRW<[A57Write_3cyc_1V], (instregex "VNEG(fd|f32q|hd|hq)")>;
H A DARMInstrVFP.td1026 IIC_fpUNA64, "vneg", ".f64\t$Dd, $Dm", "",
1031 IIC_fpUNA32, "vneg", ".f32\t$Sd, $Sm",
1040 IIC_fpUNA16, "vneg", ".f16\t$Sd, $Sm",
2722 def : VFP2MnemonicAlias<"fnegs", "vneg.f32">;
2723 def : VFP2MnemonicAlias<"fnegd", "vneg.f64">;
H A DARMScheduleM55.td464 def : InstRW<[M55WriteFloatE3], (instregex "VNEG(H|S|D)")>;
H A DARMInstrNEON.td6145 // VNEG : Vector Negate (integer)
6146 def VNEGs8d : VNEGD<0b00, "vneg", "s8", v8i8>;
6147 def VNEGs16d : VNEGD<0b01, "vneg", "s16", v4i16>;
6148 def VNEGs32d : VNEGD<0b10, "vneg", "s32", v2i32>;
6149 def VNEGs8q : VNEGQ<0b00, "vneg", "s8", v16i8>;
6150 def VNEGs16q : VNEGQ<0b01, "vneg", "s16", v8i16>;
6151 def VNEGs32q : VNEGQ<0b10, "vneg", "s32", v4i32>;
6153 // VNEG : Vector Negate (floating-point)
6156 "vneg", "f32", "$Vd, $Vm", "",
6160 "vneg", "f32", "$Vd, $Vm", "",
[all …]
H A DARMScheduleR52.td816 def : InstRW<[R52WriteFPALU_F5, R52Read_F1], (instregex "VNEG")>;
H A DARMLowOverheadLoops.cpp846 // FIXME: VNEG FP and -0? I think we'll need to handle this once we allow in canGenerateNonZeros()
H A DARMInstrMVE.td2540 "vneg", 1, 0, vnegq, int_arm_mve_neg_predicated, VTI>;
4131 defm MVE_VNEGf16 : MVE_VABSNEG_fp_m<"vneg", fneg, int_arm_mve_neg_predicated,
4133 defm MVE_VNEGf32 : MVE_VABSNEG_fp_m<"vneg", fneg, int_arm_mve_neg_predicated,
H A DARMScheduleA9.td2429 // VADDL/VSUBL/VNEG are mapped later under IIC_SHLi.
H A DARMISelLowering.cpp6306 /// will be implemented with the NEON VNEG instruction. However, VNEG does
/freebsd/contrib/llvm-project/clang/include/clang/Basic/
H A Darm_fp16.td20 def VNEGSH : SInst<"vneg", "11", "Sh">;
H A Darm_neon.td645 def VNEG : SOpInst<"vneg", "..", "csifQcQsQiQf", OP_NEG>;
804 def NEG : SOpInst<"vneg", "..", "dlQdQl", OP_NEG>;
1525 def SCALAR_NEG : SInst<"vneg", "11", "Sl">;
1693 def VNEGH : SOpInst<"vneg", "..", "hQh", OP_NEG>;
/freebsd/contrib/llvm-project/llvm/lib/Target/RISCV/
H A DRISCVInstrInfoV.td1099 def : InstAlias<"vneg.v $vd, $vs$vm", (VRSUB_VX VR:$vd, VR:$vs, X0, VMaskOp:$vm)>;
1100 def : InstAlias<"vneg.v $vd, $vs", (VRSUB_VX VR:$vd, VR:$vs, X0, zero_reg)>;
/freebsd/contrib/llvm-project/llvm/lib/Target/ARM/AsmParser/
H A DARMAsmParser.cpp13081 "vmvn", "vneg", "vorn", "vorr", "vpnot", in isMnemonicVPTPredicable()