Home
last modified time | relevance | path

Searched +full:vf610 +full:- +full:pit (Results 1 – 4 of 4) sorted by relevance

/linux/Documentation/devicetree/bindings/timer/
H A Dfsl,vf610-pit.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/timer/fsl,vf610-pit.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Freescale Periodic Interrupt Timer (PIT)
10 - Frank Li <Frank.Li@nxp.com>
13 The PIT module is an array of timers that can be used to raise interrupts
19 - enum:
20 - fsl,vf610-pit
21 - nxp,s32g2-pit
[all …]
/linux/drivers/clocksource/
H A Dtimer-nxp-pit.c1 // SPDX-License-Identifier: GPL-2.0-or-later
3 * Copyright 2012-2013 Freescale Semiconductor, Inc.
4 * Copyright 2018,2021-2025 NXP
16 * Each pit takes 0x10 Bytes register space
98 static inline void pit_timer_irqack(struct pit_timer *pit) in pit_timer_irqack() argument
100 writel(PITTFLG_TIF, PITTFLG(pit->clkevt_base)); in pit_timer_irqack()
110 struct pit_timer *pit = cs_to_pit(cs); in pit_timer_clocksource_read() local
112 return (u64)~readl(PITCVAL(pit->clksrc_base)); in pit_timer_clocksource_read()
115 static int pit_clocksource_init(struct pit_timer *pit, const char *name, in pit_clocksource_init() argument
119 * The channels 0 and 1 can be chained to build a 64-bit in pit_clocksource_init()
[all …]
/linux/arch/arm/mach-imx/
H A DKconfig1 # SPDX-License-Identifier: GPL-2.0-only
14 Support for Freescale MXC/iMX-based family of processors
88 comment "Cortex-A platforms"
185 comment "Cortex-A/Cortex-M asymmetric multiprocessing platforms"
224 bool "Vybrid Family VF610 support"
228 This enables support for Freescale Vybrid VF610 processor.
244 bool "Use PIT timer"
247 Use SoC Periodic Interrupt Timer (PIT) as clocksource
/linux/drivers/clk/imx/
H A Dclk-vf610.c1 // SPDX-License-Identifier: GPL-2.0-or-later
3 * Copyright 2012-2013 Freescale Semiconductor, Inc.
10 #include <dt-bindings/clock/vf610-clock.h>
199 np = of_find_compatible_node(NULL, NULL, "fsl,vf610-anatop"); in vf610_clocks_init()
313 clk[VF610_CLK_PIT] = imx_clk_gate2("pit", "ipg_bus", CCM_CCGR1, CCM_CCGRx_CGn(7)); in vf610_clocks_init()
440 clk[VF610_CLK_SNVS] = imx_clk_gate2("snvs-rtc", "ipg_bus", CCM_CCGR6, CCM_CCGRx_CGn(7)); in vf610_clocks_init()
472 CLK_OF_DECLARE(vf610, "fsl,vf610-ccm", vf610_clocks_init);