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/linux/Documentation/devicetree/bindings/fpga/
H A Dxlnx,versal-fpga.yaml4 $id: http://devicetree.org/schemas/fpga/xlnx,versal-fpga.yaml#
7 title: Xilinx Versal FPGA driver.
13 Device Tree Versal FPGA bindings for the Versal SoC, controlled
20 - xlnx,versal-fpga
29 versal_fpga: versal-fpga {
30 compatible = "xlnx,versal-fpga";
/linux/Documentation/devicetree/bindings/clock/
H A Dxlnx,versal-clk.yaml4 $id: http://devicetree.org/schemas/clock/xlnx,versal-clk.yaml#
7 title: Xilinx Versal clock controller
13 The clock controller is a hardware block of Xilinx versal clock tree. It
21 - xlnx,versal-clk
25 - xlnx,versal-net-clk
26 - const: xlnx,versal-clk
55 - xlnx,versal-clk
74 - xlnx,versal-net-clk
131 compatible = "xlnx,versal-clk";
/linux/Documentation/devicetree/bindings/pci/
H A Dxilinx-versal-cpm.yaml4 $id: http://devicetree.org/schemas/pci/xilinx-versal-cpm.yaml#
7 title: CPM Host Controller device tree for Xilinx Versal SoCs
18 - xlnx,versal-cpm-host-1.00
19 - xlnx,versal-cpm5-host
20 - xlnx,versal-cpm5-host1
21 - xlnx,versal-cpm5nc-host
79 versal {
83 compatible = "xlnx,versal-cpm-host-1.00";
110 compatible = "xlnx,versal-cpm5-host";
/linux/Documentation/devicetree/bindings/reset/
H A Dxlnx,zynqmp-reset.yaml7 title: Zynq UltraScale+ MPSoC and Versal reset
13 The Zynq UltraScale+ MPSoC and Versal has several different resets.
27 For list of all valid reset indices for Versal
28 <dt-bindings/reset/xlnx-versal-resets.h>
34 - xlnx,versal-reset
35 - xlnx,versal-net-reset
/linux/arch/arm64/boot/dts/xilinx/
H A Dversal-net-vn-x-b2197-01-revA.dts3 * dts file for Xilinx Versal Net VNX board revA
13 #include "versal-net.dtsi"
14 #include "versal-net-clk.dtsi"
18 compatible = "xlnx,versal-net-vnx-revA", "xlnx,versal-net-vnx", "xlnx,versal-net";
19 model = "Xilinx Versal NET VNX revA";
H A Dversal-net-clk.dtsi3 * dts file for Xilinx Versal NET fixed clock
73 versal_net_firmware: versal-net-firmware {
74 compatible = "xlnx,versal-net-firmware", "xlnx,versal-firmware";
/linux/Documentation/devicetree/bindings/memory-controllers/
H A Dxlnx,versal-net-ddrmc5.yaml4 $id: http://devicetree.org/schemas/memory-controllers/xlnx,versal-net-ddrmc5.yaml#
7 title: Xilinx Versal NET Memory Controller
14 compact and extended memory interfaces. Versal NET DDR memory controller
21 const: xlnx,versal-net-ddrmc5
39 compatible = "xlnx,versal-net-ddrmc5";
H A Dxlnx,versal-ddrmc-edac.yaml4 $id: http://devicetree.org/schemas/memory-controllers/xlnx,versal-ddrmc-edac.yaml#
7 title: Xilinx Versal DDRMC (Integrated DDR Memory Controller)
15 4X memory interfaces. Versal DDR memory controller has an optional ECC support
20 const: xlnx,versal-ddrmc
51 compatible = "xlnx,versal-ddrmc";
/linux/Documentation/devicetree/bindings/mmc/
H A Darasan,sdhci.yaml29 - xlnx,versal-8.9a
30 - xlnx,versal-net-emmc
74 - const: xlnx,versal-8.9a # Versal SDHCI 8.9a PHY
79 - const: xlnx,versal-net-emmc # Versal Net eMMC PHY
258 compatible = "xlnx,versal-8.9a", "arasan,sdhci-8.9a";
/linux/Documentation/devicetree/bindings/remoteproc/
H A Dxlnx,zynqmp-r5fss.yaml23 - xlnx,versal-r5fss
24 - xlnx,versal-net-r52fss
81 - xlnx,versal-r5f
82 - xlnx,versal-net-r52f
156 - xlnx,versal-net-r52fss
194 - xlnx,versal-r5fss
/linux/Documentation/devicetree/bindings/bus/
H A Dxlnx,versal-net-cdx.yaml4 $id: http://devicetree.org/schemas/bus/xlnx,versal-net-cdx.yaml#
39 const: xlnx,versal-net-cdx
73 compatible = "xlnx,versal-net-cdx";
/linux/Documentation/devicetree/bindings/pinctrl/
H A Dxlnx,versal-pinctrl.yaml4 $id: http://devicetree.org/schemas/pinctrl/xlnx,versal-pinctrl.yaml#
7 title: Xilinx Versal Pinctrl
17 Versal's pin configuration nodes act as a container for an arbitrary number of
28 const: xlnx,versal-pinctrl
252 compatible = "xlnx,versal-pinctrl";
/linux/Documentation/devicetree/bindings/rtc/
H A Dxlnx,zynqmp-rtc.yaml25 - xlnx,versal-rtc
26 - xlnx,versal-net-rtc
/linux/Documentation/devicetree/bindings/gpio/
H A Dgpio-zynq.yaml17 - xlnx,versal-gpio-1.0
74 - xlnx,versal-gpio-1.0
/linux/drivers/reset/
H A Dreset-zynqmp.c127 { .compatible = "xlnx,versal-reset", .data = &versal_reset_data, },
128 { .compatible = "xlnx,versal-net-reset", .data = &versal_net_reset_data, },
/linux/drivers/pci/controller/
H A Dpcie-xilinx-cpm.c3 * PCIe host controller driver for Xilinx Versal CPM DMA Bridge
659 .compatible = "xlnx,versal-cpm-host-1.00",
663 .compatible = "xlnx,versal-cpm5-host",
667 .compatible = "xlnx,versal-cpm5-host1",
671 .compatible = "xlnx,versal-cpm5nc-host",
/linux/Documentation/devicetree/bindings/usb/
H A Ddwc3-xilinx.yaml17 - xlnx,versal-dwc3
106 - xlnx,versal-dwc3
/linux/drivers/cdx/controller/
H A Dcdx_controller.c3 * CDX host controller driver for AMD versal-net platform.
238 {.compatible = "xlnx,versal-net-cdx",},
H A Dmc_cdx_pcol.h315 * addresses (prior to any potential IOMMU translation). For versal-net, these
629 * interrupt vector. Versal-net implementation specific limitations are that
674 * MSI data to be used by the hardware. On versal-net, only the lower 16-bits
703 * enum: MCDI command directed to versal-net. MCDI responses of this type
H A Dmcdi_functions.h80 * @msi_data: MSI data to be used by the hardware. On versal-net, only the
/linux/drivers/watchdog/
H A Dxilinx_wwdt.c3 * Window watchdog device driver for Xilinx Versal WWDT
236 { .compatible = "xlnx,versal-wwdt", },
/linux/Documentation/devicetree/bindings/ufs/
H A Damd,versal2-ufs.yaml7 title: AMD Versal Gen 2 UFS Host Controller
/linux/Documentation/devicetree/bindings/spi/
H A Dspi-zynqmp-qspi.yaml15 - xlnx,versal-qspi-1.0
H A Dspi-cadence.yaml23 - xlnx,versal-net-spi-r1p6
/linux/drivers/edac/
H A Dversalnet_edac.c3 * AMD Versal NET memory controller driver
818 sprintf(name, "versal-net-ddrmc5-edac-%d", i); in init_versalnet()
944 { .compatible = "xlnx,versal-net-ddrmc5", },
951 .name = "versal-net-edac",
961 MODULE_DESCRIPTION("Versal NET EDAC driver");

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