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/freebsd/sys/contrib/device-tree/Bindings/clock/
H A Darm,syscon-icst.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/clock/arm,syscon-icst.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Linus Walleij <linusw@kernel.org>
19 an ICST clock request after a write to the 32 bit register at an offset
22 writing a special token to another offset in the system controller.
25 connects the low 8 bits of the VDW (missing one bit), hard-wires RDW to
26 different values and sometimes also hard-wires the output divider. They
38 integratorap-cm
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H A Dst,stm32-rcc.txt6 Please refer to clock-bindings.txt for common clock controller binding usage.
10 - compatible: Should be:
11 "st,stm32f42xx-rcc"
12 "st,stm32f469-rcc"
13 "st,stm32f746-rcc"
14 "st,stm32f769-rcc"
16 - reg: should be register base and length as documented in the
18 - #reset-cells: 1, see below
19 - #clock-cells: 2, device nodes should specify the clock in their "clocks"
23 - clocks: External oscillator clock phandle
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/freebsd/sys/dev/qcom_clk/
H A Dqcom_clk_fepll.c1 /*-
50 * This is the top-level PLL clock on the IPQ4018/IPQ4019.
62 uint32_t offset; member
73 uint64_t vco, parent_rate; in qcom_clk_fepll_recalc() local
79 device_printf(clknode_get_device(sc->clknode), in qcom_clk_fepll_recalc()
87 CLKDEV_DEVICE_LOCK(clknode_get_device(sc->clknode)); in qcom_clk_fepll_recalc()
88 CLKDEV_READ_4(clknode_get_device(sc->clknode), sc->offset, &reg); in qcom_clk_fepll_recalc()
89 CLKDEV_DEVICE_UNLOCK(clknode_get_device(sc->clknode)); in qcom_clk_fepll_recalc()
91 fdbkdiv = (reg >> sc->fdbkdiv_shift) & in qcom_clk_fepll_recalc()
92 ((1U << sc->fdbkdiv_width) - 1); in qcom_clk_fepll_recalc()
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/freebsd/sys/contrib/device-tree/src/arm/arm/
H A Darm-realview-eb.dtsi23 #include <dt-bindings/interrupt-controller/irq.h>
24 #include <dt-bindings/gpio/gpio.h>
27 #address-cells = <1>;
28 #size-cells = <1>;
29 compatible = "arm,realview-eb";
48 vmmc: regulator-vmmc {
49 compatible = "regulator-fixed";
50 regulator-name = "vmmc";
51 regulator-min-microvolt = <3300000>;
52 regulator-max-microvolt = <3300000>;
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H A Darm-realview-pb11mp.dts23 /dts-v1/;
24 #include <dt-bindings/interrupt-controller/irq.h>
25 #include <dt-bindings/gpio/gpio.h>
28 #address-cells = <1>;
29 #size-cells = <1>;
31 compatible = "arm,realview-pb11mp";
52 #address-cells = <1>;
53 #size-cells = <0>;
54 enable-method = "arm,realview-smp";
60 next-level-cache = <&L2>;
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H A Dintegratorap.dts1 // SPDX-License-Identifier: GPL-2.0
6 /dts-v1/;
8 #include <dt-bindings/gpio/gpio.h>
9 #include <dt-bindings/input/input.h>
13 compatible = "arm,integrator-ap";
16 #address-cells = <1>;
17 #size-cells = <0>;
27 /* compatible = "arm,arm926ej-s"; */
30 * The documentation in ARM DUI 0138E page 3-12 states
32 * but painful trial-and-error has proved to me that it
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H A Darm-realview-pbx.dtsi23 #include <dt-bindings/interrupt-controller/irq.h>
24 #include <dt-bindings/gpio/gpio.h>
27 #address-cells = <1>;
28 #size-cells = <1>;
29 compatible = "arm,realview-pbx";
49 vmmc: regulator-vmmc {
50 compatible = "regulator-fixed";
51 regulator-name = "vmmc";
52 regulator-min-microvolt = <3300000>;
53 regulator-max-microvolt = <3300000>;
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H A Darm-realview-pb1176.dts23 /dts-v1/;
24 #include <dt-bindings/interrupt-controller/irq.h>
25 #include <dt-bindings/gpio/gpio.h>
28 #address-cells = <1>;
29 #size-cells = <1>;
31 compatible = "arm,realview-pb1176";
50 vmmc: regulator-vmmc {
51 compatible = "regulator-fixed";
52 regulator-name = "vmmc";
53 regulator-min-microvolt = <3300000>;
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H A Dintegratorcp.dts1 // SPDX-License-Identifier: GPL-2.0
6 /dts-v1/;
11 compatible = "arm,integrator-cp";
18 #address-cells = <1>;
19 #size-cells = <0>;
35 operating-points = <50000 0
38 clock-names = "cpu";
39 clock-latency = <1000000>; /* 1 ms */
45 * ARM DUI 0184B page 7-28 "Integrator/CP922T system clocks" which
50 xtal_codec: clock-24576000 {
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H A Dintegratorap-im-pd1.dts1 // SPDX-License-Identifier: GPL-2.0
4 * with the IM-PD1 example logical module mounted.
10 model = "ARM Integrator/AP with IM-PD1";
11 compatible = "arm,integrator-ap";
13 reserved-memory {
14 #address-cells = <1>;
15 #size-cells = <1>;
19 /* 1 MB of designated video RAM on the IM-PD1 */
20 compatible = "shared-dma-pool";
22 no-map;
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/freebsd/sys/arm64/nvidia/tegra210/
H A Dtegra210_clk_pll.c1 /*-
2 * SPDX-License-Identifier: BSD-2-Clause
42 #include <dt-bindings/clock/tegra210-car.h>
72 #define PLL_FLAG_VCO_OUT 0x02 /* Output VCO directly */
113 /* Post divider <-> register value mapping. */
159 .offset = o, \
172 .offset = o, \
187 .offset = o, \
201 .offset = o, \
215 .offset = o, \
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/freebsd/sys/dev/e1000/
H A De1000_82540.c2 SPDX-License-Identifier: BSD-3-Clause
4 Copyright (c) 2001-2020, Intel Corporation
63 * e1000_init_phy_params_82540 - Init PHY func ptrs.
68 struct e1000_phy_info *phy = &hw->phy; in e1000_init_phy_params_82540()
71 phy->addr = 1; in e1000_init_phy_params_82540()
72 phy->autoneg_mask = AUTONEG_ADVERTISE_SPEED_DEFAULT; in e1000_init_phy_params_82540()
73 phy->reset_delay_us = 10000; in e1000_init_phy_params_82540()
74 phy->type = e1000_phy_m88; in e1000_init_phy_params_82540()
77 phy->ops.check_polarity = e1000_check_polarity_m88; in e1000_init_phy_params_82540()
78 phy->ops.commit = e1000_phy_sw_reset_generic; in e1000_init_phy_params_82540()
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/freebsd/sys/dev/usb/wlan/
H A Dif_zyd.c4 /*-
6 * Copyright (c) 2006 by Florian Stoehr <ich@florian-stoehr.de>
105 usbd_do_request_flags((sc)->sc_udev, &(sc)->sc_mtx, req, data, 0, NULL, 5000)
318 if (uaa->usb_mode != USB_MODE_HOST) in zyd_match()
320 if (uaa->info.bConfigIndex != ZYD_CONFIG_INDEX) in zyd_match()
322 if (uaa->info.bIfaceIndex != ZYD_IFACE_INDEX) in zyd_match()
333 struct ieee80211com *ic = &sc->sc_ic; in zyd_attach()
337 if (uaa->info.bcdDevice < 0x4330) { in zyd_attach()
340 uaa->info.bcdDevice); in zyd_attach()
345 sc->sc_dev = dev; in zyd_attach()
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H A Dif_run.c1 /*-
5 * Copyright (c) 2013-2014 Kevin Lo
20 /*-
114 device_printf((_sc)->sc_dev, __VA_ARGS__); \
530 /* MCS - single stream */
540 /* MCS - 2 streams */
550 /* MCS - 3 streams */
731 if (uaa->dev_state != UAA_DEV_READY) in run_autoinst()
737 id = iface->idesc; in run_autoinst()
738 if (id == NULL || id->bInterfaceClass != UICLASS_MASS) in run_autoinst()
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H A Dif_mtw.c1 /*-
2 * Copyright (c) 2008-2010 Damien Bergamini <damien.bergamini@free.fr>
3 * Copyright (c) 2013-2014 Kevin Lo
108 device_printf((_sc)->sc_dev, __VA_ARGS__); \
384 if (uaa->dev_state != UAA_DEV_READY) in mtw_autoinst()
390 id = iface->idesc; in mtw_autoinst()
391 if (id == NULL || id->bInterfaceClass != UICLASS_MASS) in mtw_autoinst()
397 uaa->dev_state = UAA_DEV_EJECTING; in mtw_autoinst()
438 if (sc->asic_ver == 0x7612) in mtw_wlan_enable()
447 if (sc->asic_ver == 0x7612) { in mtw_wlan_enable()
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/freebsd/sys/dev/ral/
H A Drt2860.c1 /*-
2 * Copyright (c) 2007-2010 Damien Bergamini <damien.bergamini@free.fr>
21 /*-
70 #define DPRINTF(x) do { if (sc->sc_debug > 0) printf x; } while (0)
71 #define DPRINTFN(n, x) do { if (sc->sc_debug >= (n)) printf x; } while (0)
238 struct ieee80211com *ic = &sc->sc_ic; in rt2860_attach()
242 sc->sc_dev = dev; in rt2860_attach()
243 sc->sc_debug = 0; in rt2860_attach()
245 mtx_init(&sc->sc_mtx, device_get_nameunit(dev), MTX_NETWORK_LOCK, in rt2860_attach()
248 callout_init_mtx(&sc->watchdog_ch, &sc->sc_mtx, 0); in rt2860_attach()
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/freebsd/sys/gnu/dev/bwn/phy_n/
H A Dif_bwn_phy_n_core.c23 Boston, MA 02110-1301, USA.
165 return ((mac->mac_phy.phy_n->ipa2g_on && band == BWN_BAND_2G) || in bwn_nphy_ipa()
166 (mac->mac_phy.phy_n->ipa5g_on && band == BWN_BAND_5G)); in bwn_nphy_ipa()
169 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/RxCoreGetState */
180 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/ForceRFSeq */
196 BWN_WARNPRINTF(mac->mac_sc, "%s: seq %d > max", __func__, seq); in bwn_nphy_force_rf_sequence()
207 BWN_ERRPRINTF(mac->mac_sc, "RF sequence status timeout\n"); in bwn_nphy_force_rf_sequence()
219 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/RFCtrlOverrideRev7 */
224 struct bwn_phy *phy = &mac->mac_phy; in bwn_nphy_rf_ctl_override_rev7()
234 if (phy->rev >= 19 || phy->rev < 3) { in bwn_nphy_rf_ctl_override_rev7()
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/freebsd/sys/dev/qlnx/qlnxe/
H A Dreg_addr.h2 * Copyright (c) 2017-2018 Cavium, Inc.
78 …- For ending "endless completion". 0 - When receiving a completion timeout while receiving a compl…
79 … DataWidth:0x4 // 0 - TXCPL sync fifo pop underflow 1 - TXR sync fifo pop underflow 2 - TXW hea…
80 …s:R DataWidth:0x6 // 0 - RX target read and config sync fifo push overflow 1 - RX header syn…
81 …ataWidth:0x14 // 4:0 - TXCPL sync fifo pop status 9:5 - TXR sync fifo pop status 14:10 - TXW hea…
88 …ffff<<0) // Vendor ID. PCI-SIG assigned Manufacturer Identifier. Note: The access attributes of …
90 …ce Identifier. Note: The access attributes of this field are as follows: - Dbi: if (DBI_RO_WR_E…
116 … (0x1<<9) // Fast back-to-back transaction ena…
128 … (0x1<<23) // Fast back-to-back capable. Not ap…
145 …l has_io_bar=0. Note: The access attributes of this field are as follows: - Dbi: if (DBI_RO_WR_E…
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/freebsd/sys/dev/bwn/
H A Dif_bwn_phy_lp.c1 /*-
2 * Copyright (c) 2009-2010 Weongyo Jeong <weongyo@freebsd.org>
325 { 1, -66, 15 }, { 2, -66, 15 }, { 3, -66, 15 }, { 4, -66, 15 },
326 { 5, -66, 15 }, { 6, -66, 15 }, { 7, -66, 14 }, { 8, -66, 14 },
327 { 9, -66, 14 }, { 10, -66, 14 }, { 11, -66, 14 }, { 12, -66, 13 },
328 { 13, -66, 13 }, { 14, -66, 13 },
333 { 1, -64, 13 }, { 2, -64, 13 }, { 3, -64, 13 }, { 4, -64, 13 },
334 { 5, -64, 12 }, { 6, -64, 12 }, { 7, -64, 12 }, { 8, -64, 12 },
335 { 9, -64, 12 }, { 10, -64, 11 }, { 11, -64, 11 }, { 12, -64, 11 },
336 { 13, -64, 11 }, { 14, -64, 10 }, { 34, -62, 24 }, { 38, -62, 24 },
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