Lines Matching +full:vco +full:- +full:offset
1 /*-
2 * Copyright (c) 2009-2010 Weongyo Jeong <weongyo@freebsd.org>
325 { 1, -66, 15 }, { 2, -66, 15 }, { 3, -66, 15 }, { 4, -66, 15 },
326 { 5, -66, 15 }, { 6, -66, 15 }, { 7, -66, 14 }, { 8, -66, 14 },
327 { 9, -66, 14 }, { 10, -66, 14 }, { 11, -66, 14 }, { 12, -66, 13 },
328 { 13, -66, 13 }, { 14, -66, 13 },
333 { 1, -64, 13 }, { 2, -64, 13 }, { 3, -64, 13 }, { 4, -64, 13 },
334 { 5, -64, 12 }, { 6, -64, 12 }, { 7, -64, 12 }, { 8, -64, 12 },
335 { 9, -64, 12 }, { 10, -64, 11 }, { 11, -64, 11 }, { 12, -64, 11 },
336 { 13, -64, 11 }, { 14, -64, 10 }, { 34, -62, 24 }, { 38, -62, 24 },
337 { 42, -62, 24 }, { 46, -62, 23 }, { 36, -62, 24 }, { 40, -62, 24 },
338 { 44, -62, 23 }, { 48, -62, 23 }, { 52, -62, 23 }, { 56, -62, 22 },
339 { 60, -62, 22 }, { 64, -62, 22 }, { 100, -62, 16 }, { 104, -62, 16 },
340 { 108, -62, 15 }, { 112, -62, 14 }, { 116, -62, 14 }, { 120, -62, 13 },
341 { 124, -62, 12 }, { 128, -62, 12 }, { 132, -62, 12 }, { 136, -62, 11 },
342 { 140, -62, 10 }, { 149, -61, 9 }, { 153, -61, 9 }, { 157, -61, 9 },
343 { 161, -61, 8 }, { 165, -61, 8 }, { 184, -62, 25 }, { 188, -62, 25 },
344 { 192, -62, 25 }, { 196, -62, 25 }, { 200, -62, 25 }, { 204, -62, 25 },
345 { 208, -62, 25 }, { 212, -62, 25 }, { 216, -62, 26 },
348 static const struct bwn_rxcompco bwn_rxcompco_r2 = { 0, -64, 0 };
382 struct bwn_phy *phy = &mac->mac_phy; in bwn_phy_lp_init_pre()
383 struct bwn_phy_lp *plp = &phy->phy_lp; in bwn_phy_lp_init_pre()
385 plp->plp_antenna = BWN_ANT_DEFAULT; in bwn_phy_lp_init_pre()
408 struct bwn_phy_lp *plp = &mac->mac_phy.phy_lp; in bwn_phy_lp_init()
409 struct bwn_softc *sc = mac->mac_sc; in bwn_phy_lp_init()
411 struct ieee80211com *ic = &sc->sc_ic; in bwn_phy_lp_init()
415 /* All LP-PHY devices have a PMU */ in bwn_phy_lp_init()
416 if (sc->sc_pmu == NULL) { in bwn_phy_lp_init()
417 device_printf(sc->sc_dev, "no PMU; cannot configure PAREF " in bwn_phy_lp_init()
433 if (mac->mac_phy.rf_ver == 0x2062) { in bwn_phy_lp_init()
443 tmp = BWN_RF_READ(mac, st->st_rfaddr); in bwn_phy_lp_init()
444 tmp >>= st->st_rfshift; in bwn_phy_lp_init()
445 tmp <<= st->st_physhift; in bwn_phy_lp_init()
447 BWN_PHY_OFDM(0xf2 + st->st_phyoffset), in bwn_phy_lp_init()
448 ~(st->st_mask << st->st_physhift), tmp); in bwn_phy_lp_init()
456 if (mac->mac_phy.rev >= 2) { in bwn_phy_lp_init()
459 } else if (!plp->plp_rccap) { in bwn_phy_lp_init()
460 if (IEEE80211_IS_CHAN_2GHZ(ic->ic_curchan)) { in bwn_phy_lp_init()
469 device_printf(sc->sc_dev, in bwn_phy_lp_init()
507 if (mac->mac_phy.rev < 2 && reg != 0x4001) in bwn_phy_lp_rf_read()
509 if (mac->mac_phy.rev >= 2) in bwn_phy_lp_rf_read()
531 (mac->mac_phy.rev >= 2) ? 0xf7f7 : 0xffe7); in bwn_phy_lp_rf_onoff()
535 if (mac->mac_phy.rev >= 2) { in bwn_phy_lp_rf_onoff()
553 struct bwn_phy *phy = &mac->mac_phy; in bwn_phy_lp_switch_channel()
554 struct bwn_phy_lp *plp = &phy->phy_lp; in bwn_phy_lp_switch_channel()
557 if (phy->rf_ver == 0x2063) { in bwn_phy_lp_switch_channel()
569 plp->plp_chan = chan; in bwn_phy_lp_switch_channel()
577 struct bwn_softc *sc = mac->mac_sc; in bwn_phy_lp_get_default_chan()
578 struct ieee80211com *ic = &sc->sc_ic; in bwn_phy_lp_get_default_chan()
580 return (IEEE80211_IS_CHAN_2GHZ(ic->ic_curchan) ? 1 : 36); in bwn_phy_lp_get_default_chan()
586 struct bwn_phy *phy = &mac->mac_phy; in bwn_phy_lp_set_antenna()
587 struct bwn_phy_lp *plp = &phy->phy_lp; in bwn_phy_lp_set_antenna()
589 if (phy->rev >= 2 || antenna > BWN_ANTAUTO1) in bwn_phy_lp_set_antenna()
596 plp->plp_antenna = antenna; in bwn_phy_lp_set_antenna()
609 struct bwn_phy_lp *plp = &mac->mac_phy.phy_lp; in bwn_phy_lp_readsprom()
610 struct bwn_softc *sc = mac->mac_sc; in bwn_phy_lp_readsprom()
611 struct ieee80211com *ic = &sc->sc_ic; in bwn_phy_lp_readsprom()
625 if (IEEE80211_IS_CHAN_2GHZ(ic->ic_curchan)) { in bwn_phy_lp_readsprom()
626 BWN_PHY_LP_READVAR(sc->sc_dev, uint8, BHND_NVAR_TRI2G, in bwn_phy_lp_readsprom()
627 &plp->plp_txisoband_m); in bwn_phy_lp_readsprom()
628 BWN_PHY_LP_READVAR(sc->sc_dev, uint8, BHND_NVAR_BXA2G, in bwn_phy_lp_readsprom()
629 &plp->plp_bxarch); in bwn_phy_lp_readsprom()
630 BWN_PHY_LP_READVAR(sc->sc_dev, int8, BHND_NVAR_RXPO2G, in bwn_phy_lp_readsprom()
631 &plp->plp_rxpwroffset); in bwn_phy_lp_readsprom()
632 BWN_PHY_LP_READVAR(sc->sc_dev, uint8, BHND_NVAR_RSSISMF2G, in bwn_phy_lp_readsprom()
633 &plp->plp_rssivf); in bwn_phy_lp_readsprom()
634 BWN_PHY_LP_READVAR(sc->sc_dev, uint8, BHND_NVAR_RSSISMC2G, in bwn_phy_lp_readsprom()
635 &plp->plp_rssivc); in bwn_phy_lp_readsprom()
636 BWN_PHY_LP_READVAR(sc->sc_dev, uint8, BHND_NVAR_RSSISAV2G, in bwn_phy_lp_readsprom()
637 &plp->plp_rssigs); in bwn_phy_lp_readsprom()
642 BWN_PHY_LP_READVAR(sc->sc_dev, uint8, BHND_NVAR_TRI5GL, in bwn_phy_lp_readsprom()
643 &plp->plp_txisoband_l); in bwn_phy_lp_readsprom()
644 BWN_PHY_LP_READVAR(sc->sc_dev, uint8, BHND_NVAR_TRI5G, in bwn_phy_lp_readsprom()
645 &plp->plp_txisoband_m); in bwn_phy_lp_readsprom()
646 BWN_PHY_LP_READVAR(sc->sc_dev, uint8, BHND_NVAR_TRI5GH, in bwn_phy_lp_readsprom()
647 &plp->plp_txisoband_h); in bwn_phy_lp_readsprom()
648 BWN_PHY_LP_READVAR(sc->sc_dev, uint8, BHND_NVAR_BXA5G, in bwn_phy_lp_readsprom()
649 &plp->plp_bxarch); in bwn_phy_lp_readsprom()
650 BWN_PHY_LP_READVAR(sc->sc_dev, int8, BHND_NVAR_RXPO5G, in bwn_phy_lp_readsprom()
651 &plp->plp_rxpwroffset); in bwn_phy_lp_readsprom()
652 BWN_PHY_LP_READVAR(sc->sc_dev, uint8, BHND_NVAR_RSSISMF5G, in bwn_phy_lp_readsprom()
653 &plp->plp_rssivf); in bwn_phy_lp_readsprom()
654 BWN_PHY_LP_READVAR(sc->sc_dev, uint8, BHND_NVAR_RSSISMC5G, in bwn_phy_lp_readsprom()
655 &plp->plp_rssivc); in bwn_phy_lp_readsprom()
656 BWN_PHY_LP_READVAR(sc->sc_dev, uint8, BHND_NVAR_RSSISAV5G, in bwn_phy_lp_readsprom()
657 &plp->plp_rssigs); in bwn_phy_lp_readsprom()
669 if (mac->mac_phy.rev >= 2) in bwn_phy_lp_bbinit()
680 struct bwn_softc *sc = mac->mac_sc; in bwn_phy_lp_txpctl_init()
681 struct ieee80211com *ic = &sc->sc_ic; in bwn_phy_lp_txpctl_init()
684 IEEE80211_IS_CHAN_2GHZ(ic->ic_curchan) ? &gain_2ghz : &gain_5ghz); in bwn_phy_lp_txpctl_init()
691 struct bwn_phy_lp *plp = &mac->mac_phy.phy_lp; in bwn_phy_lp_calib()
692 struct bwn_softc *sc = mac->mac_sc; in bwn_phy_lp_calib()
693 struct ieee80211com *ic = &sc->sc_ic; in bwn_phy_lp_calib()
699 if (plp->plp_chanfullcal != plp->plp_chan) { in bwn_phy_lp_calib()
700 plp->plp_chanfullcal = plp->plp_chan; in bwn_phy_lp_calib()
710 if (mac->mac_phy.rev >= 2) in bwn_phy_lp_calib()
713 mode = plp->plp_txpctlmode; in bwn_phy_lp_calib()
715 if (mac->mac_phy.rev == 0 && mode != BWN_PHYLP_TXPCTL_OFF) in bwn_phy_lp_calib()
717 if (mac->mac_phy.rev >= 2 && fc == 1) { in bwn_phy_lp_calib()
719 omode = plp->plp_txpctlmode; in bwn_phy_lp_calib()
733 if (mac->mac_phy.rev >= 2) in bwn_phy_lp_calib()
737 if (sc->sc_cid.chip_id == BHND_CHIPID_BCM5354) { in bwn_phy_lp_calib()
739 if (bwn_rxcompco_5354[i].rc_chan == plp->plp_chan) in bwn_phy_lp_calib()
742 } else if (mac->mac_phy.rev >= 2) in bwn_phy_lp_calib()
746 if (bwn_rxcompco_r12[i].rc_chan == plp->plp_chan) in bwn_phy_lp_calib()
753 BWN_PHY_SETMASK(mac, BWN_PHY_RX_COMP_COEFF_S, 0xff00, rc->rc_c1); in bwn_phy_lp_calib()
754 BWN_PHY_SETMASK(mac, BWN_PHY_RX_COMP_COEFF_S, 0x00ff, rc->rc_c0 << 8); in bwn_phy_lp_calib()
758 if (IEEE80211_IS_CHAN_2GHZ(ic->ic_curchan)) { in bwn_phy_lp_calib()
783 if (mac->mac_phy.rev >= 2) { in bwn_phy_lp_calib()
785 if (IEEE80211_IS_CHAN_2GHZ(ic->ic_curchan)) { in bwn_phy_lp_calib()
816 struct bwn_softc *sc = mac->mac_sc; in bwn_phy_lp_b2063_switch_channel()
832 error = bhnd_get_clock_freq(sc->sc_dev, BHND_CLOCK_ALP, &freqxtal); in bwn_phy_lp_b2063_switch_channel()
834 device_printf(sc->sc_dev, "failed to fetch clock frequency: %d", in bwn_phy_lp_b2063_switch_channel()
839 BWN_RF_WRITE(mac, BWN_B2063_LOGEN_VCOBUF1, bc->bc_data[0]); in bwn_phy_lp_b2063_switch_channel()
840 BWN_RF_WRITE(mac, BWN_B2063_LOGEN_MIXER2, bc->bc_data[1]); in bwn_phy_lp_b2063_switch_channel()
841 BWN_RF_WRITE(mac, BWN_B2063_LOGEN_BUF2, bc->bc_data[2]); in bwn_phy_lp_b2063_switch_channel()
842 BWN_RF_WRITE(mac, BWN_B2063_LOGEN_RCCR1, bc->bc_data[3]); in bwn_phy_lp_b2063_switch_channel()
843 BWN_RF_WRITE(mac, BWN_B2063_A_RX_1ST3, bc->bc_data[4]); in bwn_phy_lp_b2063_switch_channel()
844 BWN_RF_WRITE(mac, BWN_B2063_A_RX_2ND1, bc->bc_data[5]); in bwn_phy_lp_b2063_switch_channel()
845 BWN_RF_WRITE(mac, BWN_B2063_A_RX_2ND4, bc->bc_data[6]); in bwn_phy_lp_b2063_switch_channel()
846 BWN_RF_WRITE(mac, BWN_B2063_A_RX_2ND7, bc->bc_data[7]); in bwn_phy_lp_b2063_switch_channel()
847 BWN_RF_WRITE(mac, BWN_B2063_A_RX_PS6, bc->bc_data[8]); in bwn_phy_lp_b2063_switch_channel()
848 BWN_RF_WRITE(mac, BWN_B2063_TX_RF_CTL2, bc->bc_data[9]); in bwn_phy_lp_b2063_switch_channel()
849 BWN_RF_WRITE(mac, BWN_B2063_TX_RF_CTL5, bc->bc_data[10]); in bwn_phy_lp_b2063_switch_channel()
850 BWN_RF_WRITE(mac, BWN_B2063_PA_CTL11, bc->bc_data[11]); in bwn_phy_lp_b2063_switch_channel()
855 freqvco = bc->bc_freq << ((bc->bc_freq > 4000) ? 1 : 2); in bwn_phy_lp_b2063_switch_channel()
858 timeout = ((((8 * freqxtal) / (div * 5000000)) + 1) >> 1) - 1; in bwn_phy_lp_b2063_switch_channel()
874 (timeoutref + 1)) - 1; in bwn_phy_lp_b2063_switch_channel()
883 tmp[1] -= freqref; in bwn_phy_lp_b2063_switch_channel()
896 tmp[2] = ((41 * (val[2] - 3000)) /1200) + 27; in bwn_phy_lp_b2063_switch_channel()
901 tmp[4] = ((tmp[3] + tmp[2]) / (tmp[2] << 1)) - 8; in bwn_phy_lp_b2063_switch_channel()
904 tmp[4] = ((tmp[3] + (tmp[2] >> 1)) / tmp[2]) - 8; in bwn_phy_lp_b2063_switch_channel()
932 /* VCO Calibration */ in bwn_phy_lp_b2063_switch_channel()
952 struct bwn_softc *sc = mac->mac_sc; in bwn_phy_lp_b2062_switch_channel()
953 struct bwn_phy_lp *plp = &mac->mac_phy.phy_lp; in bwn_phy_lp_b2062_switch_channel()
969 error = bhnd_get_clock_freq(sc->sc_dev, BHND_CLOCK_ALP, &freqxtal); in bwn_phy_lp_b2062_switch_channel()
971 device_printf(sc->sc_dev, "failed to fetch clock frequency: %d", in bwn_phy_lp_b2062_switch_channel()
977 BWN_RF_WRITE(mac, BWN_B2062_N_LGENATUNE0, bc->bc_data[0]); in bwn_phy_lp_b2062_switch_channel()
978 BWN_RF_WRITE(mac, BWN_B2062_N_LGENATUNE2, bc->bc_data[1]); in bwn_phy_lp_b2062_switch_channel()
979 BWN_RF_WRITE(mac, BWN_B2062_N_LGENATUNE3, bc->bc_data[2]); in bwn_phy_lp_b2062_switch_channel()
980 BWN_RF_WRITE(mac, BWN_B2062_N_TX_TUNE, bc->bc_data[3]); in bwn_phy_lp_b2062_switch_channel()
981 BWN_RF_WRITE(mac, BWN_B2062_S_LGENG_CTL1, bc->bc_data[4]); in bwn_phy_lp_b2062_switch_channel()
982 BWN_RF_WRITE(mac, BWN_B2062_N_LGENACTL5, bc->bc_data[5]); in bwn_phy_lp_b2062_switch_channel()
983 BWN_RF_WRITE(mac, BWN_B2062_N_LGENACTL6, bc->bc_data[6]); in bwn_phy_lp_b2062_switch_channel()
984 BWN_RF_WRITE(mac, BWN_B2062_N_TX_PGA, bc->bc_data[7]); in bwn_phy_lp_b2062_switch_channel()
985 BWN_RF_WRITE(mac, BWN_B2062_N_TX_PAD, bc->bc_data[8]); in bwn_phy_lp_b2062_switch_channel()
991 tmp[1] = plp->plp_div * 1000; in bwn_phy_lp_b2062_switch_channel()
1035 struct bwn_phy_lp *plp = &mac->mac_phy.phy_lp; in bwn_phy_lp_set_anafilter()
1038 if (mac->mac_phy.rev < 2) { in bwn_phy_lp_set_anafilter()
1040 if ((mac->mac_phy.rev == 1) && (plp->plp_rccap)) in bwn_phy_lp_set_anafilter()
1051 struct bwn_phy_lp *plp = &mac->mac_phy.phy_lp; in bwn_phy_lp_set_gaintbl()
1052 struct bwn_softc *sc = mac->mac_sc; in bwn_phy_lp_set_gaintbl()
1053 struct ieee80211com *ic = &sc->sc_ic; in bwn_phy_lp_set_gaintbl()
1056 KASSERT(mac->mac_phy.rev < 2, ("%s:%d: fail", __func__, __LINE__)); in bwn_phy_lp_set_gaintbl()
1058 if (IEEE80211_IS_CHAN_2GHZ(ic->ic_curchan)) in bwn_phy_lp_set_gaintbl()
1059 iso = plp->plp_txisoband_m; in bwn_phy_lp_set_gaintbl()
1061 iso = plp->plp_txisoband_l; in bwn_phy_lp_set_gaintbl()
1063 iso = plp->plp_txisoband_m; in bwn_phy_lp_set_gaintbl()
1065 iso = plp->plp_txisoband_h; in bwn_phy_lp_set_gaintbl()
1067 tmp[0] = ((iso - 26) / 12) << 12; in bwn_phy_lp_set_gaintbl()
1078 struct bwn_phy_lp *plp = &mac->mac_phy.phy_lp; in bwn_phy_lp_digflt_save()
1094 plp->plp_digfilt[i] = BWN_PHY_READ(mac, addr[i]); in bwn_phy_lp_digflt_save()
1102 struct bwn_phy_lp *plp = &mac->mac_phy.phy_lp; in bwn_phy_lp_get_txpctlmode()
1103 struct bwn_softc *sc = mac->mac_sc; in bwn_phy_lp_get_txpctlmode()
1109 plp->plp_txpctlmode = BWN_PHYLP_TXPCTL_OFF; in bwn_phy_lp_get_txpctlmode()
1112 plp->plp_txpctlmode = BWN_PHYLP_TXPCTL_ON_SW; in bwn_phy_lp_get_txpctlmode()
1115 plp->plp_txpctlmode = BWN_PHYLP_TXPCTL_ON_HW; in bwn_phy_lp_get_txpctlmode()
1118 plp->plp_txpctlmode = BWN_PHYLP_TXPCTL_UNKNOWN; in bwn_phy_lp_get_txpctlmode()
1119 device_printf(sc->sc_dev, "unknown command mode\n"); in bwn_phy_lp_get_txpctlmode()
1127 struct bwn_phy_lp *plp = &mac->mac_phy.phy_lp; in bwn_phy_lp_set_txpctlmode()
1132 old = plp->plp_txpctlmode; in bwn_phy_lp_set_txpctlmode()
1135 plp->plp_txpctlmode = mode; in bwn_phy_lp_set_txpctlmode()
1139 plp->plp_tssiidx); in bwn_phy_lp_set_txpctlmode()
1141 0x8fff, ((uint16_t)plp->plp_tssinpt << 16)); in bwn_phy_lp_set_txpctlmode()
1144 if (mac->mac_phy.rev < 2) in bwn_phy_lp_set_txpctlmode()
1152 plp->plp_txpwridx = -1; in bwn_phy_lp_set_txpctlmode()
1154 if (mac->mac_phy.rev >= 2) { in bwn_phy_lp_set_txpctlmode()
1162 switch (plp->plp_txpctlmode) { in bwn_phy_lp_set_txpctlmode()
1183 struct bwn_phy_lp *plp = &mac->mac_phy.phy_lp; in bwn_phy_lp_bugfix()
1184 struct bwn_softc *sc = mac->mac_sc; in bwn_phy_lp_bugfix()
1195 device_printf(sc->sc_dev, "failed to allocate buffer.\n"); in bwn_phy_lp_bugfix()
1200 mode = plp->plp_txpctlmode; in bwn_phy_lp_bugfix()
1201 txpwridx = plp->plp_txpwridx; in bwn_phy_lp_bugfix()
1202 tssinpt = plp->plp_tssinpt; in bwn_phy_lp_bugfix()
1203 tssiidx = plp->plp_tssiidx; in bwn_phy_lp_bugfix()
1206 (mac->mac_phy.rev < 2) ? BWN_TAB_4(10, 0x140) : in bwn_phy_lp_bugfix()
1216 (mac->mac_phy.rev < 2) ? BWN_TAB_4(10, 0x140) : in bwn_phy_lp_bugfix()
1219 BWN_WRITE_2(mac, BWN_CHANNEL, plp->plp_chan); in bwn_phy_lp_bugfix()
1220 plp->plp_tssinpt = tssinpt; in bwn_phy_lp_bugfix()
1221 plp->plp_tssiidx = tssiidx; in bwn_phy_lp_bugfix()
1222 bwn_phy_lp_set_anafilter(mac, plp->plp_chan); in bwn_phy_lp_bugfix()
1223 if (txpwridx != -1) { in bwn_phy_lp_bugfix()
1225 plp->plp_txpwridx = txpwridx; in bwn_phy_lp_bugfix()
1227 if (plp->plp_txpctlmode != BWN_PHYLP_TXPCTL_OFF) in bwn_phy_lp_bugfix()
1229 if (mac->mac_phy.rev >= 2) { in bwn_phy_lp_bugfix()
1257 (mac->mac_phy.rev >= 2) ? BWN_TAB_4(7, txpwridx + 448) : in bwn_phy_lp_bugfix()
1260 if (mac->mac_phy.rev >= 2) { in bwn_phy_lp_bugfix()
1268 if (plp->plp_rccap) in bwn_phy_lp_bugfix()
1270 bwn_phy_lp_set_antenna(mac, plp->plp_antenna); in bwn_phy_lp_bugfix()
1278 struct bwn_phy_lp *plp = &mac->mac_phy.phy_lp; in bwn_phy_lp_digflt_restore()
1289 BWN_PHY_WRITE(mac, addr[i], plp->plp_digfilt[i]); in bwn_phy_lp_digflt_restore()
1297 if (mac->mac_phy.rev < 2) { in bwn_phy_lp_tblinit()
1314 uint16_t offset; member
1322 struct bwn_phy_lp *plp = &mac->mac_phy.phy_lp; in bwn_phy_lp_bbinit_r2()
1323 struct bwn_softc *sc = mac->mac_sc; in bwn_phy_lp_bbinit_r2()
1324 struct ieee80211com *ic = &sc->sc_ic; in bwn_phy_lp_bbinit_r2()
1361 BWN_PHY_SETMASK(mac, v2[i].offset, v2[i].mask, v2[i].set); in bwn_phy_lp_bbinit_r2()
1366 if (sc->sc_board_info.board_rev >= 0x18) { in bwn_phy_lp_bbinit_r2()
1383 if (sc->sc_cid.chip_id == BHND_CHIPID_BCM4325 && in bwn_phy_lp_bbinit_r2()
1384 sc->sc_cid.chip_pkg == 0) { in bwn_phy_lp_bbinit_r2()
1392 BWN_PHY_SETMASK(mac, v3[i].offset, v3[i].mask, v3[i].set); in bwn_phy_lp_bbinit_r2()
1393 if (sc->sc_cid.chip_id == BHND_CHIPID_BCM4325 && in bwn_phy_lp_bbinit_r2()
1394 sc->sc_cid.chip_pkg == 0) { in bwn_phy_lp_bbinit_r2()
1399 if (IEEE80211_IS_CHAN_2GHZ(ic->ic_curchan)) { in bwn_phy_lp_bbinit_r2()
1411 BWN_PHY_SETMASK(mac, BWN_PHY_INPUT_PWRDB, 0xff00, plp->plp_rxpwroffset); in bwn_phy_lp_bbinit_r2()
1416 0x2000 | ((uint16_t)plp->plp_rssigs << 10) | in bwn_phy_lp_bbinit_r2()
1417 ((uint16_t)plp->plp_rssivc << 4) | plp->plp_rssivf); in bwn_phy_lp_bbinit_r2()
1419 if (sc->sc_cid.chip_id == BHND_CHIPID_BCM4325 && in bwn_phy_lp_bbinit_r2()
1420 sc->sc_cid.chip_pkg == 0) { in bwn_phy_lp_bbinit_r2()
1432 struct bwn_phy_lp *plp = &mac->mac_phy.phy_lp; in bwn_phy_lp_bbinit_r01()
1433 struct bwn_softc *sc = mac->mac_sc; in bwn_phy_lp_bbinit_r01()
1434 struct ieee80211com *ic = &sc->sc_ic; in bwn_phy_lp_bbinit_r01()
1511 BWN_PHY_SETMASK(mac, v1[i].offset, v1[i].mask, v1[i].set); in bwn_phy_lp_bbinit_r01()
1513 0xff00, plp->plp_rxpwroffset); in bwn_phy_lp_bbinit_r01()
1514 if ((sc->sc_board_info.board_flags & BHND_BFL_FEM) && in bwn_phy_lp_bbinit_r01()
1515 ((IEEE80211_IS_CHAN_5GHZ(ic->ic_curchan)) || in bwn_phy_lp_bbinit_r01()
1516 (sc->sc_board_info.board_flags & BHND_BFL_PAREF))) { in bwn_phy_lp_bbinit_r01()
1517 error = bhnd_pmu_set_voltage_raw(sc->sc_pmu, in bwn_phy_lp_bbinit_r01()
1520 device_printf(sc->sc_dev, "failed to set PAREF LDO " in bwn_phy_lp_bbinit_r01()
1523 error = bhnd_pmu_enable_regulator(sc->sc_pmu, in bwn_phy_lp_bbinit_r01()
1526 device_printf(sc->sc_dev, "failed to enable PAREF LDO " in bwn_phy_lp_bbinit_r01()
1529 if (mac->mac_phy.rev == 0) in bwn_phy_lp_bbinit_r01()
1534 error = bhnd_pmu_disable_regulator(sc->sc_pmu, in bwn_phy_lp_bbinit_r01()
1537 device_printf(sc->sc_dev, "failed to disable PAREF LDO " in bwn_phy_lp_bbinit_r01()
1543 tmp = plp->plp_rssivf | plp->plp_rssivc << 4 | 0xa000; in bwn_phy_lp_bbinit_r01()
1545 if (sc->sc_board_info.board_flags & BHND_BFL_RSSIINV) in bwn_phy_lp_bbinit_r01()
1551 0xfff9, (plp->plp_bxarch << 1)); in bwn_phy_lp_bbinit_r01()
1552 if (mac->mac_phy.rev == 1 && in bwn_phy_lp_bbinit_r01()
1553 (sc->sc_board_info.board_flags & BHND_BFL_FEM_BT)) { in bwn_phy_lp_bbinit_r01()
1555 BWN_PHY_SETMASK(mac, v2[i].offset, v2[i].mask, in bwn_phy_lp_bbinit_r01()
1557 } else if (IEEE80211_IS_CHAN_5GHZ(ic->ic_curchan) || in bwn_phy_lp_bbinit_r01()
1558 (sc->sc_board_info.board_type == 0x048a) || in bwn_phy_lp_bbinit_r01()
1559 ((mac->mac_phy.rev == 0) && in bwn_phy_lp_bbinit_r01()
1560 (sc->sc_board_info.board_flags & BHND_BFL_FEM))) { in bwn_phy_lp_bbinit_r01()
1562 BWN_PHY_SETMASK(mac, v3[i].offset, v3[i].mask, in bwn_phy_lp_bbinit_r01()
1564 } else if (mac->mac_phy.rev == 1 || in bwn_phy_lp_bbinit_r01()
1565 (sc->sc_board_info.board_flags & BHND_BFL_FEM)) { in bwn_phy_lp_bbinit_r01()
1567 BWN_PHY_SETMASK(mac, v4[i].offset, v4[i].mask, in bwn_phy_lp_bbinit_r01()
1571 BWN_PHY_SETMASK(mac, v5[i].offset, v5[i].mask, in bwn_phy_lp_bbinit_r01()
1574 if (mac->mac_phy.rev == 1 && in bwn_phy_lp_bbinit_r01()
1575 (sc->sc_board_info.board_flags & BHND_BFL_PAREF)) { in bwn_phy_lp_bbinit_r01()
1581 if ((sc->sc_board_info.board_flags & BHND_BFL_FEM_BT) && in bwn_phy_lp_bbinit_r01()
1582 (sc->sc_cid.chip_id == BHND_CHIPID_BCM5354) && in bwn_phy_lp_bbinit_r01()
1583 (sc->sc_cid.chip_pkg == BHND_PKGID_BCM4712SMALL)) { in bwn_phy_lp_bbinit_r01()
1589 if (IEEE80211_IS_CHAN_2GHZ(ic->ic_curchan)) { in bwn_phy_lp_bbinit_r01()
1602 if (mac->mac_phy.rev == 1) { in bwn_phy_lp_bbinit_r01()
1627 (((800000000 * (div) + (freq)) / (2 * (freq)) - 8) & 0xff) in bwn_phy_lp_b2062_init()
1629 ((((100 * (freq) + 16000000 * (div)) / (32000000 * (div))) - 1) & 0xff) in bwn_phy_lp_b2062_init()
1631 ((((2 * (freq) + 1000000 * (div)) / (2000000 * (div))) - 1) & 0xff) in bwn_phy_lp_b2062_init()
1632 struct bwn_phy_lp *plp = &mac->mac_phy.phy_lp; in bwn_phy_lp_b2062_init()
1633 struct bwn_softc *sc = mac->mac_sc; in bwn_phy_lp_b2062_init()
1634 struct ieee80211com *ic = &sc->sc_ic; in bwn_phy_lp_b2062_init()
1659 error = bhnd_get_clock_freq(sc->sc_dev, BHND_CLOCK_ALP, &xtalfreq); in bwn_phy_lp_b2062_init()
1661 device_printf(sc->sc_dev, "failed to fetch clock frequency: %d", in bwn_phy_lp_b2062_init()
1670 if (mac->mac_phy.rev > 0) in bwn_phy_lp_b2062_init()
1673 if (IEEE80211_IS_CHAN_2GHZ(ic->ic_curchan)) in bwn_phy_lp_b2062_init()
1679 plp->plp_div = 1; in bwn_phy_lp_b2062_init()
1682 plp->plp_div = 2; in bwn_phy_lp_b2062_init()
1687 CALC_CTL7(xtalfreq, plp->plp_div)); in bwn_phy_lp_b2062_init()
1689 CALC_CTL18(xtalfreq, plp->plp_div)); in bwn_phy_lp_b2062_init()
1691 CALC_CTL19(xtalfreq, plp->plp_div)); in bwn_phy_lp_b2062_init()
1693 ref = (1000 * plp->plp_div + 2 * xtalfreq) / (2000 * plp->plp_div); in bwn_phy_lp_b2062_init()
1702 f = &freqdata_tab[N(freqdata_tab) - 1]; in bwn_phy_lp_b2062_init()
1704 ((uint16_t)(f->value[1]) << 4) | f->value[0]); in bwn_phy_lp_b2062_init()
1706 ((uint16_t)(f->value[3]) << 4) | f->value[2]); in bwn_phy_lp_b2062_init()
1707 BWN_RF_WRITE(mac, BWN_B2062_S_RFPLLCTL10, f->value[4]); in bwn_phy_lp_b2062_init()
1708 BWN_RF_WRITE(mac, BWN_B2062_S_RFPLLCTL11, f->value[5]); in bwn_phy_lp_b2062_init()
1728 if (mac->mac_phy.rev == 2) { in bwn_phy_lp_b2063_init()
1743 struct bwn_softc *sc = mac->mac_sc; in bwn_phy_lp_rxcal_r2()
1765 error = bhnd_get_clock_freq(sc->sc_dev, BHND_CLOCK_ALP, &freqxtal); in bwn_phy_lp_rxcal_r2()
1767 device_printf(sc->sc_dev, "failed to fetch clock frequency: %d", in bwn_phy_lp_rxcal_r2()
1815 struct bwn_phy_lp *plp = &mac->mac_phy.phy_lp; in bwn_phy_lp_rccal_r12()
1816 struct bwn_softc *sc = mac->mac_sc; in bwn_phy_lp_rccal_r12()
1832 device_printf(sc->sc_dev, in bwn_phy_lp_rccal_r12()
1848 txpctlmode = plp->plp_txpctlmode; in bwn_phy_lp_rccal_r12()
1879 if (loopback == -1) in bwn_phy_lp_rccal_r12()
1897 ipwr = ((pwrtbl[j - 5] >> 3) + 1) >> 1; in bwn_phy_lp_rccal_r12()
1900 sum += ((ipwr - npwr) * (ipwr - npwr)); in bwn_phy_lp_rccal_r12()
1902 plp->plp_rccap = i; in bwn_phy_lp_rccal_r12()
1926 if (plp->plp_rccap) in bwn_phy_lp_rccal_r12()
1935 struct bwn_phy_lp *plp = &mac->mac_phy.phy_lp; in bwn_phy_lp_set_rccap()
1936 uint8_t rc_cap = (plp->plp_rccap & 0x1f) >> 1; in bwn_phy_lp_set_rccap()
1938 if (mac->mac_phy.rev == 1) in bwn_phy_lp_set_rccap()
1942 MAX(plp->plp_rccap - 4, 0x80)); in bwn_phy_lp_set_rccap()
1945 ((plp->plp_rccap & 0x1f) >> 2) | 0x80); in bwn_phy_lp_set_rccap()
1960 r = (r << 1) - div; in bwn_phy_lp_roundup()
1971 struct bwn_softc *sc = mac->mac_sc; in bwn_phy_lp_b2062_reset_pllbias()
1975 if (sc->sc_cid.chip_id == BHND_CHIPID_BCM5354) { in bwn_phy_lp_b2062_reset_pllbias()
1998 struct bwn_softc *sc = mac->mac_sc; in bwn_phy_lp_b2062_tblinit()
1999 struct ieee80211com *ic = &sc->sc_ic; in bwn_phy_lp_b2062_tblinit()
2054 if (IEEE80211_IS_CHAN_2GHZ(ic->ic_curchan)) { in bwn_phy_lp_b2062_tblinit()
2055 if (br->br_flags & FLAG_G) in bwn_phy_lp_b2062_tblinit()
2056 BWN_RF_WRITE(mac, br->br_offset, br->br_valueg); in bwn_phy_lp_b2062_tblinit()
2058 if (br->br_flags & FLAG_A) in bwn_phy_lp_b2062_tblinit()
2059 BWN_RF_WRITE(mac, br->br_offset, br->br_valuea); in bwn_phy_lp_b2062_tblinit()
2071 struct bwn_softc *sc = mac->mac_sc; in bwn_phy_lp_b2063_tblinit()
2072 struct ieee80211com *ic = &sc->sc_ic; in bwn_phy_lp_b2063_tblinit()
2122 if (IEEE80211_IS_CHAN_2GHZ(ic->ic_curchan)) { in bwn_phy_lp_b2063_tblinit()
2123 if (br->br_flags & FLAG_G) in bwn_phy_lp_b2063_tblinit()
2124 BWN_RF_WRITE(mac, br->br_offset, br->br_valueg); in bwn_phy_lp_b2063_tblinit()
2126 if (br->br_flags & FLAG_A) in bwn_phy_lp_b2063_tblinit()
2127 BWN_RF_WRITE(mac, br->br_offset, br->br_valuea); in bwn_phy_lp_b2063_tblinit()
2139 uint32_t offset, type; in bwn_tab_read_multi() local
2143 offset = BWN_TAB_GETOFFSET(typenoffset); in bwn_tab_read_multi()
2144 KASSERT(offset <= 0xffff, ("%s:%d: fail", __func__, __LINE__)); in bwn_tab_read_multi()
2146 BWN_PHY_WRITE(mac, BWN_PHY_TABLE_ADDR, offset); in bwn_tab_read_multi()
2177 uint32_t offset, type, value; in bwn_tab_write_multi() local
2182 offset = BWN_TAB_GETOFFSET(typenoffset); in bwn_tab_write_multi()
2183 KASSERT(offset <= 0xffff, ("%s:%d: fail", __func__, __LINE__)); in bwn_tab_write_multi()
2185 BWN_PHY_WRITE(mac, BWN_PHY_TABLE_ADDR, offset); in bwn_tab_write_multi()
2222 if (mac->mac_phy.rev < 2) { in bwn_phy_lp_get_txgain()
2250 if (mac->mac_phy.rev < 2) { in bwn_phy_lp_set_txgain()
2252 (tg->tg_pad << 7) | (tg->tg_pga << 3) | tg->tg_gm); in bwn_phy_lp_set_txgain()
2253 bwn_phy_lp_set_txgain_dac(mac, tg->tg_dac); in bwn_phy_lp_set_txgain()
2260 (tg->tg_pga << 8) | tg->tg_gm); in bwn_phy_lp_set_txgain()
2262 tg->tg_pad | (pa << 6)); in bwn_phy_lp_set_txgain()
2263 BWN_PHY_WRITE(mac, BWN_PHY_OFDM(0xfc), (tg->tg_pga << 8) | tg->tg_gm); in bwn_phy_lp_set_txgain()
2265 tg->tg_pad | (pa << 8)); in bwn_phy_lp_set_txgain()
2266 bwn_phy_lp_set_txgain_dac(mac, tg->tg_dac); in bwn_phy_lp_set_txgain()
2289 struct bwn_softc *sc = mac->mac_sc; in bwn_phy_lp_set_rxgain()
2290 struct ieee80211com *ic = &sc->sc_ic; in bwn_phy_lp_set_rxgain()
2293 if (mac->mac_phy.rev < 2) { in bwn_phy_lp_set_rxgain()
2317 if (IEEE80211_IS_CHAN_2GHZ(ic->ic_curchan)) { in bwn_phy_lp_set_rxgain()
2329 if (mac->mac_phy.rev >= 2) { in bwn_phy_lp_set_rxgain()
2331 if (IEEE80211_IS_CHAN_2GHZ(ic->ic_curchan)) { in bwn_phy_lp_set_rxgain()
2343 struct bwn_phy_lp *plp = &mac->mac_phy.phy_lp; in bwn_phy_lp_set_deaf()
2346 plp->plp_crsusr_off = 1; in bwn_phy_lp_set_deaf()
2348 plp->plp_crssys_off = 1; in bwn_phy_lp_set_deaf()
2356 struct bwn_phy_lp *plp = &mac->mac_phy.phy_lp; in bwn_phy_lp_clear_deaf()
2357 struct bwn_softc *sc = mac->mac_sc; in bwn_phy_lp_clear_deaf()
2358 struct ieee80211com *ic = &sc->sc_ic; in bwn_phy_lp_clear_deaf()
2361 plp->plp_crsusr_off = 0; in bwn_phy_lp_clear_deaf()
2363 plp->plp_crssys_off = 0; in bwn_phy_lp_clear_deaf()
2365 if (plp->plp_crsusr_off || plp->plp_crssys_off) in bwn_phy_lp_clear_deaf()
2368 if (IEEE80211_IS_CHAN_2GHZ(ic->ic_curchan)) in bwn_phy_lp_clear_deaf()
2379 _t = _x - 20; \ in bwn_phy_lp_calc_rx_iq_comp()
2381 _v = ((_y << (30 - _x)) + (_z >> (1 + _t))) / (_z >> _t); \ in bwn_phy_lp_calc_rx_iq_comp()
2383 _v = ((_y << (30 - _x)) + (_z << (-1 - _t))) / (_z << -_t); \ in bwn_phy_lp_calc_rx_iq_comp()
2388 _t = _x - 11; \ in bwn_phy_lp_calc_rx_iq_comp()
2390 _v = (_y << (31 - _x)) / (_z >> _t); \ in bwn_phy_lp_calc_rx_iq_comp()
2392 _v = (_y << (31 - _x)) / (_z << -_t); \ in bwn_phy_lp_calc_rx_iq_comp()
2417 tmp[1] = -bwn_sqrt(mac, tmp[1] - (tmp[0] * tmp[0])); in bwn_phy_lp_calc_rx_iq_comp()
2596 KASSERT(mac->mac_phy.rev < 2, ("%s:%d: fail", __func__, __LINE__)); in bwn_phy_lp_tblinit_r01()
2608 if (mac->mac_phy.rev == 0) { in bwn_phy_lp_tblinit_r01()
2626 struct bwn_softc *sc = mac->mac_sc; in bwn_phy_lp_tblinit_r2()
2811 KASSERT(mac->mac_phy.rev < 2, ("%s:%d: fail", __func__, __LINE__)); in bwn_phy_lp_tblinit_r2()
2834 if (sc->sc_cid.chip_id == BHND_CHIPID_BCM4325 && in bwn_phy_lp_tblinit_r2()
2835 sc->sc_cid.chip_pkg == 0) { in bwn_phy_lp_tblinit_r2()
2849 struct bwn_softc *sc = mac->mac_sc; in bwn_phy_lp_tblinit_txgain()
2850 struct ieee80211com *ic = &sc->sc_ic; in bwn_phy_lp_tblinit_txgain()
3451 if (mac->mac_phy.rev != 0 && mac->mac_phy.rev != 1) { in bwn_phy_lp_tblinit_txgain()
3452 if (sc->sc_board_info.board_flags & BHND_BFL_NOPA) in bwn_phy_lp_tblinit_txgain()
3454 else if (IEEE80211_IS_CHAN_2GHZ(ic->ic_curchan)) in bwn_phy_lp_tblinit_txgain()
3463 if (mac->mac_phy.rev == 0) { in bwn_phy_lp_tblinit_txgain()
3464 if ((sc->sc_board_info.board_flags & BHND_BFL_NOPA) || in bwn_phy_lp_tblinit_txgain()
3465 (sc->sc_board_info.board_flags & BHND_BFL_HGPA)) in bwn_phy_lp_tblinit_txgain()
3467 else if (IEEE80211_IS_CHAN_2GHZ(ic->ic_curchan)) in bwn_phy_lp_tblinit_txgain()
3476 if ((sc->sc_board_info.board_flags & BHND_BFL_NOPA) || in bwn_phy_lp_tblinit_txgain()
3477 (sc->sc_board_info.board_flags & BHND_BFL_HGPA)) in bwn_phy_lp_tblinit_txgain()
3479 else if (IEEE80211_IS_CHAN_2GHZ(ic->ic_curchan)) in bwn_phy_lp_tblinit_txgain()
3488 uint32_t offset, type; in bwn_tab_write() local
3491 offset = BWN_TAB_GETOFFSET(typeoffset); in bwn_tab_write()
3492 KASSERT(offset <= 0xffff, ("%s:%d: fail", __func__, __LINE__)); in bwn_tab_write()
3497 BWN_PHY_WRITE(mac, BWN_PHY_TABLE_ADDR, offset); in bwn_tab_write()
3503 BWN_PHY_WRITE(mac, BWN_PHY_TABLE_ADDR, offset); in bwn_tab_write()
3507 BWN_PHY_WRITE(mac, BWN_PHY_TABLE_ADDR, offset); in bwn_tab_write()
3520 int i, index = -1; in bwn_phy_lp_loopback()
3598 ie->ie_iqprod = BWN_PHY_READ(mac, BWN_PHY_IQ_ACC_HI_ADDR); in bwn_phy_lp_rx_iq_est()
3599 ie->ie_iqprod <<= 16; in bwn_phy_lp_rx_iq_est()
3600 ie->ie_iqprod |= BWN_PHY_READ(mac, BWN_PHY_IQ_ACC_LO_ADDR); in bwn_phy_lp_rx_iq_est()
3601 ie->ie_ipwr = BWN_PHY_READ(mac, BWN_PHY_IQ_I_PWR_ACC_HI_ADDR); in bwn_phy_lp_rx_iq_est()
3602 ie->ie_ipwr <<= 16; in bwn_phy_lp_rx_iq_est()
3603 ie->ie_ipwr |= BWN_PHY_READ(mac, BWN_PHY_IQ_I_PWR_ACC_LO_ADDR); in bwn_phy_lp_rx_iq_est()
3604 ie->ie_qpwr = BWN_PHY_READ(mac, BWN_PHY_IQ_Q_PWR_ACC_HI_ADDR); in bwn_phy_lp_rx_iq_est()
3605 ie->ie_qpwr <<= 16; in bwn_phy_lp_rx_iq_est()
3606 ie->ie_qpwr |= BWN_PHY_READ(mac, BWN_PHY_IQ_Q_PWR_ACC_LO_ADDR); in bwn_phy_lp_rx_iq_est()
3615 uint32_t offset, type, value; in bwn_tab_read() local
3618 offset = BWN_TAB_GETOFFSET(typeoffset); in bwn_tab_read()
3619 KASSERT(offset <= 0xffff, ("%s:%d: fail", __func__, __LINE__)); in bwn_tab_read()
3623 BWN_PHY_WRITE(mac, BWN_PHY_TABLE_ADDR, offset); in bwn_tab_read()
3627 BWN_PHY_WRITE(mac, BWN_PHY_TABLE_ADDR, offset); in bwn_tab_read()
3631 BWN_PHY_WRITE(mac, BWN_PHY_TABLE_ADDR, offset); in bwn_tab_read()
3674 if (mac->mac_phy.rev < 2) in bwn_phy_lp_set_txgain_override()
3702 bwn_phy_lp_gaintbl_write_multi(struct bwn_mac *mac, int offset, int count, in bwn_phy_lp_gaintbl_write_multi() argument
3707 for (i = offset; i < count; i++) in bwn_phy_lp_gaintbl_write_multi()
3712 bwn_phy_lp_gaintbl_write(struct bwn_mac *mac, int offset, in bwn_phy_lp_gaintbl_write() argument
3716 if (mac->mac_phy.rev >= 2) in bwn_phy_lp_gaintbl_write()
3717 bwn_phy_lp_gaintbl_write_r2(mac, offset, data); in bwn_phy_lp_gaintbl_write()
3719 bwn_phy_lp_gaintbl_write_r01(mac, offset, data); in bwn_phy_lp_gaintbl_write()
3723 bwn_phy_lp_gaintbl_write_r2(struct bwn_mac *mac, int offset, in bwn_phy_lp_gaintbl_write_r2() argument
3726 struct bwn_softc *sc = mac->mac_sc; in bwn_phy_lp_gaintbl_write_r2()
3727 struct ieee80211com *ic = &sc->sc_ic; in bwn_phy_lp_gaintbl_write_r2()
3730 KASSERT(mac->mac_phy.rev >= 2, ("%s:%d: fail", __func__, __LINE__)); in bwn_phy_lp_gaintbl_write_r2()
3733 if (mac->mac_phy.rev >= 3) { in bwn_phy_lp_gaintbl_write_r2()
3734 tmp |= ((IEEE80211_IS_CHAN_5GHZ(ic->ic_curchan)) ? in bwn_phy_lp_gaintbl_write_r2()
3737 tmp |= ((IEEE80211_IS_CHAN_5GHZ(ic->ic_curchan)) ? in bwn_phy_lp_gaintbl_write_r2()
3740 bwn_tab_write(mac, BWN_TAB_4(7, 0xc0 + offset), tmp); in bwn_phy_lp_gaintbl_write_r2()
3741 bwn_tab_write(mac, BWN_TAB_4(7, 0x140 + offset), in bwn_phy_lp_gaintbl_write_r2()
3746 bwn_phy_lp_gaintbl_write_r01(struct bwn_mac *mac, int offset, in bwn_phy_lp_gaintbl_write_r01() argument
3750 KASSERT(mac->mac_phy.rev < 2, ("%s:%d: fail", __func__, __LINE__)); in bwn_phy_lp_gaintbl_write_r01()
3752 bwn_tab_write(mac, BWN_TAB_4(10, 0xc0 + offset), in bwn_phy_lp_gaintbl_write_r01()
3755 bwn_tab_write(mac, BWN_TAB_4(10, 0x140 + offset), te.te_bbmult << 20); in bwn_phy_lp_gaintbl_write_r01()